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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dpllgt215.c36 *P = info->vco1.max_freq / freq; in gt215_pll_calc()
37 if (*P > info->max_p) in gt215_pll_calc()
38 *P = info->max_p; in gt215_pll_calc()
39 if (*P < info->min_p) in gt215_pll_calc()
40 *P = info->min_p; in gt215_pll_calc()
42 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; in gt215_pll_calc()
43 lM = max(lM, (int)info->vco1.min_m); in gt215_pll_calc()
44 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; in gt215_pll_calc()
45 hM = min(hM, (int)info->vco1.max_m); in gt215_pll_calc()
50 N = tmp / info->refclk; in gt215_pll_calc()
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt7620-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt7620-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
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/openbmc/qemu/hw/timer/
H A Darmv7m_systick.c4 * Copyright (c) 2006-2007 CodeSourcery.
17 #include "hw/qdev-clock.h"
31 #define SYSCALIB_TENMS ((1U << 24) - 1)
39 if (s->control & SYSTICK_CLKSOURCE) { in systick_set_period_from_clock()
40 ptimer_set_period_from_clock(s->ptimer, s->cpuclk, 1); in systick_set_period_from_clock()
42 ptimer_set_period_from_clock(s->ptimer, s->refclk, 1); in systick_set_period_from_clock()
52 s->control |= SYSTICK_COUNTFLAG; in systick_timer_tick()
53 if (s->control & SYSTICK_TICKINT) { in systick_timer_tick()
55 qemu_irq_pulse(s->irq); in systick_timer_tick()
57 if (ptimer_get_limit(s->ptimer) == 0) { in systick_timer_tick()
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/openbmc/linux/drivers/phy/ti/
H A Dphy-dm816x-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
47 struct clk *refclk; member
55 otg->host = host; in dm816x_usb_phy_set_host()
57 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_host()
65 otg->gadget = gadget; in dm816x_usb_phy_set_peripheral()
67 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_peripheral()
77 if (clk_get_rate(phy->refclk) != 24000000) in dm816x_usb_phy_init()
78 dev_warn(phy->dev, "nonstandard phy refclk\n"); in dm816x_usb_phy_init()
81 regmap_update_bits(phy->syscon, phy->usb_ctrl, in dm816x_usb_phy_init()
86 regmap_read(phy->syscon, phy->usb_ctrl, &val); in dm816x_usb_phy_init()
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H A Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
171 struct clk *refclk; member
215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
241 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
266 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
302 struct pipe3_dpll_map *dpll_map = phy->dpll_map; in ti_pipe3_get_dpll_params()
304 rate = clk_get_rate(phy->sys_clk); in ti_pipe3_get_dpll_params()
306 for (; dpll_map->rate; dpll_map++) { in ti_pipe3_get_dpll_params()
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c2 * Copyright © 2006-2017 Intel Corporation
84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
91 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
97 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
103 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
109 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
115 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
121 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
127 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
133 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
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H A Dintel_dpll.c1 // SPDX-License-Identifier: MIT
193 * the range value for them is (actual_value - 2).
234 /* LVDS 100mhz refclk limits. */
305 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
306 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
310 * divided-down version of it.
313 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
315 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
316 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
317 if (WARN_ON(clock->n == 0 || clock->p == 0)) in pnv_calc_dpll_params()
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H A Dintel_dpll.h1 /* SPDX-License-Identifier: MIT */
23 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
24 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dsmsc,usb3503.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SMSC USB3503 High-Speed Hub Controller
10 - Dongjin Kim <tobetter@gmail.com>
15 - smsc,usb3503
16 - smsc,usb3503a
17 - smsc,usb3803
22 connect-gpios:
27 intn-gpios:
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H A Docteon-usb.txt7 - compatible: must be "cavium,octeon-5750-usbn"
9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
21 - clock-frequency: speed of the USB reference clock. Allowed values are
24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
33 The main node must have one child node which describes the built-in
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/openbmc/u-boot/drivers/video/rockchip/
H A Drk_mipi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Author: Eric Gao <eric.gao@rock-chips.com>
19 #include <dm/uclass-internal.h>
33 ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), in rk_mipi_read_timing()
38 return -EINVAL; in rk_mipi_read_timing()
61 mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits))); in rk_mipi_dsi_write()
84 uintptr_t regs = priv->regs; in rk_mipi_dsi_enable()
85 u32 txbyte_clk = priv->txbyte_clk; in rk_mipi_dsi_enable()
86 u32 txesc_clk = priv->txesc_clk; in rk_mipi_dsi_enable()
91 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); in rk_mipi_dsi_enable()
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/openbmc/linux/drivers/gpu/drm/gma500/
H A Dgma_display.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2006-2011 Intel Corporation
44 int target, int refclk,
49 void (*clock)(int refclk, struct gma_clock_t *clock);
50 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
83 extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
84 extern void gma_clock(int refclk, struct gma_clock_t *clock);
89 struct drm_crtc *crtc, int target, int refclk,
H A Doaktrail_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
41 int refclk, struct gma_clock_t *best_clock);
45 int refclk, struct gma_clock_t *best_clock);
84 int refclk) in mrst_limit() argument
87 struct drm_device *dev = crtc->dev; in mrst_limit()
92 switch (dev_priv->core_freq) { in mrst_limit()
107 dev_err(dev->dev, "mrst_limit Wrong display type.\n"); in mrst_limit()
113 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
114 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
116 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
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H A Dcdv_intel_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
25 int refclk, struct gma_clock_t *best_clock);
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
118 ret__ = -ETIMEDOUT; \
217 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
272 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
288 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
290 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dccg.c34 (dccg_dcn->regs->reg)
38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
41 dccg_dcn->base.ctx
43 dccg->ctx->logger
161 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
170 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
179 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
188 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
203 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
210 int req_dtbclk_khz = params->pixclk_khz / 4; in dccg32_set_dtbclk_dto()
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/openbmc/qemu/hw/arm/
H A Dstm32f100_soc.c30 #include "exec/address-spaces.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-clock.h"
51 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in stm32f100_soc_initfn()
54 object_initialize_child(obj, "usart[*]", &s->usart[i], in stm32f100_soc_initfn()
59 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); in stm32f100_soc_initfn()
62 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in stm32f100_soc_initfn()
63 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); in stm32f100_soc_initfn()
76 * We use s->refclk internally and only define it with qdev_init_clock_in() in stm32f100_soc_realize()
80 if (clock_has_source(s->refclk)) { in stm32f100_soc_realize()
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H A Dstm32f205_soc.c29 #include "exec/address-spaces.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/qdev-clock.h"
55 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in stm32f205_soc_initfn()
57 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG); in stm32f205_soc_initfn()
60 object_initialize_child(obj, "usart[*]", &s->usart[i], in stm32f205_soc_initfn()
65 object_initialize_child(obj, "timer[*]", &s->timer[i], in stm32f205_soc_initfn()
69 s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); in stm32f205_soc_initfn()
72 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); in stm32f205_soc_initfn()
76 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); in stm32f205_soc_initfn()
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H A Dmsf2-soc.c4 * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
28 #include "exec/address-spaces.h"
29 #include "hw/char/serial-mm.h"
30 #include "hw/arm/msf2-soc.h"
32 #include "hw/qdev-clock.h"
66 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); in m2sxxx_soc_initfn()
68 object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG); in m2sxxx_soc_initfn()
70 object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER); in m2sxxx_soc_initfn()
73 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI); in m2sxxx_soc_initfn()
76 object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC); in m2sxxx_soc_initfn()
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/openbmc/linux/drivers/net/ethernet/arc/
H A Demac_rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * emac-rockchip.c - Rockchip EMAC specific glue layer
32 struct clk *refclk; member
39 u32 speed_offset = emac->soc_data->grf_speed_offset; in emac_rockchip_set_mac_speed()
55 err = regmap_write(emac->grf, emac->soc_data->grf_offset, data); in emac_rockchip_set_mac_speed()
77 .compatible = "rockchip,rk3036-emac",
81 .compatible = "rockchip,rk3066-emac",
85 .compatible = "rockchip,rk3188-emac",
95 struct device *dev = &pdev->dev; in emac_rockchip_probe()
103 if (!pdev->dev.of_node) in emac_rockchip_probe()
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/openbmc/linux/drivers/gpu/drm/loongson/
H A Dlsdc_pixpll.h1 /* SPDX-License-Identifier: GPL-2.0+ */
14 * refclk: reference frequency, 100 MHz from external oscillator
19 * refclk +-----------+ +------------------+ +---------+ outclk
20 * ---+---> | Prescaler | ---> | Clock Multiplier | ---> | divider | -------->
21 * | +-----------+ +------------------+ +---------+ ^
27 * +---- bypass (bypass above software configurable clock if set) ----+
29 * outclk = refclk / div_ref * loopc / div_out;
38 * 1) 20 MHz <= refclk / div_ref <= 40Mhz
39 * 2) 1.2 GHz <= refclk /div_out * loopc <= 3.2 Ghz
/openbmc/linux/Documentation/devicetree/bindings/mips/cavium/
H A Ductl.txt4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
28 #size-cells = <2>;
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/openbmc/linux/arch/mips/bcm63xx/
H A Dclk.c33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
92 if (clk->id == 0) in enetx_set()
403 return clk->rate; in clk_get_rate()
423 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
424 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
440 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
441 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
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/openbmc/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
104 /* Refclk selection parameters */
190 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
204 * struct xpsgtr_phy - representation of a lane
211 * @refclk: reference clock index
220 unsigned int refclk; member
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dccg.c1 // SPDX-License-Identifier: MIT
37 (dccg_dcn->regs->reg)
41 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
44 dccg_dcn->base.ctx
46 dccg->ctx->logger
161 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
170 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
179 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
188 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
203 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
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