Lines Matching +full:- +full:refclk
1 // SPDX-License-Identifier: MIT
193 * the range value for them is (actual_value - 2).
234 /* LVDS 100mhz refclk limits. */
305 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
306 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
310 * divided-down version of it.
313 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
315 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
316 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
317 if (WARN_ON(clock->n == 0 || clock->p == 0)) in pnv_calc_dpll_params()
319 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
320 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in pnv_calc_dpll_params()
322 return clock->dot; in pnv_calc_dpll_params()
327 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
330 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params() argument
332 clock->m = i9xx_dpll_compute_m(clock); in i9xx_calc_dpll_params()
333 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
334 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) in i9xx_calc_dpll_params()
336 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); in i9xx_calc_dpll_params()
337 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in i9xx_calc_dpll_params()
339 return clock->dot; in i9xx_calc_dpll_params()
342 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params() argument
344 clock->m = clock->m1 * clock->m2; in vlv_calc_dpll_params()
345 clock->p = clock->p1 * clock->p2 * 5; in vlv_calc_dpll_params()
346 if (WARN_ON(clock->n == 0 || clock->p == 0)) in vlv_calc_dpll_params()
348 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in vlv_calc_dpll_params()
349 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in vlv_calc_dpll_params()
351 return clock->dot; in vlv_calc_dpll_params()
354 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params() argument
356 clock->m = clock->m1 * clock->m2; in chv_calc_dpll_params()
357 clock->p = clock->p1 * clock->p2 * 5; in chv_calc_dpll_params()
358 if (WARN_ON(clock->n == 0 || clock->p == 0)) in chv_calc_dpll_params()
360 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), in chv_calc_dpll_params()
361 clock->n << 22); in chv_calc_dpll_params()
362 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in chv_calc_dpll_params()
364 return clock->dot; in chv_calc_dpll_params()
368 * Returns whether the given set of divisors are valid for a given refclk with
375 if (clock->n < limit->n.min || limit->n.max < clock->n) in intel_pll_is_valid()
377 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in intel_pll_is_valid()
379 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in intel_pll_is_valid()
381 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in intel_pll_is_valid()
385 if (clock->m1 <= clock->m2) in intel_pll_is_valid()
389 if (clock->p < limit->p.min || limit->p.max < clock->p) in intel_pll_is_valid()
391 if (clock->m < limit->m.min || limit->m.max < clock->m) in intel_pll_is_valid()
395 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in intel_pll_is_valid()
400 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in intel_pll_is_valid()
411 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in i9xx_select_p2_div()
415 * For LVDS just rely on its current settings for dual-channel. in i9xx_select_p2_div()
420 return limit->p2.p2_fast; in i9xx_select_p2_div()
422 return limit->p2.p2_slow; in i9xx_select_p2_div()
424 if (target < limit->p2.dot_limit) in i9xx_select_p2_div()
425 return limit->p2.p2_slow; in i9xx_select_p2_div()
427 return limit->p2.p2_fast; in i9xx_select_p2_div()
433 * refclk, or FALSE.
443 int target, int refclk, in i9xx_find_best_dpll() argument
447 struct drm_device *dev = crtc_state->uapi.crtc->dev; in i9xx_find_best_dpll()
455 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in i9xx_find_best_dpll()
457 for (clock.m2 = limit->m2.min; in i9xx_find_best_dpll()
458 clock.m2 <= limit->m2.max; clock.m2++) { in i9xx_find_best_dpll()
461 for (clock.n = limit->n.min; in i9xx_find_best_dpll()
462 clock.n <= limit->n.max; clock.n++) { in i9xx_find_best_dpll()
463 for (clock.p1 = limit->p1.min; in i9xx_find_best_dpll()
464 clock.p1 <= limit->p1.max; clock.p1++) { in i9xx_find_best_dpll()
467 i9xx_calc_dpll_params(refclk, &clock); in i9xx_find_best_dpll()
473 clock.p != match_clock->p) in i9xx_find_best_dpll()
476 this_err = abs(clock.dot - target); in i9xx_find_best_dpll()
491 * refclk, or FALSE.
501 int target, int refclk, in pnv_find_best_dpll() argument
505 struct drm_device *dev = crtc_state->uapi.crtc->dev; in pnv_find_best_dpll()
513 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in pnv_find_best_dpll()
515 for (clock.m2 = limit->m2.min; in pnv_find_best_dpll()
516 clock.m2 <= limit->m2.max; clock.m2++) { in pnv_find_best_dpll()
517 for (clock.n = limit->n.min; in pnv_find_best_dpll()
518 clock.n <= limit->n.max; clock.n++) { in pnv_find_best_dpll()
519 for (clock.p1 = limit->p1.min; in pnv_find_best_dpll()
520 clock.p1 <= limit->p1.max; clock.p1++) { in pnv_find_best_dpll()
523 pnv_calc_dpll_params(refclk, &clock); in pnv_find_best_dpll()
529 clock.p != match_clock->p) in pnv_find_best_dpll()
532 this_err = abs(clock.dot - target); in pnv_find_best_dpll()
547 * refclk, or FALSE.
557 int target, int refclk, in g4x_find_best_dpll() argument
561 struct drm_device *dev = crtc_state->uapi.crtc->dev; in g4x_find_best_dpll()
572 max_n = limit->n.max; in g4x_find_best_dpll()
574 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in g4x_find_best_dpll()
576 for (clock.m1 = limit->m1.max; in g4x_find_best_dpll()
577 clock.m1 >= limit->m1.min; clock.m1--) { in g4x_find_best_dpll()
578 for (clock.m2 = limit->m2.max; in g4x_find_best_dpll()
579 clock.m2 >= limit->m2.min; clock.m2--) { in g4x_find_best_dpll()
580 for (clock.p1 = limit->p1.max; in g4x_find_best_dpll()
581 clock.p1 >= limit->p1.min; clock.p1--) { in g4x_find_best_dpll()
584 i9xx_calc_dpll_params(refclk, &clock); in g4x_find_best_dpll()
590 this_err = abs(clock.dot - target); in g4x_find_best_dpll()
621 return calculated_clock->p > best_clock->p; in vlv_PLL_is_optimal()
628 abs(target_freq - calculated_clock->dot), in vlv_PLL_is_optimal()
635 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { in vlv_PLL_is_optimal()
646 * refclk, or FALSE.
651 int target, int refclk, in vlv_find_best_dpll() argument
655 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_find_best_dpll()
656 struct drm_device *dev = crtc->base.dev; in vlv_find_best_dpll()
660 int max_n = min(limit->n.max, refclk / 19200); in vlv_find_best_dpll()
666 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in vlv_find_best_dpll()
667 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in vlv_find_best_dpll()
668 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; in vlv_find_best_dpll()
669 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in vlv_find_best_dpll()
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in vlv_find_best_dpll()
676 refclk * clock.m1); in vlv_find_best_dpll()
678 vlv_calc_dpll_params(refclk, &clock); in vlv_find_best_dpll()
704 * refclk, or FALSE.
709 int target, int refclk, in chv_find_best_dpll() argument
713 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_find_best_dpll()
714 struct drm_device *dev = crtc->base.dev; in chv_find_best_dpll()
725 * set to 2. If requires to support 200Mhz refclk, we need to in chv_find_best_dpll()
731 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in chv_find_best_dpll()
732 for (clock.p2 = limit->p2.p2_fast; in chv_find_best_dpll()
733 clock.p2 >= limit->p2.p2_slow; in chv_find_best_dpll()
734 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in chv_find_best_dpll()
740 refclk * clock.m1); in chv_find_best_dpll()
747 chv_calc_dpll_params(refclk, &clock); in chv_find_best_dpll()
769 int refclk = 100000; in bxt_find_best_dpll() local
772 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
778 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
783 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
790 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_update_pll_dividers()
791 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_update_pll_dividers()
802 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
803 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
810 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_compute_dpll()
811 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_compute_dpll()
825 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
838 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
839 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
841 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
842 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_compute_dpll()
844 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
845 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_compute_dpll()
848 switch (clock->p2) { in i9xx_compute_dpll()
862 WARN_ON(reduced_clock->p2 != clock->p2); in i9xx_compute_dpll()
867 if (crtc_state->sdvo_tv_clock) in i9xx_compute_dpll()
876 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
879 u32 dpll_md = (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
881 crtc_state->dpll_hw_state.dpll_md = dpll_md; in i9xx_compute_dpll()
889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i8xx_compute_dpll()
890 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i8xx_compute_dpll()
898 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
900 if (clock->p1 == 2) in i8xx_compute_dpll()
903 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
904 if (clock->p2 == 4) in i8xx_compute_dpll()
907 WARN_ON(reduced_clock->p1 != clock->p1); in i8xx_compute_dpll()
908 WARN_ON(reduced_clock->p2 != clock->p2); in i8xx_compute_dpll()
916 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." in i8xx_compute_dpll()
933 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
939 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in hsw_crtc_compute_clock()
959 if (!crtc_state->has_pch_encoder) in hsw_crtc_compute_clock()
960 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in hsw_crtc_compute_clock()
968 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in hsw_crtc_get_shared_dpll()
994 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in dg2_crtc_compute_clock()
1002 struct drm_i915_private *i915 = to_i915(state->base.dev); in mtl_crtc_compute_clock()
1007 enum phy phy = intel_port_to_phy(i915, encoder->port); in mtl_crtc_compute_clock()
1016 crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10); in mtl_crtc_compute_clock()
1018 crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20); in mtl_crtc_compute_clock()
1020 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in mtl_crtc_compute_clock()
1027 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1034 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_update_pll_dividers()
1035 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_update_pll_dividers()
1043 dev_priv->display.vbt.lvds_ssc_freq == 100000) || in ilk_update_pll_dividers()
1047 } else if (crtc_state->sdvo_tv_clock) { in ilk_update_pll_dividers()
1059 crtc_state->dpll_hw_state.fp0 = fp; in ilk_update_pll_dividers()
1060 crtc_state->dpll_hw_state.fp1 = fp2; in ilk_update_pll_dividers()
1067 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_compute_dpll()
1068 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_compute_dpll()
1080 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_compute_dpll()
1102 * this on ILK at all since it has a fixed DPLL<->pipe mapping. in ilk_compute_dpll()
1109 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1111 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1113 switch (clock->p2) { in ilk_compute_dpll()
1127 WARN_ON(reduced_clock->p2 != clock->p2); in ilk_compute_dpll()
1137 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1143 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in ilk_crtc_compute_clock()
1147 int refclk = 120000; in ilk_crtc_compute_clock() local
1151 if (!crtc_state->has_pch_encoder) in ilk_crtc_compute_clock()
1156 drm_dbg_kms(&dev_priv->drm, in ilk_crtc_compute_clock()
1158 dev_priv->display.vbt.lvds_ssc_freq); in ilk_crtc_compute_clock()
1159 refclk = dev_priv->display.vbt.lvds_ssc_freq; in ilk_crtc_compute_clock()
1163 if (refclk == 100000) in ilk_crtc_compute_clock()
1168 if (refclk == 100000) in ilk_crtc_compute_clock()
1177 if (!crtc_state->clock_set && in ilk_crtc_compute_clock()
1178 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1179 refclk, NULL, &crtc_state->dpll)) in ilk_crtc_compute_clock()
1180 return -EINVAL; in ilk_crtc_compute_clock()
1182 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1183 &crtc_state->dpll); in ilk_crtc_compute_clock()
1189 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1190 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in ilk_crtc_compute_clock()
1202 if (!crtc_state->has_pch_encoder) in ilk_crtc_get_shared_dpll()
1210 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_compute_dpll()
1212 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
1214 if (crtc->pipe != PIPE_A) in vlv_compute_dpll()
1215 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
1219 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
1222 crtc_state->dpll_hw_state.dpll_md = in vlv_compute_dpll()
1223 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in vlv_compute_dpll()
1228 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_compute_dpll()
1230 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
1232 if (crtc->pipe != PIPE_A) in chv_compute_dpll()
1233 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
1237 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
1239 crtc_state->dpll_hw_state.dpll_md = in chv_compute_dpll()
1240 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in chv_compute_dpll()
1249 int refclk = 100000; in chv_crtc_compute_clock() local
1251 if (!crtc_state->clock_set && in chv_crtc_compute_clock()
1252 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1253 refclk, NULL, &crtc_state->dpll)) in chv_crtc_compute_clock()
1254 return -EINVAL; in chv_crtc_compute_clock()
1262 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1263 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in chv_crtc_compute_clock()
1274 int refclk = 100000; in vlv_crtc_compute_clock() local
1276 if (!crtc_state->clock_set && in vlv_crtc_compute_clock()
1277 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1278 refclk, NULL, &crtc_state->dpll)) { in vlv_crtc_compute_clock()
1279 return -EINVAL; in vlv_crtc_compute_clock()
1288 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1289 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in vlv_crtc_compute_clock()
1297 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in g4x_crtc_compute_clock()
1301 int refclk = 96000; in g4x_crtc_compute_clock() local
1305 refclk = dev_priv->display.vbt.lvds_ssc_freq; in g4x_crtc_compute_clock()
1306 drm_dbg_kms(&dev_priv->drm, in g4x_crtc_compute_clock()
1308 refclk); in g4x_crtc_compute_clock()
1325 if (!crtc_state->clock_set && in g4x_crtc_compute_clock()
1326 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1327 refclk, NULL, &crtc_state->dpll)) in g4x_crtc_compute_clock()
1328 return -EINVAL; in g4x_crtc_compute_clock()
1330 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1331 &crtc_state->dpll); in g4x_crtc_compute_clock()
1333 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1336 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in g4x_crtc_compute_clock()
1344 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in pnv_crtc_compute_clock()
1348 int refclk = 96000; in pnv_crtc_compute_clock() local
1352 refclk = dev_priv->display.vbt.lvds_ssc_freq; in pnv_crtc_compute_clock()
1353 drm_dbg_kms(&dev_priv->drm, in pnv_crtc_compute_clock()
1355 refclk); in pnv_crtc_compute_clock()
1363 if (!crtc_state->clock_set && in pnv_crtc_compute_clock()
1364 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
1365 refclk, NULL, &crtc_state->dpll)) in pnv_crtc_compute_clock()
1366 return -EINVAL; in pnv_crtc_compute_clock()
1368 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1369 &crtc_state->dpll); in pnv_crtc_compute_clock()
1371 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1372 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in pnv_crtc_compute_clock()
1380 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in i9xx_crtc_compute_clock()
1384 int refclk = 96000; in i9xx_crtc_compute_clock() local
1388 refclk = dev_priv->display.vbt.lvds_ssc_freq; in i9xx_crtc_compute_clock()
1389 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_compute_clock()
1391 refclk); in i9xx_crtc_compute_clock()
1399 if (!crtc_state->clock_set && in i9xx_crtc_compute_clock()
1400 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
1401 refclk, NULL, &crtc_state->dpll)) in i9xx_crtc_compute_clock()
1402 return -EINVAL; in i9xx_crtc_compute_clock()
1404 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1405 &crtc_state->dpll); in i9xx_crtc_compute_clock()
1407 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1410 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in i9xx_crtc_compute_clock()
1418 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in i8xx_crtc_compute_clock()
1422 int refclk = 48000; in i8xx_crtc_compute_clock() local
1426 refclk = dev_priv->display.vbt.lvds_ssc_freq; in i8xx_crtc_compute_clock()
1427 drm_dbg_kms(&dev_priv->drm, in i8xx_crtc_compute_clock()
1429 refclk); in i8xx_crtc_compute_clock()
1439 if (!crtc_state->clock_set && in i8xx_crtc_compute_clock()
1440 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i8xx_crtc_compute_clock()
1441 refclk, NULL, &crtc_state->dpll)) in i8xx_crtc_compute_clock()
1442 return -EINVAL; in i8xx_crtc_compute_clock()
1444 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
1445 &crtc_state->dpll); in i8xx_crtc_compute_clock()
1447 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
1448 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in i8xx_crtc_compute_clock()
1498 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dpll_crtc_compute_clock()
1503 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); in intel_dpll_crtc_compute_clock()
1505 memset(&crtc_state->dpll_hw_state, 0, in intel_dpll_crtc_compute_clock()
1506 sizeof(crtc_state->dpll_hw_state)); in intel_dpll_crtc_compute_clock()
1508 if (!crtc_state->hw.enable) in intel_dpll_crtc_compute_clock()
1511 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); in intel_dpll_crtc_compute_clock()
1513 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", in intel_dpll_crtc_compute_clock()
1514 crtc->base.base.id, crtc->base.name); in intel_dpll_crtc_compute_clock()
1524 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dpll_crtc_get_shared_dpll()
1529 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); in intel_dpll_crtc_get_shared_dpll()
1530 drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); in intel_dpll_crtc_get_shared_dpll()
1532 if (!crtc_state->hw.enable || crtc_state->shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1535 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1538 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); in intel_dpll_crtc_get_shared_dpll()
1540 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", in intel_dpll_crtc_get_shared_dpll()
1541 crtc->base.base.id, crtc->base.name); in intel_dpll_crtc_get_shared_dpll()
1552 dev_priv->display.funcs.dpll = &mtl_dpll_funcs; in intel_dpll_init_clock_hook()
1554 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; in intel_dpll_init_clock_hook()
1556 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; in intel_dpll_init_clock_hook()
1558 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; in intel_dpll_init_clock_hook()
1560 dev_priv->display.funcs.dpll = &chv_dpll_funcs; in intel_dpll_init_clock_hook()
1562 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; in intel_dpll_init_clock_hook()
1564 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; in intel_dpll_init_clock_hook()
1566 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; in intel_dpll_init_clock_hook()
1568 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; in intel_dpll_init_clock_hook()
1570 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; in intel_dpll_init_clock_hook()
1583 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_enable_pll()
1584 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_enable_pll()
1585 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll()
1586 enum pipe pipe = crtc->pipe; in i9xx_enable_pll()
1589 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_enable_pll()
1595 intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0); in i9xx_enable_pll()
1596 intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1); in i9xx_enable_pll()
1612 crtc_state->dpll_hw_state.dpll_md); in i9xx_enable_pll()
1661 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_prepare_pll()
1662 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_prepare_pll()
1663 enum pipe pipe = crtc->pipe; in vlv_prepare_pll()
1670 bestn = crtc_state->dpll.n; in vlv_prepare_pll()
1671 bestm1 = crtc_state->dpll.m1; in vlv_prepare_pll()
1672 bestm2 = crtc_state->dpll.m2; in vlv_prepare_pll()
1673 bestp1 = crtc_state->dpll.p1; in vlv_prepare_pll()
1674 bestp2 = crtc_state->dpll.p2; in vlv_prepare_pll()
1711 if (crtc_state->port_clock == 162000 || in vlv_prepare_pll()
1751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in _vlv_enable_pll()
1752 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _vlv_enable_pll()
1753 enum pipe pipe = crtc->pipe; in _vlv_enable_pll()
1755 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _vlv_enable_pll()
1760 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); in _vlv_enable_pll()
1765 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_enable_pll()
1766 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_enable_pll()
1767 enum pipe pipe = crtc->pipe; in vlv_enable_pll()
1769 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in vlv_enable_pll()
1774 /* Enable Refclk */ in vlv_enable_pll()
1776 crtc_state->dpll_hw_state.dpll & in vlv_enable_pll()
1779 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
1785 crtc_state->dpll_hw_state.dpll_md); in vlv_enable_pll()
1791 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_prepare_pll()
1792 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_prepare_pll()
1793 enum pipe pipe = crtc->pipe; in chv_prepare_pll()
1800 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; in chv_prepare_pll()
1801 bestm2 = crtc_state->dpll.m2 >> 22; in chv_prepare_pll()
1802 bestp1 = crtc_state->dpll.p1; in chv_prepare_pll()
1803 bestp2 = crtc_state->dpll.p2; in chv_prepare_pll()
1804 vco = crtc_state->dpll.vco; in chv_prepare_pll()
1817 /* Feedback post-divider - m2 */ in chv_prepare_pll()
1820 /* Feedback refclk divider - n and m1 */ in chv_prepare_pll()
1885 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in _chv_enable_pll()
1886 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _chv_enable_pll()
1887 enum pipe pipe = crtc->pipe; in _chv_enable_pll()
1906 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _chv_enable_pll()
1910 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); in _chv_enable_pll()
1915 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_enable_pll()
1916 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_enable_pll()
1917 enum pipe pipe = crtc->pipe; in chv_enable_pll()
1919 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in chv_enable_pll()
1924 /* Enable Refclk and SSC */ in chv_enable_pll()
1926 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
1928 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in chv_enable_pll()
1942 crtc_state->dpll_hw_state.dpll_md); in chv_enable_pll()
1944 dev_priv->display.state.chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md; in chv_enable_pll()
1950 drm_WARN_ON(&dev_priv->drm, in chv_enable_pll()
1955 crtc_state->dpll_hw_state.dpll_md); in chv_enable_pll()
1961 * vlv_force_pll_on - forcibly enable just the PLL
1978 return -ENOMEM; in vlv_force_pll_on()
1980 crtc_state->cpu_transcoder = (enum transcoder)pipe; in vlv_force_pll_on()
1981 crtc_state->pixel_multiplier = 1; in vlv_force_pll_on()
1982 crtc_state->dpll = *dpll; in vlv_force_pll_on()
1983 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); in vlv_force_pll_on()
2042 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_disable_pll()
2043 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_disable_pll()
2044 enum pipe pipe = crtc->pipe; in i9xx_disable_pll()
2051 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_disable_pll()
2059 * vlv_force_pll_off - forcibly disable just the PLL
2074 /* Only for pre-ILK configs */