30 #include "exec/address-spaces.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-clock.h"
51     object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);  in stm32f100_soc_initfn()
54         object_initialize_child(obj, "usart[*]", &s->usart[i],  in stm32f100_soc_initfn()
59         object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);  in stm32f100_soc_initfn()
62     s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);  in stm32f100_soc_initfn()
63     s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);  in stm32f100_soc_initfn()
76      * We use s->refclk internally and only define it with qdev_init_clock_in()  in stm32f100_soc_realize()
80     if (clock_has_source(s->refclk)) {  in stm32f100_soc_realize()
81         error_setg(errp, "refclk clock must not be wired up by the board code");  in stm32f100_soc_realize()
85     if (!clock_has_source(s->sysclk)) {  in stm32f100_soc_realize()
95     /* The refclk always runs at frequency HCLK / 8 */  in stm32f100_soc_realize()
96     clock_set_mul_div(s->refclk, 8, 1);  in stm32f100_soc_realize()
97     clock_set_source(s->refclk, s->sysclk);  in stm32f100_soc_realize()
103     memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F100.flash",  in stm32f100_soc_realize()
105     memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),  in stm32f100_soc_realize()
106                              "STM32F100.flash.alias", &s->flash, 0, FLASH_SIZE);  in stm32f100_soc_realize()
107     memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);  in stm32f100_soc_realize()
108     memory_region_add_subregion(system_memory, 0, &s->flash_alias);  in stm32f100_soc_realize()
111     memory_region_init_ram(&s->sram, NULL, "STM32F100.sram", SRAM_SIZE,  in stm32f100_soc_realize()
113     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);  in stm32f100_soc_realize()
116     armv7m = DEVICE(&s->armv7m);  in stm32f100_soc_realize()
117     qdev_prop_set_uint32(armv7m, "num-irq", 61);  in stm32f100_soc_realize()
118     qdev_prop_set_uint8(armv7m, "num-prio-bits", 4);  in stm32f100_soc_realize()
119     qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));  in stm32f100_soc_realize()
120     qdev_prop_set_bit(armv7m, "enable-bitband", true);  in stm32f100_soc_realize()
121     qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);  in stm32f100_soc_realize()
122     qdev_connect_clock_in(armv7m, "refclk", s->refclk);  in stm32f100_soc_realize()
123     object_property_set_link(OBJECT(&s->armv7m), "memory",  in stm32f100_soc_realize()
125     if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {  in stm32f100_soc_realize()
131         dev = DEVICE(&(s->usart[i]));  in stm32f100_soc_realize()
133         if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {  in stm32f100_soc_realize()
143         dev = DEVICE(&(s->spi[i]));  in stm32f100_soc_realize()
144         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {  in stm32f100_soc_realize()
188     dc->realize = stm32f100_soc_realize;  in stm32f100_soc_class_init()