Lines Matching +full:- +full:refclk
1 // SPDX-License-Identifier: GPL-2.0-only
41 int refclk, struct gma_clock_t *best_clock);
45 int refclk, struct gma_clock_t *best_clock);
84 int refclk) in mrst_limit() argument
87 struct drm_device *dev = crtc->dev; in mrst_limit()
92 switch (dev_priv->core_freq) { in mrst_limit()
107 dev_err(dev->dev, "mrst_limit Wrong display type.\n"); in mrst_limit()
113 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
114 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) in mrst_lvds_clock() argument
116 clock->dot = (refclk * clock->m) / (14 * clock->p1); in mrst_lvds_clock()
122 clock->dot, clock->m, clock->m1, clock->m2, clock->n, in mrst_print_pll()
123 clock->p1, clock->p2); in mrst_print_pll()
128 int refclk, struct gma_clock_t *best_clock) in mrst_sdvo_find_best_pll() argument
137 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { in mrst_sdvo_find_best_pll()
138 for (clock.n = limit->n.min; clock.n <= limit->n.max; in mrst_sdvo_find_best_pll()
140 for (clock.p1 = limit->p1.min; in mrst_sdvo_find_best_pll()
141 clock.p1 <= limit->p1.max; clock.p1++) { in mrst_sdvo_find_best_pll()
143 clock.p = clock.p1 * limit->p2.p2_slow; in mrst_sdvo_find_best_pll()
147 if (target_vco > limit->vco.max) in mrst_sdvo_find_best_pll()
150 if (target_vco < limit->vco.min) in mrst_sdvo_find_best_pll()
153 actual_freq = (refclk * clock.m) / in mrst_sdvo_find_best_pll()
155 freq_error = 10000 - in mrst_sdvo_find_best_pll()
158 if (freq_error < -min_error) { in mrst_sdvo_find_best_pll()
165 freq_error = -freq_error; in mrst_sdvo_find_best_pll()
181 * Returns a set of divisors for the desired target clock with the given refclk,
186 int refclk, struct gma_clock_t *best_clock) in mrst_lvds_find_best_pll() argument
194 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { in mrst_lvds_find_best_pll()
195 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max; in mrst_lvds_find_best_pll()
199 mrst_lvds_clock(refclk, &clock); in mrst_lvds_find_best_pll()
201 this_err = abs(clock.dot - target); in mrst_lvds_find_best_pll()
219 struct drm_device *dev = crtc->dev; in oaktrail_crtc_dpms()
222 int pipe = gma_crtc->pipe; in oaktrail_crtc_dpms()
223 const struct psb_offset *map = &dev_priv->regmap[pipe]; in oaktrail_crtc_dpms()
245 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
247 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
248 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
251 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
253 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
256 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
258 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
264 temp = REG_READ_WITH_AUX(map->conf, i); in oaktrail_crtc_dpms()
266 REG_WRITE_WITH_AUX(map->conf, in oaktrail_crtc_dpms()
271 temp = REG_READ_WITH_AUX(map->cntr, i); in oaktrail_crtc_dpms()
273 REG_WRITE_WITH_AUX(map->cntr, in oaktrail_crtc_dpms()
277 REG_WRITE_WITH_AUX(map->base, in oaktrail_crtc_dpms()
278 REG_READ_WITH_AUX(map->base, i), i); in oaktrail_crtc_dpms()
297 temp = REG_READ_WITH_AUX(map->cntr, i); in oaktrail_crtc_dpms()
299 REG_WRITE_WITH_AUX(map->cntr, in oaktrail_crtc_dpms()
302 REG_WRITE_WITH_AUX(map->base, in oaktrail_crtc_dpms()
303 REG_READ(map->base), i); in oaktrail_crtc_dpms()
304 REG_READ_WITH_AUX(map->base, i); in oaktrail_crtc_dpms()
308 temp = REG_READ_WITH_AUX(map->conf, i); in oaktrail_crtc_dpms()
310 REG_WRITE_WITH_AUX(map->conf, in oaktrail_crtc_dpms()
312 REG_READ_WITH_AUX(map->conf, i); in oaktrail_crtc_dpms()
317 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
319 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
321 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
345 * or -1 if the panel fitter is not present or not in use
355 return -1; in oaktrail_panel_fitter_pipe()
365 struct drm_device *dev = crtc->dev; in oaktrail_crtc_mode_set()
368 int pipe = gma_crtc->pipe; in oaktrail_crtc_mode_set()
369 const struct psb_offset *map = &dev_priv->regmap[pipe]; in oaktrail_crtc_mode_set()
370 int refclk = 0; in oaktrail_crtc_mode_set() local
390 drm_mode_copy(&gma_crtc->saved_mode, mode); in oaktrail_crtc_mode_set()
391 drm_mode_copy(&gma_crtc->saved_adjusted_mode, adjusted_mode); in oaktrail_crtc_mode_set()
395 if (!connector->encoder || connector->encoder->crtc != crtc) in oaktrail_crtc_mode_set()
400 switch (gma_encoder->type) { in oaktrail_crtc_mode_set()
416 drm_object_property_get_value(&connector->base, in oaktrail_crtc_mode_set()
417 dev->mode_config.scaling_mode_property, &scalingType); in oaktrail_crtc_mode_set()
430 REG_WRITE_WITH_AUX(map->src, ((mode->crtc_hdisplay - 1) << 16) | in oaktrail_crtc_mode_set()
431 (mode->crtc_vdisplay - 1), i); in oaktrail_crtc_mode_set()
440 offsetX = (adjusted_mode->crtc_hdisplay - in oaktrail_crtc_mode_set()
441 mode->crtc_hdisplay) / 2; in oaktrail_crtc_mode_set()
442 offsetY = (adjusted_mode->crtc_vdisplay - in oaktrail_crtc_mode_set()
443 mode->crtc_vdisplay) / 2; in oaktrail_crtc_mode_set()
446 REG_WRITE_WITH_AUX(map->htotal, (mode->crtc_hdisplay - 1) | in oaktrail_crtc_mode_set()
447 ((adjusted_mode->crtc_htotal - 1) << 16), i); in oaktrail_crtc_mode_set()
448 REG_WRITE_WITH_AUX(map->vtotal, (mode->crtc_vdisplay - 1) | in oaktrail_crtc_mode_set()
449 ((adjusted_mode->crtc_vtotal - 1) << 16), i); in oaktrail_crtc_mode_set()
450 REG_WRITE_WITH_AUX(map->hblank, in oaktrail_crtc_mode_set()
451 (adjusted_mode->crtc_hblank_start - offsetX - 1) | in oaktrail_crtc_mode_set()
452 ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16), i); in oaktrail_crtc_mode_set()
453 REG_WRITE_WITH_AUX(map->hsync, in oaktrail_crtc_mode_set()
454 (adjusted_mode->crtc_hsync_start - offsetX - 1) | in oaktrail_crtc_mode_set()
455 ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16), i); in oaktrail_crtc_mode_set()
456 REG_WRITE_WITH_AUX(map->vblank, in oaktrail_crtc_mode_set()
457 (adjusted_mode->crtc_vblank_start - offsetY - 1) | in oaktrail_crtc_mode_set()
458 ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16), i); in oaktrail_crtc_mode_set()
459 REG_WRITE_WITH_AUX(map->vsync, in oaktrail_crtc_mode_set()
460 (adjusted_mode->crtc_vsync_start - offsetY - 1) | in oaktrail_crtc_mode_set()
461 ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16), i); in oaktrail_crtc_mode_set()
465 REG_WRITE_WITH_AUX(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in oaktrail_crtc_mode_set()
466 ((adjusted_mode->crtc_htotal - 1) << 16), i); in oaktrail_crtc_mode_set()
467 REG_WRITE_WITH_AUX(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in oaktrail_crtc_mode_set()
468 ((adjusted_mode->crtc_vtotal - 1) << 16), i); in oaktrail_crtc_mode_set()
469 REG_WRITE_WITH_AUX(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in oaktrail_crtc_mode_set()
470 ((adjusted_mode->crtc_hblank_end - 1) << 16), i); in oaktrail_crtc_mode_set()
471 REG_WRITE_WITH_AUX(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in oaktrail_crtc_mode_set()
472 ((adjusted_mode->crtc_hsync_end - 1) << 16), i); in oaktrail_crtc_mode_set()
473 REG_WRITE_WITH_AUX(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in oaktrail_crtc_mode_set()
474 ((adjusted_mode->crtc_vblank_end - 1) << 16), i); in oaktrail_crtc_mode_set()
475 REG_WRITE_WITH_AUX(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in oaktrail_crtc_mode_set()
476 ((adjusted_mode->crtc_vsync_end - 1) << 16), i); in oaktrail_crtc_mode_set()
483 crtc->helper_private; in oaktrail_crtc_mode_set()
484 crtc_funcs->mode_set_base(crtc, x, y, old_fb); in oaktrail_crtc_mode_set()
488 pipeconf = REG_READ(map->conf); in oaktrail_crtc_mode_set()
491 dspcntr = REG_READ(map->cntr); in oaktrail_crtc_mode_set()
505 refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000; in oaktrail_crtc_mode_set()
506 limit = mrst_limit(crtc, refclk); in oaktrail_crtc_mode_set()
507 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, in oaktrail_crtc_mode_set()
508 refclk, &clock); in oaktrail_crtc_mode_set()
512 clock.p1 = (1L << (clock.p1 - 1)); in oaktrail_crtc_mode_set()
513 clock.m -= 2; in oaktrail_crtc_mode_set()
514 clock.n = (1L << (clock.n - 1)); in oaktrail_crtc_mode_set()
525 fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8; in oaktrail_crtc_mode_set()
539 adjusted_mode->clock / mode->clock; in oaktrail_crtc_mode_set()
543 (sdvo_pixel_multiply - in oaktrail_crtc_mode_set()
550 dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16; in oaktrail_crtc_mode_set()
552 dpll |= (1 << (clock.p1 - 2)) << 17; in oaktrail_crtc_mode_set()
558 REG_WRITE_WITH_AUX(map->fp0, fp, i); in oaktrail_crtc_mode_set()
559 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set()
560 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_mode_set()
567 REG_WRITE_WITH_AUX(map->fp0, fp, i); in oaktrail_crtc_mode_set()
568 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set()
569 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_mode_set()
573 /* write it again -- the BIOS does, after all */ in oaktrail_crtc_mode_set()
574 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set()
575 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_mode_set()
579 REG_WRITE_WITH_AUX(map->conf, pipeconf, i); in oaktrail_crtc_mode_set()
580 REG_READ_WITH_AUX(map->conf, i); in oaktrail_crtc_mode_set()
583 REG_WRITE_WITH_AUX(map->cntr, dspcntr, i); in oaktrail_crtc_mode_set()
595 struct drm_device *dev = crtc->dev; in oaktrail_pipe_set_base()
598 struct drm_framebuffer *fb = crtc->primary->fb; in oaktrail_pipe_set_base()
599 int pipe = gma_crtc->pipe; in oaktrail_pipe_set_base()
600 const struct psb_offset *map = &dev_priv->regmap[pipe]; in oaktrail_pipe_set_base()
608 dev_dbg(dev->dev, "No FB bound\n"); in oaktrail_pipe_set_base()
615 start = to_psb_gem_object(fb->obj[0])->offset; in oaktrail_pipe_set_base()
616 offset = y * fb->pitches[0] + x * fb->format->cpp[0]; in oaktrail_pipe_set_base()
618 REG_WRITE(map->stride, fb->pitches[0]); in oaktrail_pipe_set_base()
620 dspcntr = REG_READ(map->cntr); in oaktrail_pipe_set_base()
623 switch (fb->format->cpp[0] * 8) { in oaktrail_pipe_set_base()
628 if (fb->format->depth == 15) in oaktrail_pipe_set_base()
638 dev_err(dev->dev, "Unknown color depth\n"); in oaktrail_pipe_set_base()
639 ret = -EINVAL; in oaktrail_pipe_set_base()
642 REG_WRITE(map->cntr, dspcntr); in oaktrail_pipe_set_base()
644 REG_WRITE(map->base, offset); in oaktrail_pipe_set_base()
645 REG_READ(map->base); in oaktrail_pipe_set_base()
646 REG_WRITE(map->surf, start); in oaktrail_pipe_set_base()
647 REG_READ(map->surf); in oaktrail_pipe_set_base()