1 // SPDX-License-Identifier: GPL-2.0+
4  * Author: Eric Gao <eric.gao@rock-chips.com>
19 #include <dm/uclass-internal.h>
33 	ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),  in rk_mipi_read_timing()
38 		return -EINVAL;  in rk_mipi_read_timing()
61 	mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits)));  in rk_mipi_dsi_write()
84 	uintptr_t regs = priv->regs;  in rk_mipi_dsi_enable()
85 	u32 txbyte_clk = priv->txbyte_clk;  in rk_mipi_dsi_enable()
86 	u32 txesc_clk = priv->txesc_clk;  in rk_mipi_dsi_enable()
91 	rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);  in rk_mipi_dsi_enable()
92 	rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);  in rk_mipi_dsi_enable()
93 	rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ  in rk_mipi_dsi_enable()
94 			  + timing->hback_porch.typ + timing->hactive.typ  in rk_mipi_dsi_enable()
95 			  + timing->hfront_porch.typ));  in rk_mipi_dsi_enable()
96 	rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ);  in rk_mipi_dsi_enable()
97 	rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ);  in rk_mipi_dsi_enable()
98 	rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ);  in rk_mipi_dsi_enable()
99 	rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ);  in rk_mipi_dsi_enable()
102 	val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;  in rk_mipi_dsi_enable()
105 	val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;  in rk_mipi_dsi_enable()
108 	val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;  in rk_mipi_dsi_enable()
111 	val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;  in rk_mipi_dsi_enable()
124 	timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),  in rk_mipi_dsi_enable()
125 									 "display-timings");  in rk_mipi_dsi_enable()
126 	node = fdt_first_subnode(gd->fdt_blob, timing_node);  in rk_mipi_dsi_enable()
127 	val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);  in rk_mipi_dsi_enable()
155 	/* Timeout count for hs<->lp transation between Line period */  in rk_mipi_dsi_enable()
201 	uintptr_t regs = priv->regs;  in rk_mipi_phy_enable()
206 	u64 ddr_clk = priv->phy_clk;  in rk_mipi_phy_enable()
207 	u32 refclk = priv->ref_clk;  in rk_mipi_phy_enable()  local
208 	u32 remain = refclk;  in rk_mipi_phy_enable()
249 		return -EINVAL;  in rk_mipi_phy_enable()
258 	 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz  in rk_mipi_phy_enable()
261 	max_prediv = (refclk / (5 * MHz));  in rk_mipi_phy_enable()
262 	min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1);  in rk_mipi_phy_enable()
268 		debug("%s: Invalid refclk value\n", __func__);  in rk_mipi_phy_enable()
269 		return -EINVAL;  in rk_mipi_phy_enable()
272 	/* Calculate the best refclk and feedback division value for dphy pll */  in rk_mipi_phy_enable()
274 		if ((ddr_clk * i % refclk < remain) &&  in rk_mipi_phy_enable()
275 		    (ddr_clk * i / refclk) < max_fbdiv) {  in rk_mipi_phy_enable()
277 			remain = ddr_clk * i % refclk;  in rk_mipi_phy_enable()
280 	fbdiv = ddr_clk * prediv / refclk;  in rk_mipi_phy_enable()
281 	ddr_clk = refclk * fbdiv / prediv;  in rk_mipi_phy_enable()
282 	priv->phy_clk = ddr_clk;  in rk_mipi_phy_enable()
284 	debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n",  in rk_mipi_phy_enable()
285 	      __func__, refclk, prediv, fbdiv, ddr_clk);  in rk_mipi_phy_enable()
288 	test_data[0] = prediv - 1;  in rk_mipi_phy_enable()
290 	test_data[0] = (fbdiv - 1) & 0x1f;  in rk_mipi_phy_enable()
292 	test_data[0] = (fbdiv - 1) >> 5 | 0x80;  in rk_mipi_phy_enable()