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Searched defs:CPUArchState (Results 1 – 21 of 21) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu.h200 target_ulong vl;
203 bool vill;
251 uint64_t mip;
263 uint64_t mie;
270 uint64_t sie;
276 uint64_t vsie;
298 uint64_t mvien;
299 uint64_t mvip;
312 uint64_t hvien;
319 uint64_t hvip;
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/openbmc/qemu/target/loongarch/
H A Dcpu.h285 uint64_t gpr[32];
286 uint64_t pc;
288 fpr_t fpr[32];
289 bool cf[8];
290 uint32_t fcsr0;
301 uint64_t CSR_ERA;
312 uint64_t CSR_PGD;
322 uint64_t CSR_TID;
346 uint64_t CSR_DBG;
354 uint64_t llval;
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/openbmc/qemu/target/rx/
H A Dcpu.h69 typedef struct CPUArchState { struct
76 uint32_t psw_u;
77 uint32_t psw_i;
78 uint32_t psw_pm;
79 uint32_t psw_ipl;
86 uint32_t fintv;
87 uint32_t fpsw;
88 uint64_t acc;
91 struct {} end_reset_fields;
94 uint32_t in_sleep;
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/openbmc/qemu/target/hexagon/
H A Dcpu.h71 typedef struct CPUArchState { struct
76 target_ulong last_pc_dumped;
77 target_ulong stack_start;
79 uint8_t slot_cancelled;
80 target_ulong new_value_usr;
90 float_status fp_status;
92 target_ulong llsc_addr;
93 target_ulong llsc_val;
94 uint64_t llsc_val_i64;
112 bool vtcm_pending;
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/openbmc/qemu/target/avr/
H A Dcpu.h107 typedef struct CPUArchState { struct
110 uint32_t sregC; /* 0x00000001 1 bit */
111 uint32_t sregZ; /* 0x00000001 1 bit */
112 uint32_t sregN; /* 0x00000001 1 bit */
113 uint32_t sregV; /* 0x00000001 1 bit */
114 uint32_t sregS; /* 0x00000001 1 bit */
115 uint32_t sregH; /* 0x00000001 1 bit */
116 uint32_t sregT; /* 0x00000001 1 bit */
117 uint32_t sregI; /* 0x00000001 1 bit */
126 uint32_t sp; /* 16 bits */
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/openbmc/qemu/target/sparc/
H A Dcpu.h463 struct {} end_reset_fields;
471 uint64_t lsu;
483 uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
493 uint32_t asi;
495 uint32_t tl;
497 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
503 uint32_t fprs;
504 uint64_t tick_cmpr, stick_cmpr;
505 CPUTimer *tick, *stick;
508 uint64_t gsr;
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/openbmc/qemu/target/sh4/
H A Dcpu.h141 typedef struct CPUArchState { struct
163 union {
175 float_status fp_status;
192 uint32_t lock_addr;
193 uint32_t lock_value;
196 struct {} end_reset_fields;
199 int id; /* CPU model */
202 uint32_t features;
204 void *intc_handle;
206 memory_content *movcal_backup;
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/openbmc/qemu/target/openrisc/
H A Dcpu.h235 typedef struct CPUArchState { struct
239 target_ulong ppc; /* Prev PC */
240 target_ulong jmp_pc; /* Jump PC */
254 uint32_t fpcsr; /* Float register */
255 float_status fp_status;
257 target_ulong lock_addr;
258 target_ulong lock_value;
263 CPUOpenRISCTLBContext tlb;
267 struct {} end_reset_fields;
279 QEMUTimer *timer;
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/openbmc/qemu/target/cris/
H A Dcpu.h114 uint32_t pc;
117 uint32_t ksp;
120 int dslot;
121 int btaken;
125 uint32_t cc_op;
128 uint32_t cc_src;
131 int cc_size;
133 int cc_x;
136 int locked_irq;
139 int trap_vector;
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/openbmc/qemu/target/mips/
H A Dcpu.h529 TCState active_tc;
535 uint32_t SEGBITS;
536 uint32_t PABITS;
543 uint64_t PAMask;
546 int32_t msair;
827 int32_t CP0_PRid;
1102 int error_code;
1175 struct {} end_reset_fields;
1181 qemu_irq irq[8];
1185 struct {
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/openbmc/qemu/target/i386/
H A Dcpu.h1721 struct {} start_init_save;
1738 floatx80 ft0;
1798 uint64_t pat;
1811 struct {} end_init_save;
1867 union {
1897 struct {} end_reset_fields;
1907 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1909 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1911 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1924 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
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/openbmc/qemu/target/hppa/
H A Dcpu.h203 typedef struct CPUArchState { struct
207 target_ulong gr[32];
208 uint64_t fr[32];
226 uint64_t iasq_f;
227 uint64_t iasq_b;
230 float_status fp_status;
240 uint32_t unwind_breg;
251 uint32_t tlb_last;
257 HPPATLBEntry *tlb_partial;
260 HPPATLBEntry *tlb_unused;
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/openbmc/qemu/target/alpha/
H A Dcpu.h199 uint64_t ir[31];
201 uint64_t pc;
207 uint32_t fpcr;
209 uint32_t swcr;
218 uint32_t flags;
233 uint64_t palbr;
234 uint64_t ptbr;
237 uint64_t usp;
245 int error_code;
248 uint32_t amask;
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/openbmc/qemu/target/m68k/
H A Dcpu.h86 uint32_t pc;
87 uint32_t sr;
109 uint32_t fpcr;
110 uint32_t fpsr;
124 struct {
140 } mmu;
143 uint32_t vbr;
144 uint32_t mbar;
147 uint32_t sfc;
148 uint32_t dfc;
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/openbmc/qemu/target/s390x/
H A Dcpu.h70 struct {} start_initial_reset_fields;
73 uint32_t cc_op;
78 PSW psw;
84 uint64_t cc_vr;
90 uint64_t psa;
103 uint64_t ckc;
104 uint64_t cputm;
111 uint64_t gbea;
112 uint64_t pp;
115 struct {} start_normal_reset_fields;
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/openbmc/qemu/target/microblaze/
H A Dcpu.h242 struct CPUArchState { struct
246 uint32_t imm;
248 uint32_t pc;
251 target_ulong ear;
252 uint32_t esr;
253 uint32_t fsr;
254 uint32_t btr;
255 uint32_t edr;
258 uint32_t slr, shr;
283 uint32_t iflags;
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/openbmc/qemu/target/tricore/
H A Dcpu.h29 typedef struct CPUArchState { struct
31 uint32_t gpr_a[16];
32 uint32_t gpr_d[16];
36 uint32_t PSW;
38 uint32_t PSW_USB_C;
39 uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */
40 uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */
41 uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
42 uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
53 float_status fp_status;
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/openbmc/qemu/target/xtensa/
H A Dcpu.h509 struct CPUArchState { struct
511 uint32_t regs[16];
512 uint32_t pc;
513 uint32_t sregs[256];
514 uint32_t uregs[256];
516 union {
519 } fregs[16];
530 bool runstall;
534 qemu_irq *irq_inputs;
538 uint64_t time_base;
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/openbmc/qemu/target/ppc/
H A Dcpu.h1220 target_ulong lr;
1227 target_ulong so;
1228 target_ulong ov;
1229 target_ulong ca;
1252 int core_index;
1289 uint32_t vscr;
1325 int bfd_mach;
1326 uint32_t flags;
1330 int error_code;
1385 uint64_t tm_cr;
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/openbmc/qemu/target/arm/
H A Dcpu.h267 struct {
526 } cp15;
528 struct {
571 } v7m;
579 struct {
590 struct {
606 struct {
668 } vfp;
696 } keys;
730 struct {} end_reset_fields;
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/openbmc/qemu/include/qemu/
H A Dtypedefs.h40 typedef struct CPUArchState CPUArchState; typedef