Searched defs:CPUArchState (Results 1 – 11 of 11) sorted by relevance
75 typedef struct CPUArchState { struct77 uint32_t regs[NUM_REGS]; /* general registers */78 uint32_t psw_o; /* O bit of status register */79 uint32_t psw_s; /* S bit of status register */80 uint32_t psw_z; /* Z bit of status register */81 uint32_t psw_c; /* C bit of status register */82 uint32_t psw_u;83 uint32_t psw_i;84 uint32_t psw_pm;85 uint32_t psw_ipl;[all …]
76 typedef struct CPUArchState { struct77 target_ulong gpr[TOTAL_PER_THREAD_REGS];78 target_ulong pred[NUM_PREGS];81 target_ulong last_pc_dumped;82 target_ulong stack_start;84 uint8_t slot_cancelled;85 target_ulong new_value_usr;87 MemLog mem_log_stores[STORES_MAX];89 float_status fp_status;91 target_ulong llsc_addr;[all …]
116 typedef struct CPUArchState { struct117 uint32_t pc_w; /* 0x003fffff up to 22 bits */119 uint32_t sregC; /* 0x00000001 1 bit */120 uint32_t sregZ; /* 0x00000001 1 bit */121 uint32_t sregN; /* 0x00000001 1 bit */122 uint32_t sregV; /* 0x00000001 1 bit */123 uint32_t sregS; /* 0x00000001 1 bit */124 uint32_t sregH; /* 0x00000001 1 bit */125 uint32_t sregT; /* 0x00000001 1 bit */126 uint32_t sregI; /* 0x00000001 1 bit */[all …]
528 typedef struct CPUArchState { struct529 TCState active_tc;530 CPUMIPSFPUContext active_fpu;532 uint32_t current_tc;534 uint32_t SEGBITS;535 uint32_t PABITS;541 target_ulong SEGMask;542 uint64_t PAMask;545 int32_t msair;552 int32_t CP0_Index;[all …]
200 typedef struct CPUArchState { struct201 uint64_t ir[31];202 float64 fir[31];203 uint64_t pc;204 uint64_t unique;205 uint64_t lock_addr;206 uint64_t lock_value;209 uint32_t fpcr;211 uint32_t swcr;213 uint32_t fpcr_exc_enable;[all …]
83 typedef struct CPUArchState { struct84 uint32_t dregs[8];85 uint32_t aregs[8];86 uint32_t pc;87 uint32_t sr;96 int current_sp;97 uint32_t sp[3];100 uint32_t cc_op;101 uint32_t cc_x; /* always 0/1 */102 uint32_t cc_n; /* in bit 31 (i.e. negative) */[all …]
53 typedef struct CPUArchState { struct54 uint64_t regs[16]; /* GP registers */59 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */60 uint32_t aregs[16]; /* access registers */61 uint64_t gscb[4]; /* guarded storage control */62 uint64_t etoken; /* etoken */63 uint64_t etoken_extension; /* etoken extension */65 uint64_t diag318_info;68 struct {} start_initial_reset_fields;70 uint32_t fpc; /* floating-point control register */[all …]
34 typedef struct CPUArchState { struct36 uint32_t gpr_a[16];37 uint32_t gpr_d[16];41 uint32_t PSW;43 uint32_t PSW_USB_C;44 uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */45 uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */46 uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */47 uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */58 float_status fp_status;[all …]
511 struct CPUArchState { struct512 const XtensaConfig *config;513 uint32_t regs[16];514 uint32_t pc;515 uint32_t sregs[256];516 uint32_t uregs[256];517 uint32_t phys_regs[MAX_NAREG];518 union {521 } fregs[16];522 float_status fp_status;[all …]
1280 struct CPUArchState { struct1282 target_ulong gpr[32]; /* general purpose registers */1283 target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */1284 target_ulong lr;1285 target_ulong ctr;1286 uint32_t crf[8]; /* condition register */1288 target_ulong cfar;1290 target_ulong xer; /* XER (with SO, OV, CA split out) */1291 target_ulong so;1292 target_ulong ov;[all …]
41 typedef struct CPUArchState CPUArchState; typedef