target/riscv/cpu.h

192 struct CPUArchState {  struct
193     target_ulong gpr[32];
194     target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
197     uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
198     target_ulong vxrm;
199     target_ulong vxsat;
200     target_ulong vl;
201     target_ulong vstart;
202     target_ulong vtype;
203     bool vill;
205     target_ulong pc;
206     target_ulong load_res;
207     target_ulong load_val;
210     uint64_t fpr[32]; /* assume both F and D extensions */
211     target_ulong frm;
212     float_status fp_status;
214     target_ulong badaddr;
215     target_ulong bins;
217     target_ulong guest_phys_fault_addr;
219     target_ulong priv_ver;
220     target_ulong vext_ver;
223     uint32_t misa_mxl;      /* current mxl */
224     uint32_t misa_ext;      /* current extensions */
225     uint32_t misa_ext_mask; /* max ext for this cpu */
226     uint32_t xl;            /* current xlen */
229     target_ulong retxh;
231     target_ulong jvt;
234     uint32_t elf_flags;
238     target_ulong priv;
240     bool virt_enabled;
241     target_ulong geilen;
242     uint64_t resetvec;
244     target_ulong mhartid;
249     uint64_t mstatus;
251     uint64_t mip;
258     bool external_seip;
259     bool software_seip;
261     uint64_t miclaim;
263     uint64_t mie;
264     uint64_t mideleg;
270     uint64_t sie;
276     uint64_t vsie;
278     target_ulong satp;   /* since: priv-1.10.0 */
279     target_ulong stval;
280     target_ulong medeleg;
282     target_ulong stvec;
283     target_ulong sepc;
284     target_ulong scause;
286     target_ulong mtvec;
287     target_ulong mepc;
288     target_ulong mcause;
289     target_ulong mtval;  /* since: priv-1.10.0 */
292     uint8_t miprio[64];
293     uint8_t siprio[64];
296     target_ulong miselect;
297     target_ulong siselect;
298     uint64_t mvien;
299     uint64_t mvip;
302     target_ulong hstatus;
303     target_ulong hedeleg;
304     uint64_t hideleg;
305     uint32_t hcounteren;
306     target_ulong htval;
307     target_ulong htinst;
308     target_ulong hgatp;
309     target_ulong hgeie;
310     target_ulong hgeip;
311     uint64_t htimedelta;
312     uint64_t hvien;
319     uint64_t hvip;
322     target_ulong hvictl;
323     uint8_t hviprio[64];
326     uint64_t mscratchh;
327     uint64_t sscratchh;
334     uint64_t vsstatus;
335     target_ulong vstvec;
336     target_ulong vsscratch;
337     target_ulong vsepc;
338     target_ulong vscause;
339     target_ulong vstval;
340     target_ulong vsatp;
343     target_ulong vsiselect;
345     target_ulong mtval2;
346     target_ulong mtinst;
349     target_ulong stvec_hs;
350     target_ulong sscratch_hs;
351     target_ulong sepc_hs;
352     target_ulong scause_hs;
353     target_ulong stval_hs;
354     target_ulong satp_hs;
355     uint64_t mstatus_hs;
361     bool two_stage_lookup;
366     bool two_stage_indirect_lookup;
368     uint32_t scounteren;
369     uint32_t mcounteren;
371     uint32_t mcountinhibit;
374     target_ulong mcyclecfg;
375     target_ulong mcyclecfgh;
376     target_ulong minstretcfg;
377     target_ulong minstretcfgh;
380     PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
383     target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
386     target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
388     PMUFixedCtrState pmu_fixed_ctrs[2];
390     target_ulong sscratch;
391     target_ulong mscratch;
394     uint64_t stimecmp;
396     uint64_t vstimecmp;
399     pmp_table_t pmp_state;
400     target_ulong mseccfg;
403     target_ulong trigger_cur;
404     target_ulong tdata1[RV_MAX_TRIGGERS];
405     target_ulong tdata2[RV_MAX_TRIGGERS];
406     target_ulong tdata3[RV_MAX_TRIGGERS];
407     target_ulong mcontext;
408     struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
409     struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
410     QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
411     int64_t last_icount;
412     bool itrigger_enabled;
415     uint64_t (*rdtime_fn)(void *);
416     void *rdtime_fn_arg;
430     int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
432     void *aia_ireg_rmw_fn_arg[4];
435     bool debugger;
440     target_ulong mmte;
441     target_ulong mpmmask;
442     target_ulong mpmbase;
443     target_ulong spmmask;
444     target_ulong spmbase;
445     target_ulong upmmask;
446     target_ulong upmbase;
449     uint64_t menvcfg;
450     uint64_t mstateen[SMSTATEEN_MAX_COUNT];
451     uint64_t hstateen[SMSTATEEN_MAX_COUNT];
452     uint64_t sstateen[SMSTATEEN_MAX_COUNT];
453     target_ulong senvcfg;
454     uint64_t henvcfg;
456     target_ulong cur_pmmask;
457     target_ulong cur_pmbase;
460     QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
461     QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
462     bool vstime_irq;
464     hwaddr kernel_addr;
465     hwaddr fdt_addr;
469     bool kvm_timer_dirty;
470     uint64_t kvm_timer_time;
471     uint64_t kvm_timer_compare;
472     uint64_t kvm_timer_state;
473     uint64_t kvm_timer_frequency;