target/sh4/cpu.h

141 typedef struct CPUArchState {  struct
142     uint32_t flags;             /* general execution flags */
143     uint32_t gregs[24];         /* general registers */
144     float32 fregs[32];          /* floating point registers */
145     uint32_t sr;                /* status register (with T split out) */
146     uint32_t sr_m;              /* M bit of status register */
147     uint32_t sr_q;              /* Q bit of status register */
148     uint32_t sr_t;              /* T bit of status register */
149     uint32_t ssr;               /* saved status register */
150     uint32_t spc;               /* saved program counter */
151     uint32_t gbr;               /* global base register */
152     uint32_t vbr;               /* vector base register */
153     uint32_t sgr;               /* saved global register 15 */
154     uint32_t dbr;               /* debug base register */
155     uint32_t pc;                /* program counter */
156     uint32_t delayed_pc;        /* target of delayed branch */
157     uint32_t delayed_cond;      /* condition of delayed branch */
158     uint32_t pr;                /* procedure register */
159     uint32_t fpscr;             /* floating point status/control register */
160     uint32_t fpul;              /* floating point communication register */
163     union {
175     float_status fp_status;
178     uint32_t mmucr;             /* MMU control register */
179     uint32_t pteh;              /* page table entry high register */
180     uint32_t ptel;              /* page table entry low register */
181     uint32_t ptea;              /* page table entry assistance register */
182     uint32_t ttb;               /* translation table base register */
183     uint32_t tea;               /* TLB exception address register */
184     uint32_t tra;               /* TRAPA exception register */
185     uint32_t expevt;            /* exception event register */
186     uint32_t intevt;            /* interrupt event register */
188     tlb_t itlb[ITLB_SIZE];      /* instruction translation table */
189     tlb_t utlb[UTLB_SIZE];      /* unified translation table */
192     uint32_t lock_addr;
193     uint32_t lock_value;
196     struct {} end_reset_fields;
199     int id;                     /* CPU model */
202     uint32_t features;
204     void *intc_handle;
205     int in_sleep;               /* SR_BL ignored during sleep */
206     memory_content *movcal_backup;
207     memory_content **movcal_backup_tail;