target/hppa/cpu.h

203 typedef struct CPUArchState {  struct
204     target_ulong iaoq_f;     /* front */
205     target_ulong iaoq_b;     /* back, aka next instruction */
207     target_ulong gr[32];
208     uint64_t fr[32];
209     uint64_t sr[8];          /* stored shifted into place for gva */
211     uint32_t psw;            /* All psw bits except the following:  */
212     uint32_t psw_xb;         /* X and B, in their normal positions */
213     target_ulong psw_n;      /* boolean */
214     target_long psw_v;       /* in most significant bit */
223     target_ulong psw_cb;     /* in least significant bit of next nibble */
224     target_ulong psw_cb_msb; /* boolean */
226     uint64_t iasq_f;
227     uint64_t iasq_b;
229     uint32_t fr0_shadow;     /* flags, c, ca/cq, rm, d, enables */
230     float_status fp_status;
232     target_ulong cr[32];     /* control registers */
233     target_ulong cr_back[2]; /* back of cr17/cr18 */
234     target_ulong shadow[7];  /* shadow registers */
240     uint32_t unwind_breg;
251     uint32_t tlb_last;
257     HPPATLBEntry *tlb_partial;
260     HPPATLBEntry *tlb_unused;
263     IntervalTreeRoot tlb_root;
265     HPPATLBEntry tlb[HPPA_TLB_ENTRIES];