Lines Matching defs:CPUArchState

284 typedef struct CPUArchState {  struct
285 uint64_t gpr[32];
286 uint64_t pc;
288 fpr_t fpr[32];
289 bool cf[8];
290 uint32_t fcsr0;
292 uint32_t cpucfg[21];
295 uint64_t CSR_CRMD;
296 uint64_t CSR_PRMD;
297 uint64_t CSR_EUEN;
298 uint64_t CSR_MISC;
299 uint64_t CSR_ECFG;
300 uint64_t CSR_ESTAT;
301 uint64_t CSR_ERA;
302 uint64_t CSR_BADV;
303 uint64_t CSR_BADI;
304 uint64_t CSR_EENTRY;
305 uint64_t CSR_TLBIDX;
306 uint64_t CSR_TLBEHI;
307 uint64_t CSR_TLBELO0;
308 uint64_t CSR_TLBELO1;
309 uint64_t CSR_ASID;
310 uint64_t CSR_PGDL;
311 uint64_t CSR_PGDH;
312 uint64_t CSR_PGD;
313 uint64_t CSR_PWCL;
314 uint64_t CSR_PWCH;
315 uint64_t CSR_STLBPS;
316 uint64_t CSR_RVACFG;
317 uint64_t CSR_CPUID;
318 uint64_t CSR_PRCFG1;
319 uint64_t CSR_PRCFG2;
320 uint64_t CSR_PRCFG3;
321 uint64_t CSR_SAVE[16];
322 uint64_t CSR_TID;
323 uint64_t CSR_TCFG;
324 uint64_t CSR_TVAL;
325 uint64_t CSR_CNTC;
326 uint64_t CSR_TICLR;
327 uint64_t CSR_LLBCTL;
328 uint64_t CSR_IMPCTL1;
329 uint64_t CSR_IMPCTL2;
330 uint64_t CSR_TLBRENTRY;
331 uint64_t CSR_TLBRBADV;
332 uint64_t CSR_TLBRERA;
333 uint64_t CSR_TLBRSAVE;
334 uint64_t CSR_TLBRELO0;
335 uint64_t CSR_TLBRELO1;
336 uint64_t CSR_TLBREHI;
337 uint64_t CSR_TLBRPRMD;
338 uint64_t CSR_MERRCTL;
339 uint64_t CSR_MERRINFO1;
340 uint64_t CSR_MERRINFO2;
341 uint64_t CSR_MERRENTRY;
342 uint64_t CSR_MERRERA;
343 uint64_t CSR_MERRSAVE;
344 uint64_t CSR_CTAG;
345 uint64_t CSR_DMW[4];
346 uint64_t CSR_DBG;
347 uint64_t CSR_DERA;
348 uint64_t CSR_DSAVE;
351 float_status fp_status;
352 uint32_t fcsr0_mask;
353 uint64_t lladdr; /* LL virtual address compared against SC */
354 uint64_t llval;
358 LoongArchTLB tlb[LOONGARCH_TLB_MAX];
361 AddressSpace *address_space_iocsr;
362 bool load_elf;
363 uint64_t elf_address;
364 uint32_t mp_state;
366 DeviceState *ipistate;
368 struct loongarch_boot_info *boot_info;