target/ppc/cpu.h

1216 struct CPUArchState {  struct
1218     target_ulong gpr[32];  /* general purpose registers */
1219     target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
1220     target_ulong lr;
1221     target_ulong ctr;
1222     uint32_t crf[8];       /* condition register */
1224     target_ulong cfar;
1226     target_ulong xer;      /* XER (with SO, OV, CA split out) */
1227     target_ulong so;
1228     target_ulong ov;
1229     target_ulong ca;
1230     target_ulong ov32;
1231     target_ulong ca32;
1233     target_ulong reserve_addr;   /* Reservation address */
1234     target_ulong reserve_length; /* Reservation larx op size (bytes) */
1235     target_ulong reserve_val;    /* Reservation value */
1237     target_ulong reserve_val2;
1241     target_ulong msr;      /* machine state register */
1242     target_ulong tgpr[4];  /* temporary general purpose registers, */
1245     target_ulong nip;      /* next instruction pointer */
1248     int access_type;
1251     bool has_smt_siblings;
1252     int core_index;
1257     ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1258     struct CPUBreakpoint *ciabr_breakpoint;
1259     struct CPUWatchpoint *dawr0_watchpoint;
1261     target_ulong sr[32];   /* segment registers */
1262     uint32_t nb_BATs;      /* number of BATs */
1263     target_ulong DBAT[2][8];
1264     target_ulong IBAT[2][8];
1266     int32_t nb_tlb;  /* Total number of TLB */
1267     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1268     int nb_ways;     /* Number of ways in the TLB set */
1269     int last_way;    /* Last used way used to allocate TLB in a LRU way */
1270     int nb_pids;     /* Number of available PID registers */
1271     int tlb_type;    /* Type of TLB we're dealing with */
1272     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed */
1274     bool tlb_dirty;  /* Set to non-zero when modifying TLB */
1275     bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1277     uint32_t tlb_need_flush; /* Delayed flush needed */
1283     target_ulong spr[1024]; /* special purpose registers */
1284     ppc_spr_t spr_cb[1024];
1286     uint8_t pmc_ins_cnt;
1287     uint8_t pmc_cyc_cnt;
1289     uint32_t vscr;
1291     ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1295     uint64_t spe_acc;
1296     uint32_t spe_fscr;
1298     float_status vec_status;
1299     float_status fp_status; /* Floating point execution context */
1300     target_ulong fpscr;     /* Floating point status and control register */
1303     ppc_tb_t *tb_env;      /* Time base and decrementer */
1304     ppc_dcr_t *dcr_env;    /* Device control registers */
1306     int dcache_line_size;
1307     int icache_line_size;
1311     target_ulong bhrb_num_entries;
1312     intptr_t     bhrb_base;
1313     target_ulong bhrb_filter;
1314     target_ulong bhrb_offset;
1315     target_ulong bhrb_offset_mask;
1316     uint64_t bhrb[BHRB_MAX_NUM_ENTRIES];
1321     target_ulong msr_mask;
1322     powerpc_mmu_t mmu_model;
1323     powerpc_excp_t excp_model;
1324     powerpc_input_t bus_model;
1325     int bfd_mach;
1326     uint32_t flags;
1327     uint64_t insns_flags;
1328     uint64_t insns_flags2;
1330     int error_code;
1331     uint32_t pending_interrupts;
1333     uint64_t excp_stats[POWERPC_EXCP_NB];
1339     uint32_t irq_input_state;
1341     target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
1342     target_ulong excp_prefix;
1343     target_ulong ivor_mask;
1344     target_ulong ivpr_mask;
1345     target_ulong hreset_vector;
1346     hwaddr mpic_iack;
1347     bool mpic_proxy;  /* true if the external proxy facility mode is enabled */
1348     bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1354     bool resume_as_sreset;
1358     uint32_t hflags;
1359     target_ulong hflags_compat_nmsr; /* for migration compatibility */
1362     int (*check_pow)(CPUPPCState *env);
1365     int (*check_attn)(CPUPPCState *env);
1368     void *load_info;  /* holds boot loading state */
1379     uint8_t fit_period[4];
1380     uint8_t wdt_period[4];
1383     target_ulong tm_gpr[32];
1384     ppc_avr_t tm_vsr[64];
1385     uint64_t tm_cr;
1386     uint64_t tm_lr;
1387     uint64_t tm_ctr;
1388     uint64_t tm_fpscr;
1389     uint64_t tm_amr;
1390     uint64_t tm_ppr;
1391     uint64_t tm_vrsave;
1392     uint32_t tm_vscr;
1393     uint64_t tm_dscr;
1394     uint64_t tm_tar;
1400     QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
1406     uint64_t pmu_base_time;