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1ef7d21a |
| 10-Feb-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: add --cpu parameter With the --cpu parameter, turbostat prints only lines for the specified set of CPUs: sudo ./turbostat --quiet --show Core,CPU --cpu 0,
tools/power turbostat: add --cpu parameter With the --cpu parameter, turbostat prints only lines for the specified set of CPUs: sudo ./turbostat --quiet --show Core,CPU --cpu 0,1,3..5,6-7 Core CPU - - 0 0 0 4 1 1 1 5 2 6 3 3 3 7 Signed-off-by: Len Brown <len.brown@intel.com>
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41618e63 |
| 09-Feb-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: print sysfs C-state stats When turbostat shows % of time in a CPU idle power state, it has always been showing information from underlying hardware residency c
tools/power turbostat: print sysfs C-state stats When turbostat shows % of time in a CPU idle power state, it has always been showing information from underlying hardware residency counters. While this reflects what the hardware is doing, and is thus useful for understanding the hardware, it doesn't directly tell us what Linux requested -- which is useful for tuning Linux itself. Here we add columns to turbostat to show the Linux cpuidle sub-system statistics: /sys/devices/system/cpu/cpu*/cpuidle/state*/* The first group of columns are the "usage", which is the number of times software requested that C-state in the measurement interval. eg C1 below. The second group of columns are the "time", which is the percentage of the measurement interval time that software has requested the specified C-state. eg C1% below. These software counters can be compared to the underlying hardware residency counters (eg CPU%c1 CPU%c3 CPU%c6 CPU%c7) to compare what sofware requested to what the hardware delivered. These sysfs attributes are discovered when turbostat starts, rather than being "built in". So the --show and --hide parameters do not know about these dynamic column names. However "--show sysfs" and "--hide sysfs" act on the entire group of columns: turbostat --show sysfs ... cpu4: POLL: CPUIDLE CORE POLL IDLE cpu4: C1: MWAIT 0x00 cpu4: C1E: MWAIT 0x01 cpu4: C3: MWAIT 0x10 cpu4: C6: MWAIT 0x20 cpu4: C7s: MWAIT 0x32 ... C1 C1E C3 C6 C7s C1% C1E% C3% C6% C7s% 3 6 5 1 188 0.00 0.02 0.00 0.00 99.93 0 6 5 0 58 0.00 0.16 0.02 0.00 99.70 0 0 0 0 9 0.00 0.00 0.00 0.00 99.96 0 0 0 1 24 0.00 0.00 0.00 0.02 99.93 0 0 0 0 9 0.00 0.00 0.00 0.00 99.97 0 0 0 0 32 0.00 0.00 0.00 0.00 99.96 0 0 0 0 7 0.00 0.00 0.00 0.00 99.98 2 0 0 0 36 0.00 0.00 0.00 0.00 99.97 1 0 0 0 13 0.00 0.00 0.00 0.00 99.98 Signed-off-by: Len Brown <len.brown@intel.com>
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495c7654 |
| 08-Feb-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: extend --add option to accept /sys path Previously, the --add option could specify only an MSR. Here is is extended so an arbitrary /sys attribute, as spe
tools/power turbostat: extend --add option to accept /sys path Previously, the --add option could specify only an MSR. Here is is extended so an arbitrary /sys attribute, as specified by an absolute file path name. sudo ./turbostat --add /sys/devices/system/cpu/cpu0/cpuidle/state5/usage Signed-off-by: Len Brown <len.brown@intel.com>
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ade0ebac |
| 10-Feb-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: skip unused counters on BDX Skip these two counters on BDX, as they are always zero: cc7, pc7 Signed-off-by: Len Brown <len.brown@intel.com>
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31e07522 |
| 31-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: fix decoding for GLM, DNV, SKX turbo-ratio limits Newer processors do not hard-code the the number of cpus in each bin to {1, 2, 3, 4, 5, 6, 7, 8} Rather, they ca
tools/power turbostat: fix decoding for GLM, DNV, SKX turbo-ratio limits Newer processors do not hard-code the the number of cpus in each bin to {1, 2, 3, 4, 5, 6, 7, 8} Rather, they can specify any number of CPUS in each of the 8 bins: eg. ... 37 * 100.0 = 3600.0 MHz max turbo 4 active cores 38 * 100.0 = 3700.0 MHz max turbo 3 active cores 39 * 100.0 = 3800.0 MHz max turbo 2 active cores 39 * 100.0 = 3900.0 MHz max turbo 1 active cores could now look something like this: ... 37 * 100.0 = 3600.0 MHz max turbo 16 active cores 38 * 100.0 = 3700.0 MHz max turbo 8 active cores 39 * 100.0 = 3800.0 MHz max turbo 4 active cores 39 * 100.0 = 3900.0 MHz max turbo 2 active cores Signed-off-by: Len Brown <len.brown@intel.com>
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34c76197 |
| 27-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: skip unused counters on SKX Skip these four counters on SKX, as they are always zero: cc3, pc3 cc7, pc7 Signed-off-by: Len Brown <len.brown@intel.com>
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7170a374 |
| 27-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: Denverton: use HW CC1 counter, skip C3, C7 The CC1 column in tubostat can be computed by subtracting the core c-state residency countes from the total Cx residency
tools/power turbostat: Denverton: use HW CC1 counter, skip C3, C7 The CC1 column in tubostat can be computed by subtracting the core c-state residency countes from the total Cx residency. CC1 = (Idle_time_as_measured by MPERF) - (all core C-states with residency counters) However, as the underlying counter reads are not atomic, error can be noticed in this calculations, especially when the numbers are small. Denverton has a hardware CC1 residency counter to improve the accuracy of the cc1 statistic -- use it. At the same time, Denverton has no concept of CC3, PC3, CC7, PC7, so skip collecting and printing those columns. Finally, a note of clarification. Turbostat prints the standard PC2 residency counter, but on Denverton hardware, that actually means PC1E. Turbostat prints the standard PC6 residency counter, but on Denverton hardware, that actually means PC2. At this point, we document that differnce in this commit message, rather than adding a quirk to the software. Signed-off-by: Len Brown <len.brown@intel.com>
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ac01ac13 |
| 27-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: initial Gemini Lake SOC support Gemini Lake is similar to Apollo Lake (Broxton/Goldmont) Signed-off-by: Len Brown <len.brown@intel.com>
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0f47c08d |
| 26-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: bug fixes to --add, --show/--hide features Fix a bug with --add, where the title of the column is un-initialized if not specified by the user. The initial
tools/power turbostat: bug fixes to --add, --show/--hide features Fix a bug with --add, where the title of the column is un-initialized if not specified by the user. The initial implementation of --show and --hide neglected to handle the pc8/pc9/pc10 counters. Fix a bug where "--show Core" only worked with --debug Reported-by: Wendy Wang <wendy.wang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
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008d396e |
| 09-Feb-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: use tsc_tweak everwhere it is needed The CPU ticks at a rate in the "bus clock" domain. eg. 100 MHz * bus_ratio. On newer processors, the TSC has been mov
tools/power turbostat: use tsc_tweak everwhere it is needed The CPU ticks at a rate in the "bus clock" domain. eg. 100 MHz * bus_ratio. On newer processors, the TSC has been moved out of this BCLK domain and into a separate crystal-clock domain. While the TSC ticks "close to" the base frequency, those that look closely at the numbers will notice small errors in calculations that mix units of TSC clocks and bus clocks. "tsc_tweak" was introduced to address the most visible mixing -- the %Busy and the the Busy_MHz calculations. (A simplification as since removed TSC from the BusyMHz calculation) Here we apply the tsc_tweak to everyplace where BCLK and TSC units are mixed. The results is that on a system which is 100% idle, the sum of the C-states are now much more likely to be closer to 100%. Reported-by: Travis Downs <travis.downs@gmail.com> Signed-off-by: Len Brown <len.brown@intel.com>
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96e47158 |
| 21-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: print system config, unless --quiet Some users want turbostat to tell them everything, by default. Some users want turbostat to be quiet, by default. I fi
tools/power turbostat: print system config, unless --quiet Some users want turbostat to tell them everything, by default. Some users want turbostat to be quiet, by default. I find that I'm in the 1st camp, and so I've never liked needing to type the --debug parameter to decode the system configuration. So here we change the default and print the system configuration, by default. (The --debug option is now un-documented, though it does still exist for debugging turbostat internals) When you do not want to see the system configuration header, use the new "--quiet" option. Signed-off-by: Len Brown <len.brown@intel.com>
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fee86541 |
| 21-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: show all columns, independent of --debug Some time ago, turbostat overflowed 80 columns. So on the assumption that a "casual" user would always want topol
tools/power turbostat: show all columns, independent of --debug Some time ago, turbostat overflowed 80 columns. So on the assumption that a "casual" user would always want topology and frequency columns, we hid the rest of the columns and the system configuration decoding behind the --debug option. Not everybody liked that change -- including me. I use --debug 99% of the time... Well, now we have "-o file" to put turbostat output into a file, so unless you are watching real-time in a small window, column count is less frequently a factor. And more recently, we got the "--hide columnA,columnB" option to specify columns to skip. So now we "un-hide" the rest of the columns from behind --debug, and show them all, by default. Signed-off-by: Len Brown <len.brown@intel.com>
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33148d67 |
| 21-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: decode MSR_MISC_FEATURE_CONTROL useful for observing if the BIOS disabled prefetch Not architectural, but docuemented as present on NHM, SNB and is present on
tools/power turbostat: decode MSR_MISC_FEATURE_CONTROL useful for observing if the BIOS disabled prefetch Not architectural, but docuemented as present on NHM, SNB and is present on others. Signed-off-by: Len Brown <len.brown@intel.com>
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b3a34e93 |
| 20-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: decode CPUID(6).TURBO show the CPUID feature for turbo to clarify the case when it may not be shown in MISC_ENABLE CPUID(6): APERF, TURBO, DTS, PTM, No-HW
tools/power turbostat: decode CPUID(6).TURBO show the CPUID feature for turbo to clarify the case when it may not be shown in MISC_ENABLE CPUID(6): APERF, TURBO, DTS, PTM, No-HWP, No-HWPnotify, No-HWPwindow, No-HWPepp, No-HWPpkg, EPB cpu4: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT TURBO) Signed-off-by: Len Brown <len.brown@intel.com>
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0f7887c4 |
| 12-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: dump Atom P-states correctly Turbostat dumps MSR_TURBO_RATIO_LIMIT on Core Architecture. But Atom Architecture uses MSR_ATOM_CORE_RATIOS and MSR_ATOM_CORE_TURB
tools/power turbostat: dump Atom P-states correctly Turbostat dumps MSR_TURBO_RATIO_LIMIT on Core Architecture. But Atom Architecture uses MSR_ATOM_CORE_RATIOS and MSR_ATOM_CORE_TURBO_RATIOS. Signed-off-by: Len Brown <len.brown@intel.com>
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e6512624 |
| 11-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: further decode MSR_IA32_MISC_ENABLE Decode MISC_ENABLE.NO_TURBO, also use the #defines in msr-index.h for decoding this register cpu0: MSR_IA32_MISC_ENABL
tools/power turbostat: further decode MSR_IA32_MISC_ENABLE Decode MISC_ENABLE.NO_TURBO, also use the #defines in msr-index.h for decoding this register cpu0: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT TURBO) Although it is not architectural, decode also MSR_IA32_MISC_ENABLE.prefetch-disable (bit-9). documented to be present on: Core, P4, Intel-Xeon reserved on: Atom, Silvermont, Nehalem, SNB, PHI ec. Signed-off-by: Len Brown <len.brown@intel.com>
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710f273b |
| 11-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: add precision to --debug frequency output Add a digit of precision to the --debug output for frequency range. This is useful when BCLK is not an integer.
tools/power turbostat: add precision to --debug frequency output Add a digit of precision to the --debug output for frequency range. This is useful when BCLK is not an integer. old: 6 * 83 = 500 MHz max efficiency frequency 26 * 83 = 2166 MHz base frequency new: 6 * 83.3 = 499.8 MHz max efficiency frequency 26 * 83.3 = 2165.8 MHz base frequency Signed-off-by: Len Brown <len.brown@intel.com>
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0539ba11 |
| 09-Feb-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: Baytrail c-state support The Baytrail SOC, with its Silvermont core, has some unique properties: 1. a hardware CC1 residency counter 2. a module-c6 reside
tools/power turbostat: Baytrail c-state support The Baytrail SOC, with its Silvermont core, has some unique properties: 1. a hardware CC1 residency counter 2. a module-c6 residency counter 3. a package-c6 counter at traditional package-c7 counter address. The SOC does not support c3, pc3, c7 or pc7 counters. Signed-off-by: Len Brown <len.brown@intel.com>
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1df2e55a |
| 07-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: use new name for MSR_PKG_CST_CONFIG_CONTROL Previously called MSR_NHM_SNB_PKG_CST_CFG_CTL Signed-off-by: Len Brown <len.brown@intel.com>
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f2642888 |
| 07-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: update MSR_PKG_CST_CONFIG_CONTROL decoding AMT value 0 is unlimited, not PC0 Signed-off-by: Len Brown <len.brown@intel.com>
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8f6196c1 |
| 07-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: Baytrail: remove debug line in quiet mode Without --debug, a debug line was printed on Baytrail: SLM BCLK: 83.3 Mhz Signed-off-by: Len Brown <len.bro
tools/power turbostat: Baytrail: remove debug line in quiet mode Without --debug, a debug line was printed on Baytrail: SLM BCLK: 83.3 Mhz Signed-off-by: Len Brown <len.brown@intel.com>
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71616c8e |
| 07-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: decode Baytrail CC6 and MC6 demotion configuration with --debug, see: cpu0: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x00000000 (DISable-CC6-Demotion) cpu0: MSR_MC
tools/power turbostat: decode Baytrail CC6 and MC6 demotion configuration with --debug, see: cpu0: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x00000000 (DISable-CC6-Demotion) cpu0: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x00000000 (DISable-MC6-Demotion) Note that the hardware default is to enable demotion, and Linux started clearing these registers in 3.17. Signed-off-by: Len Brown <len.brown@intel.com>
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cf4cbe53 |
| 01-Jan-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: BYT does not have MSR_MISC_PWR_MGMT and so --debug fails with: turbostat: msr 1 offset 0x1aa read failed: Input/output error It seems that baytrail,
tools/power turbostat: BYT does not have MSR_MISC_PWR_MGMT and so --debug fails with: turbostat: msr 1 offset 0x1aa read failed: Input/output error It seems that baytrail, and airmont do not have this MSR. It is included in subsequent Goldmont Atom. Signed-off-by: Len Brown <len.brown@intel.com>
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812db3f7 |
| 09-Feb-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: Add --show and --hide parameters Add the "--show" and "--hide" cmdline parameters. By default, turbostat shows all columns. turbostat --hide counter_
tools/power turbostat: Add --show and --hide parameters Add the "--show" and "--hide" cmdline parameters. By default, turbostat shows all columns. turbostat --hide counter_list will continue showing all columns, except for those listed. turbostat --show counter_list will show _only_ the listed columns These features work for built-in counters, and have no effect on columns added with the --add parameter. Signed-off-by: Len Brown <len.brown@intel.com>
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678a3bd1 |
| 09-Feb-2017 |
Len Brown <len.brown@intel.com> |
tools/power turbostat: fix bugs in --add option When --add was used more than once, overflowed buffers caused some counters to be stored on top of others, corrupting the results. Si
tools/power turbostat: fix bugs in --add option When --add was used more than once, overflowed buffers caused some counters to be stored on top of others, corrupting the results. Simplify the code by simply reserving space for up to 16 added counters per each cpu, core, package. Per-cpu added counters were being printed only per-core. Signed-off-by: Len Brown <len.brown@intel.com>
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