1 /* 2 * turbostat -- show CPU frequency and C-state residency 3 * on modern Intel turbo-capable processors. 4 * 5 * Copyright (c) 2013 Intel Corporation. 6 * Len Brown <len.brown@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #define _GNU_SOURCE 23 #include MSRHEADER 24 #include INTEL_FAMILY_HEADER 25 #include <stdarg.h> 26 #include <stdio.h> 27 #include <err.h> 28 #include <unistd.h> 29 #include <sys/types.h> 30 #include <sys/wait.h> 31 #include <sys/stat.h> 32 #include <sys/resource.h> 33 #include <fcntl.h> 34 #include <signal.h> 35 #include <sys/time.h> 36 #include <stdlib.h> 37 #include <getopt.h> 38 #include <dirent.h> 39 #include <string.h> 40 #include <ctype.h> 41 #include <sched.h> 42 #include <time.h> 43 #include <cpuid.h> 44 #include <linux/capability.h> 45 #include <errno.h> 46 47 char *proc_stat = "/proc/stat"; 48 FILE *outf; 49 int *fd_percpu; 50 struct timespec interval_ts = {5, 0}; 51 unsigned int debug; 52 unsigned int quiet; 53 unsigned int rapl_joules; 54 unsigned int summary_only; 55 unsigned int dump_only; 56 unsigned int do_snb_cstates; 57 unsigned int do_knl_cstates; 58 unsigned int do_skl_residency; 59 unsigned int do_slm_cstates; 60 unsigned int use_c1_residency_msr; 61 unsigned int has_aperf; 62 unsigned int has_epb; 63 unsigned int do_irtl_snb; 64 unsigned int do_irtl_hsw; 65 unsigned int units = 1000000; /* MHz etc */ 66 unsigned int genuine_intel; 67 unsigned int has_invariant_tsc; 68 unsigned int do_nhm_platform_info; 69 unsigned int no_MSR_MISC_PWR_MGMT; 70 unsigned int aperf_mperf_multiplier = 1; 71 double bclk; 72 double base_hz; 73 unsigned int has_base_hz; 74 double tsc_tweak = 1.0; 75 unsigned int show_pkg_only; 76 unsigned int show_core_only; 77 char *output_buffer, *outp; 78 unsigned int do_rapl; 79 unsigned int do_dts; 80 unsigned int do_ptm; 81 unsigned long long gfx_cur_rc6_ms; 82 unsigned int gfx_cur_mhz; 83 unsigned int tcc_activation_temp; 84 unsigned int tcc_activation_temp_override; 85 double rapl_power_units, rapl_time_units; 86 double rapl_dram_energy_units, rapl_energy_units; 87 double rapl_joule_counter_range; 88 unsigned int do_core_perf_limit_reasons; 89 unsigned int do_gfx_perf_limit_reasons; 90 unsigned int do_ring_perf_limit_reasons; 91 unsigned int crystal_hz; 92 unsigned long long tsc_hz; 93 int base_cpu; 94 double discover_bclk(unsigned int family, unsigned int model); 95 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 96 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 97 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 98 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 99 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 100 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 101 unsigned int has_misc_feature_control; 102 103 #define RAPL_PKG (1 << 0) 104 /* 0x610 MSR_PKG_POWER_LIMIT */ 105 /* 0x611 MSR_PKG_ENERGY_STATUS */ 106 #define RAPL_PKG_PERF_STATUS (1 << 1) 107 /* 0x613 MSR_PKG_PERF_STATUS */ 108 #define RAPL_PKG_POWER_INFO (1 << 2) 109 /* 0x614 MSR_PKG_POWER_INFO */ 110 111 #define RAPL_DRAM (1 << 3) 112 /* 0x618 MSR_DRAM_POWER_LIMIT */ 113 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 114 #define RAPL_DRAM_PERF_STATUS (1 << 4) 115 /* 0x61b MSR_DRAM_PERF_STATUS */ 116 #define RAPL_DRAM_POWER_INFO (1 << 5) 117 /* 0x61c MSR_DRAM_POWER_INFO */ 118 119 #define RAPL_CORES_POWER_LIMIT (1 << 6) 120 /* 0x638 MSR_PP0_POWER_LIMIT */ 121 #define RAPL_CORE_POLICY (1 << 7) 122 /* 0x63a MSR_PP0_POLICY */ 123 124 #define RAPL_GFX (1 << 8) 125 /* 0x640 MSR_PP1_POWER_LIMIT */ 126 /* 0x641 MSR_PP1_ENERGY_STATUS */ 127 /* 0x642 MSR_PP1_POLICY */ 128 129 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 130 /* 0x639 MSR_PP0_ENERGY_STATUS */ 131 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 132 #define TJMAX_DEFAULT 100 133 134 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 135 136 /* 137 * buffer size used by sscanf() for added column names 138 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 139 */ 140 #define NAME_BYTES 20 141 142 int backwards_count; 143 char *progname; 144 145 cpu_set_t *cpu_present_set, *cpu_affinity_set; 146 size_t cpu_present_setsize, cpu_affinity_setsize; 147 #define MAX_ADDED_COUNTERS 16 148 149 struct thread_data { 150 unsigned long long tsc; 151 unsigned long long aperf; 152 unsigned long long mperf; 153 unsigned long long c1; 154 unsigned int irq_count; 155 unsigned int smi_count; 156 unsigned int cpu_id; 157 unsigned int flags; 158 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 159 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 160 unsigned long long counter[MAX_ADDED_COUNTERS]; 161 } *thread_even, *thread_odd; 162 163 struct core_data { 164 unsigned long long c3; 165 unsigned long long c6; 166 unsigned long long c7; 167 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 168 unsigned int core_temp_c; 169 unsigned int core_id; 170 unsigned long long counter[MAX_ADDED_COUNTERS]; 171 } *core_even, *core_odd; 172 173 struct pkg_data { 174 unsigned long long pc2; 175 unsigned long long pc3; 176 unsigned long long pc6; 177 unsigned long long pc7; 178 unsigned long long pc8; 179 unsigned long long pc9; 180 unsigned long long pc10; 181 unsigned long long pkg_wtd_core_c0; 182 unsigned long long pkg_any_core_c0; 183 unsigned long long pkg_any_gfxe_c0; 184 unsigned long long pkg_both_core_gfxe_c0; 185 long long gfx_rc6_ms; 186 unsigned int gfx_mhz; 187 unsigned int package_id; 188 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 189 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 190 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 191 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 192 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 193 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 194 unsigned int pkg_temp_c; 195 unsigned long long counter[MAX_ADDED_COUNTERS]; 196 } *package_even, *package_odd; 197 198 #define ODD_COUNTERS thread_odd, core_odd, package_odd 199 #define EVEN_COUNTERS thread_even, core_even, package_even 200 201 #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \ 202 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \ 203 topo.num_threads_per_core + \ 204 (core_no) * topo.num_threads_per_core + (thread_no)) 205 #define GET_CORE(core_base, core_no, pkg_no) \ 206 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no)) 207 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 208 209 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; 210 enum counter_type {COUNTER_CYCLES, COUNTER_SECONDS}; 211 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; 212 213 struct msr_counter { 214 unsigned int msr_num; 215 char name[NAME_BYTES]; 216 unsigned int width; 217 enum counter_type type; 218 enum counter_format format; 219 struct msr_counter *next; 220 unsigned int flags; 221 #define FLAGS_HIDE (1 << 0) 222 #define FLAGS_SHOW (1 << 1) 223 }; 224 225 struct sys_counters { 226 unsigned int added_thread_counters; 227 unsigned int added_core_counters; 228 unsigned int added_package_counters; 229 struct msr_counter *tp; 230 struct msr_counter *cp; 231 struct msr_counter *pp; 232 } sys; 233 234 struct system_summary { 235 struct thread_data threads; 236 struct core_data cores; 237 struct pkg_data packages; 238 } average; 239 240 241 struct topo_params { 242 int num_packages; 243 int num_cpus; 244 int num_cores; 245 int max_cpu_num; 246 int num_cores_per_pkg; 247 int num_threads_per_core; 248 } topo; 249 250 struct timeval tv_even, tv_odd, tv_delta; 251 252 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 253 int *irqs_per_cpu; /* indexed by cpu_num */ 254 255 void setup_all_buffers(void); 256 257 int cpu_is_not_present(int cpu) 258 { 259 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 260 } 261 /* 262 * run func(thread, core, package) in topology order 263 * skip non-present cpus 264 */ 265 266 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 267 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 268 { 269 int retval, pkg_no, core_no, thread_no; 270 271 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 272 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { 273 for (thread_no = 0; thread_no < 274 topo.num_threads_per_core; ++thread_no) { 275 struct thread_data *t; 276 struct core_data *c; 277 struct pkg_data *p; 278 279 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); 280 281 if (cpu_is_not_present(t->cpu_id)) 282 continue; 283 284 c = GET_CORE(core_base, core_no, pkg_no); 285 p = GET_PKG(pkg_base, pkg_no); 286 287 retval = func(t, c, p); 288 if (retval) 289 return retval; 290 } 291 } 292 } 293 return 0; 294 } 295 296 int cpu_migrate(int cpu) 297 { 298 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 299 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 300 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 301 return -1; 302 else 303 return 0; 304 } 305 int get_msr_fd(int cpu) 306 { 307 char pathname[32]; 308 int fd; 309 310 fd = fd_percpu[cpu]; 311 312 if (fd) 313 return fd; 314 315 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 316 fd = open(pathname, O_RDONLY); 317 if (fd < 0) 318 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 319 320 fd_percpu[cpu] = fd; 321 322 return fd; 323 } 324 325 int get_msr(int cpu, off_t offset, unsigned long long *msr) 326 { 327 ssize_t retval; 328 329 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 330 331 if (retval != sizeof *msr) 332 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 333 334 return 0; 335 } 336 337 /* 338 * Each string in this array is compared in --show and --hide cmdline. 339 * Thus, strings that are proper sub-sets must follow their more specific peers. 340 */ 341 struct msr_counter bic[] = { 342 { 0x0, "Package" }, 343 { 0x0, "Avg_MHz" }, 344 { 0x0, "Bzy_MHz" }, 345 { 0x0, "TSC_MHz" }, 346 { 0x0, "IRQ" }, 347 { 0x0, "SMI", 32, 0, FORMAT_DELTA, NULL}, 348 { 0x0, "Busy%" }, 349 { 0x0, "CPU%c1" }, 350 { 0x0, "CPU%c3" }, 351 { 0x0, "CPU%c6" }, 352 { 0x0, "CPU%c7" }, 353 { 0x0, "ThreadC" }, 354 { 0x0, "CoreTmp" }, 355 { 0x0, "CoreCnt" }, 356 { 0x0, "PkgTmp" }, 357 { 0x0, "GFX%rc6" }, 358 { 0x0, "GFXMHz" }, 359 { 0x0, "Pkg%pc2" }, 360 { 0x0, "Pkg%pc3" }, 361 { 0x0, "Pkg%pc6" }, 362 { 0x0, "Pkg%pc7" }, 363 { 0x0, "Pkg%pc8" }, 364 { 0x0, "Pkg%pc9" }, 365 { 0x0, "Pkg%pc10" }, 366 { 0x0, "PkgWatt" }, 367 { 0x0, "CorWatt" }, 368 { 0x0, "GFXWatt" }, 369 { 0x0, "PkgCnt" }, 370 { 0x0, "RAMWatt" }, 371 { 0x0, "PKG_%" }, 372 { 0x0, "RAM_%" }, 373 { 0x0, "Pkg_J" }, 374 { 0x0, "Cor_J" }, 375 { 0x0, "GFX_J" }, 376 { 0x0, "RAM_J" }, 377 { 0x0, "Core" }, 378 { 0x0, "CPU" }, 379 { 0x0, "Mod%c6" }, 380 }; 381 382 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 383 #define BIC_Package (1ULL << 0) 384 #define BIC_Avg_MHz (1ULL << 1) 385 #define BIC_Bzy_MHz (1ULL << 2) 386 #define BIC_TSC_MHz (1ULL << 3) 387 #define BIC_IRQ (1ULL << 4) 388 #define BIC_SMI (1ULL << 5) 389 #define BIC_Busy (1ULL << 6) 390 #define BIC_CPU_c1 (1ULL << 7) 391 #define BIC_CPU_c3 (1ULL << 8) 392 #define BIC_CPU_c6 (1ULL << 9) 393 #define BIC_CPU_c7 (1ULL << 10) 394 #define BIC_ThreadC (1ULL << 11) 395 #define BIC_CoreTmp (1ULL << 12) 396 #define BIC_CoreCnt (1ULL << 13) 397 #define BIC_PkgTmp (1ULL << 14) 398 #define BIC_GFX_rc6 (1ULL << 15) 399 #define BIC_GFXMHz (1ULL << 16) 400 #define BIC_Pkgpc2 (1ULL << 17) 401 #define BIC_Pkgpc3 (1ULL << 18) 402 #define BIC_Pkgpc6 (1ULL << 19) 403 #define BIC_Pkgpc7 (1ULL << 20) 404 #define BIC_Pkgpc8 (1ULL << 21) 405 #define BIC_Pkgpc9 (1ULL << 22) 406 #define BIC_Pkgpc10 (1ULL << 23) 407 #define BIC_PkgWatt (1ULL << 24) 408 #define BIC_CorWatt (1ULL << 25) 409 #define BIC_GFXWatt (1ULL << 26) 410 #define BIC_PkgCnt (1ULL << 27) 411 #define BIC_RAMWatt (1ULL << 28) 412 #define BIC_PKG__ (1ULL << 29) 413 #define BIC_RAM__ (1ULL << 30) 414 #define BIC_Pkg_J (1ULL << 31) 415 #define BIC_Cor_J (1ULL << 32) 416 #define BIC_GFX_J (1ULL << 33) 417 #define BIC_RAM_J (1ULL << 34) 418 #define BIC_Core (1ULL << 35) 419 #define BIC_CPU (1ULL << 36) 420 #define BIC_Mod_c6 (1ULL << 37) 421 422 unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL; 423 unsigned long long bic_present; 424 425 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 426 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 427 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 428 429 /* 430 * bic_lookup 431 * for all the strings in comma separate name_list, 432 * set the approprate bit in return value. 433 */ 434 unsigned long long bic_lookup(char *name_list) 435 { 436 int i; 437 unsigned long long retval = 0; 438 439 while (name_list) { 440 char *comma; 441 442 comma = strchr(name_list, ','); 443 444 if (comma) 445 *comma = '\0'; 446 447 for (i = 0; i < MAX_BIC; ++i) { 448 if (!strcmp(name_list, bic[i].name)) { 449 retval |= (1ULL << i); 450 break; 451 } 452 } 453 if (i == MAX_BIC) { 454 fprintf(stderr, "Invalid counter name: %s\n", name_list); 455 exit(-1); 456 } 457 458 name_list = comma; 459 if (name_list) 460 name_list++; 461 462 } 463 return retval; 464 } 465 466 void print_header(void) 467 { 468 struct msr_counter *mp; 469 470 if (DO_BIC(BIC_Package)) 471 outp += sprintf(outp, "\tPackage"); 472 if (DO_BIC(BIC_Core)) 473 outp += sprintf(outp, "\tCore"); 474 if (DO_BIC(BIC_CPU)) 475 outp += sprintf(outp, "\tCPU"); 476 if (DO_BIC(BIC_Avg_MHz)) 477 outp += sprintf(outp, "\tAvg_MHz"); 478 if (DO_BIC(BIC_Busy)) 479 outp += sprintf(outp, "\tBusy%%"); 480 if (DO_BIC(BIC_Bzy_MHz)) 481 outp += sprintf(outp, "\tBzy_MHz"); 482 if (DO_BIC(BIC_TSC_MHz)) 483 outp += sprintf(outp, "\tTSC_MHz"); 484 485 if (DO_BIC(BIC_IRQ)) 486 outp += sprintf(outp, "\tIRQ"); 487 if (DO_BIC(BIC_SMI)) 488 outp += sprintf(outp, "\tSMI"); 489 490 if (DO_BIC(BIC_CPU_c1)) 491 outp += sprintf(outp, "\tCPU%%c1"); 492 493 for (mp = sys.tp; mp; mp = mp->next) { 494 if (mp->format == FORMAT_RAW) { 495 if (mp->width == 64) 496 outp += sprintf(outp, "\t%18.18s", mp->name); 497 else 498 outp += sprintf(outp, "\t%10.10s", mp->name); 499 } else { 500 outp += sprintf(outp, "\t%-7.7s", mp->name); 501 } 502 } 503 504 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) 505 outp += sprintf(outp, "\tCPU%%c3"); 506 if (DO_BIC(BIC_CPU_c6)) 507 outp += sprintf(outp, "\tCPU%%c6"); 508 if (DO_BIC(BIC_CPU_c7)) 509 outp += sprintf(outp, "\tCPU%%c7"); 510 511 if (DO_BIC(BIC_Mod_c6)) 512 outp += sprintf(outp, "\tMod%%c6"); 513 514 if (DO_BIC(BIC_CoreTmp)) 515 outp += sprintf(outp, "\tCoreTmp"); 516 517 for (mp = sys.cp; mp; mp = mp->next) { 518 if (mp->format == FORMAT_RAW) { 519 if (mp->width == 64) 520 outp += sprintf(outp, "\t%18.18s", mp->name); 521 else 522 outp += sprintf(outp, "\t%10.10s", mp->name); 523 } else { 524 outp += sprintf(outp, "\t%-7.7s", mp->name); 525 } 526 } 527 528 if (DO_BIC(BIC_PkgTmp)) 529 outp += sprintf(outp, "\tPkgTmp"); 530 531 if (DO_BIC(BIC_GFX_rc6)) 532 outp += sprintf(outp, "\tGFX%%rc6"); 533 534 if (DO_BIC(BIC_GFXMHz)) 535 outp += sprintf(outp, "\tGFXMHz"); 536 537 if (do_skl_residency) { 538 outp += sprintf(outp, "\tTotl%%C0"); 539 outp += sprintf(outp, "\tAny%%C0"); 540 outp += sprintf(outp, "\tGFX%%C0"); 541 outp += sprintf(outp, "\tCPUGFX%%"); 542 } 543 544 if (DO_BIC(BIC_Pkgpc2)) 545 outp += sprintf(outp, "\tPkg%%pc2"); 546 if (DO_BIC(BIC_Pkgpc3)) 547 outp += sprintf(outp, "\tPkg%%pc3"); 548 if (DO_BIC(BIC_Pkgpc6)) 549 outp += sprintf(outp, "\tPkg%%pc6"); 550 if (DO_BIC(BIC_Pkgpc7)) 551 outp += sprintf(outp, "\tPkg%%pc7"); 552 if (DO_BIC(BIC_Pkgpc8)) 553 outp += sprintf(outp, "\tPkg%%pc8"); 554 if (DO_BIC(BIC_Pkgpc9)) 555 outp += sprintf(outp, "\tPkg%%pc9"); 556 if (DO_BIC(BIC_Pkgpc10)) 557 outp += sprintf(outp, "\tPk%%pc10"); 558 559 if (do_rapl && !rapl_joules) { 560 if (DO_BIC(BIC_PkgWatt)) 561 outp += sprintf(outp, "\tPkgWatt"); 562 if (DO_BIC(BIC_CorWatt)) 563 outp += sprintf(outp, "\tCorWatt"); 564 if (DO_BIC(BIC_GFXWatt)) 565 outp += sprintf(outp, "\tGFXWatt"); 566 if (DO_BIC(BIC_RAMWatt)) 567 outp += sprintf(outp, "\tRAMWatt"); 568 if (DO_BIC(BIC_PKG__)) 569 outp += sprintf(outp, "\tPKG_%%"); 570 if (DO_BIC(BIC_RAM__)) 571 outp += sprintf(outp, "\tRAM_%%"); 572 } else if (do_rapl && rapl_joules) { 573 if (DO_BIC(BIC_Pkg_J)) 574 outp += sprintf(outp, "\tPkg_J"); 575 if (DO_BIC(BIC_Cor_J)) 576 outp += sprintf(outp, "\tCor_J"); 577 if (DO_BIC(BIC_GFX_J)) 578 outp += sprintf(outp, "\tGFX_J"); 579 if (DO_BIC(BIC_RAM_J)) 580 outp += sprintf(outp, "\tRAM_J"); 581 if (DO_BIC(BIC_PKG__)) 582 outp += sprintf(outp, "\tPKG_%%"); 583 if (DO_BIC(BIC_RAM__)) 584 outp += sprintf(outp, "\tRAM_%%"); 585 } 586 for (mp = sys.pp; mp; mp = mp->next) { 587 if (mp->format == FORMAT_RAW) { 588 if (mp->width == 64) 589 outp += sprintf(outp, "\t%18.18s", mp->name); 590 else 591 outp += sprintf(outp, "\t%10.10s", mp->name); 592 } else { 593 outp += sprintf(outp, "\t%-7.7s", mp->name); 594 } 595 } 596 597 outp += sprintf(outp, "\n"); 598 } 599 600 int dump_counters(struct thread_data *t, struct core_data *c, 601 struct pkg_data *p) 602 { 603 int i; 604 struct msr_counter *mp; 605 606 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 607 608 if (t) { 609 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 610 t->cpu_id, t->flags); 611 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 612 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 613 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 614 outp += sprintf(outp, "c1: %016llX\n", t->c1); 615 616 if (DO_BIC(BIC_IRQ)) 617 outp += sprintf(outp, "IRQ: %08X\n", t->irq_count); 618 if (DO_BIC(BIC_SMI)) 619 outp += sprintf(outp, "SMI: %08X\n", t->smi_count); 620 621 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 622 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", 623 i, mp->msr_num, t->counter[i]); 624 } 625 } 626 627 if (c) { 628 outp += sprintf(outp, "core: %d\n", c->core_id); 629 outp += sprintf(outp, "c3: %016llX\n", c->c3); 630 outp += sprintf(outp, "c6: %016llX\n", c->c6); 631 outp += sprintf(outp, "c7: %016llX\n", c->c7); 632 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 633 634 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 635 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", 636 i, mp->msr_num, c->counter[i]); 637 } 638 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 639 } 640 641 if (p) { 642 outp += sprintf(outp, "package: %d\n", p->package_id); 643 644 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 645 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 646 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 647 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 648 649 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 650 if (DO_BIC(BIC_Pkgpc3)) 651 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 652 if (DO_BIC(BIC_Pkgpc6)) 653 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 654 if (DO_BIC(BIC_Pkgpc7)) 655 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 656 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 657 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 658 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 659 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); 660 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); 661 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); 662 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); 663 outp += sprintf(outp, "Throttle PKG: %0X\n", 664 p->rapl_pkg_perf_status); 665 outp += sprintf(outp, "Throttle RAM: %0X\n", 666 p->rapl_dram_perf_status); 667 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 668 669 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 670 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", 671 i, mp->msr_num, p->counter[i]); 672 } 673 } 674 675 outp += sprintf(outp, "\n"); 676 677 return 0; 678 } 679 680 /* 681 * column formatting convention & formats 682 */ 683 int format_counters(struct thread_data *t, struct core_data *c, 684 struct pkg_data *p) 685 { 686 double interval_float, tsc; 687 char *fmt8; 688 int i; 689 struct msr_counter *mp; 690 691 /* if showing only 1st thread in core and this isn't one, bail out */ 692 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 693 return 0; 694 695 /* if showing only 1st thread in pkg and this isn't one, bail out */ 696 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 697 return 0; 698 699 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; 700 701 tsc = t->tsc * tsc_tweak; 702 703 /* topo columns, print blanks on 1st (average) line */ 704 if (t == &average.threads) { 705 if (DO_BIC(BIC_Package)) 706 outp += sprintf(outp, "\t-"); 707 if (DO_BIC(BIC_Core)) 708 outp += sprintf(outp, "\t-"); 709 if (DO_BIC(BIC_CPU)) 710 outp += sprintf(outp, "\t-"); 711 } else { 712 if (DO_BIC(BIC_Package)) { 713 if (p) 714 outp += sprintf(outp, "\t%d", p->package_id); 715 else 716 outp += sprintf(outp, "\t-"); 717 } 718 if (DO_BIC(BIC_Core)) { 719 if (c) 720 outp += sprintf(outp, "\t%d", c->core_id); 721 else 722 outp += sprintf(outp, "\t-"); 723 } 724 if (DO_BIC(BIC_CPU)) 725 outp += sprintf(outp, "\t%d", t->cpu_id); 726 } 727 728 if (DO_BIC(BIC_Avg_MHz)) 729 outp += sprintf(outp, "\t%.0f", 730 1.0 / units * t->aperf / interval_float); 731 732 if (DO_BIC(BIC_Busy)) 733 outp += sprintf(outp, "\t%.2f", 100.0 * t->mperf/tsc); 734 735 if (DO_BIC(BIC_Bzy_MHz)) { 736 if (has_base_hz) 737 outp += sprintf(outp, "\t%.0f", base_hz / units * t->aperf / t->mperf); 738 else 739 outp += sprintf(outp, "\t%.0f", 740 tsc / units * t->aperf / t->mperf / interval_float); 741 } 742 743 if (DO_BIC(BIC_TSC_MHz)) 744 outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float); 745 746 /* IRQ */ 747 if (DO_BIC(BIC_IRQ)) 748 outp += sprintf(outp, "\t%d", t->irq_count); 749 750 /* SMI */ 751 if (DO_BIC(BIC_SMI)) 752 outp += sprintf(outp, "\t%d", t->smi_count); 753 754 /* C1 */ 755 if (DO_BIC(BIC_CPU_c1)) 756 outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/tsc); 757 758 /* Added counters */ 759 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 760 if (mp->format == FORMAT_RAW) { 761 if (mp->width == 32) 762 outp += sprintf(outp, "\t0x%08lx", (unsigned long) t->counter[i]); 763 else 764 outp += sprintf(outp, "\t0x%016llx", t->counter[i]); 765 } else if (mp->format == FORMAT_DELTA) { 766 outp += sprintf(outp, "\t%lld", t->counter[i]); 767 } else if (mp->format == FORMAT_PERCENT) { 768 outp += sprintf(outp, "\t%.2f", 100.0 * t->counter[i]/tsc); 769 } 770 } 771 772 /* print per-core data only for 1st thread in core */ 773 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 774 goto done; 775 776 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) 777 outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/tsc); 778 if (DO_BIC(BIC_CPU_c6)) 779 outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/tsc); 780 if (DO_BIC(BIC_CPU_c7)) 781 outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/tsc); 782 783 /* Mod%c6 */ 784 if (DO_BIC(BIC_Mod_c6)) 785 outp += sprintf(outp, "\t%.2f", 100.0 * c->mc6_us / tsc); 786 787 if (DO_BIC(BIC_CoreTmp)) 788 outp += sprintf(outp, "\t%d", c->core_temp_c); 789 790 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 791 if (mp->format == FORMAT_RAW) { 792 if (mp->width == 32) 793 outp += sprintf(outp, "\t0x%08lx", (unsigned long) c->counter[i]); 794 else 795 outp += sprintf(outp, "\t0x%016llx", c->counter[i]); 796 } else if (mp->format == FORMAT_DELTA) { 797 outp += sprintf(outp, "\t%lld", c->counter[i]); 798 } else if (mp->format == FORMAT_PERCENT) { 799 outp += sprintf(outp, "\t%.2f", 100.0 * c->counter[i]/tsc); 800 } 801 } 802 803 /* print per-package data only for 1st core in package */ 804 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 805 goto done; 806 807 /* PkgTmp */ 808 if (DO_BIC(BIC_PkgTmp)) 809 outp += sprintf(outp, "\t%d", p->pkg_temp_c); 810 811 /* GFXrc6 */ 812 if (DO_BIC(BIC_GFX_rc6)) { 813 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 814 outp += sprintf(outp, "\t**.**"); 815 } else { 816 outp += sprintf(outp, "\t%.2f", 817 p->gfx_rc6_ms / 10.0 / interval_float); 818 } 819 } 820 821 /* GFXMHz */ 822 if (DO_BIC(BIC_GFXMHz)) 823 outp += sprintf(outp, "\t%d", p->gfx_mhz); 824 825 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 826 if (do_skl_residency) { 827 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_wtd_core_c0/tsc); 828 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_core_c0/tsc); 829 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_gfxe_c0/tsc); 830 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_both_core_gfxe_c0/tsc); 831 } 832 833 if (DO_BIC(BIC_Pkgpc2)) 834 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc2/tsc); 835 if (DO_BIC(BIC_Pkgpc3)) 836 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc3/tsc); 837 if (DO_BIC(BIC_Pkgpc6)) 838 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc6/tsc); 839 if (DO_BIC(BIC_Pkgpc7)) 840 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc7/tsc); 841 if (DO_BIC(BIC_Pkgpc8)) 842 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc8/tsc); 843 if (DO_BIC(BIC_Pkgpc9)) 844 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc9/tsc); 845 if (DO_BIC(BIC_Pkgpc10)) 846 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc10/tsc); 847 848 /* 849 * If measurement interval exceeds minimum RAPL Joule Counter range, 850 * indicate that results are suspect by printing "**" in fraction place. 851 */ 852 if (interval_float < rapl_joule_counter_range) 853 fmt8 = "\t%.2f"; 854 else 855 fmt8 = "%6.0f**"; 856 857 if (DO_BIC(BIC_PkgWatt)) 858 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float); 859 if (DO_BIC(BIC_CorWatt)) 860 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float); 861 if (DO_BIC(BIC_GFXWatt)) 862 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float); 863 if (DO_BIC(BIC_RAMWatt)) 864 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float); 865 if (DO_BIC(BIC_Pkg_J)) 866 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units); 867 if (DO_BIC(BIC_Cor_J)) 868 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units); 869 if (DO_BIC(BIC_GFX_J)) 870 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units); 871 if (DO_BIC(BIC_RAM_J)) 872 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units); 873 if (DO_BIC(BIC_PKG__)) 874 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 875 if (DO_BIC(BIC_RAM__)) 876 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 877 878 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 879 if (mp->format == FORMAT_RAW) { 880 if (mp->width == 32) 881 outp += sprintf(outp, "\t0x%08lx", (unsigned long) p->counter[i]); 882 else 883 outp += sprintf(outp, "\t0x%016llx", p->counter[i]); 884 } else if (mp->format == FORMAT_DELTA) { 885 outp += sprintf(outp, "\t%lld", p->counter[i]); 886 } else if (mp->format == FORMAT_PERCENT) { 887 outp += sprintf(outp, "\t%.2f", 100.0 * p->counter[i]/tsc); 888 } 889 } 890 891 done: 892 outp += sprintf(outp, "\n"); 893 894 return 0; 895 } 896 897 void flush_output_stdout(void) 898 { 899 FILE *filep; 900 901 if (outf == stderr) 902 filep = stdout; 903 else 904 filep = outf; 905 906 fputs(output_buffer, filep); 907 fflush(filep); 908 909 outp = output_buffer; 910 } 911 void flush_output_stderr(void) 912 { 913 fputs(output_buffer, outf); 914 fflush(outf); 915 outp = output_buffer; 916 } 917 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 918 { 919 static int printed; 920 921 if (!printed || !summary_only) 922 print_header(); 923 924 if (topo.num_cpus > 1) 925 format_counters(&average.threads, &average.cores, 926 &average.packages); 927 928 printed = 1; 929 930 if (summary_only) 931 return; 932 933 for_all_cpus(format_counters, t, c, p); 934 } 935 936 #define DELTA_WRAP32(new, old) \ 937 if (new > old) { \ 938 old = new - old; \ 939 } else { \ 940 old = 0x100000000 + new - old; \ 941 } 942 943 int 944 delta_package(struct pkg_data *new, struct pkg_data *old) 945 { 946 int i; 947 struct msr_counter *mp; 948 949 if (do_skl_residency) { 950 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 951 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 952 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 953 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 954 } 955 old->pc2 = new->pc2 - old->pc2; 956 if (DO_BIC(BIC_Pkgpc3)) 957 old->pc3 = new->pc3 - old->pc3; 958 if (DO_BIC(BIC_Pkgpc6)) 959 old->pc6 = new->pc6 - old->pc6; 960 if (DO_BIC(BIC_Pkgpc7)) 961 old->pc7 = new->pc7 - old->pc7; 962 old->pc8 = new->pc8 - old->pc8; 963 old->pc9 = new->pc9 - old->pc9; 964 old->pc10 = new->pc10 - old->pc10; 965 old->pkg_temp_c = new->pkg_temp_c; 966 967 /* flag an error when rc6 counter resets/wraps */ 968 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 969 old->gfx_rc6_ms = -1; 970 else 971 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 972 973 old->gfx_mhz = new->gfx_mhz; 974 975 DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 976 DELTA_WRAP32(new->energy_cores, old->energy_cores); 977 DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 978 DELTA_WRAP32(new->energy_dram, old->energy_dram); 979 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 980 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 981 982 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 983 if (mp->format == FORMAT_RAW) 984 old->counter[i] = new->counter[i]; 985 else 986 old->counter[i] = new->counter[i] - old->counter[i]; 987 } 988 989 return 0; 990 } 991 992 void 993 delta_core(struct core_data *new, struct core_data *old) 994 { 995 int i; 996 struct msr_counter *mp; 997 998 old->c3 = new->c3 - old->c3; 999 old->c6 = new->c6 - old->c6; 1000 old->c7 = new->c7 - old->c7; 1001 old->core_temp_c = new->core_temp_c; 1002 old->mc6_us = new->mc6_us - old->mc6_us; 1003 1004 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1005 if (mp->format == FORMAT_RAW) 1006 old->counter[i] = new->counter[i]; 1007 else 1008 old->counter[i] = new->counter[i] - old->counter[i]; 1009 } 1010 } 1011 1012 /* 1013 * old = new - old 1014 */ 1015 int 1016 delta_thread(struct thread_data *new, struct thread_data *old, 1017 struct core_data *core_delta) 1018 { 1019 int i; 1020 struct msr_counter *mp; 1021 1022 old->tsc = new->tsc - old->tsc; 1023 1024 /* check for TSC < 1 Mcycles over interval */ 1025 if (old->tsc < (1000 * 1000)) 1026 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1027 "You can disable all c-states by booting with \"idle=poll\"\n" 1028 "or just the deep ones with \"processor.max_cstate=1\""); 1029 1030 old->c1 = new->c1 - old->c1; 1031 1032 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1033 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1034 old->aperf = new->aperf - old->aperf; 1035 old->mperf = new->mperf - old->mperf; 1036 } else { 1037 return -1; 1038 } 1039 } 1040 1041 1042 if (use_c1_residency_msr) { 1043 /* 1044 * Some models have a dedicated C1 residency MSR, 1045 * which should be more accurate than the derivation below. 1046 */ 1047 } else { 1048 /* 1049 * As counter collection is not atomic, 1050 * it is possible for mperf's non-halted cycles + idle states 1051 * to exceed TSC's all cycles: show c1 = 0% in that case. 1052 */ 1053 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc) 1054 old->c1 = 0; 1055 else { 1056 /* normal case, derive c1 */ 1057 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1058 - core_delta->c6 - core_delta->c7; 1059 } 1060 } 1061 1062 if (old->mperf == 0) { 1063 if (debug > 1) 1064 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1065 old->mperf = 1; /* divide by 0 protection */ 1066 } 1067 1068 if (DO_BIC(BIC_IRQ)) 1069 old->irq_count = new->irq_count - old->irq_count; 1070 1071 if (DO_BIC(BIC_SMI)) 1072 old->smi_count = new->smi_count - old->smi_count; 1073 1074 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1075 if (mp->format == FORMAT_RAW) 1076 old->counter[i] = new->counter[i]; 1077 else 1078 old->counter[i] = new->counter[i] - old->counter[i]; 1079 } 1080 return 0; 1081 } 1082 1083 int delta_cpu(struct thread_data *t, struct core_data *c, 1084 struct pkg_data *p, struct thread_data *t2, 1085 struct core_data *c2, struct pkg_data *p2) 1086 { 1087 int retval = 0; 1088 1089 /* calculate core delta only for 1st thread in core */ 1090 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1091 delta_core(c, c2); 1092 1093 /* always calculate thread delta */ 1094 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1095 if (retval) 1096 return retval; 1097 1098 /* calculate package delta only for 1st core in package */ 1099 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1100 retval = delta_package(p, p2); 1101 1102 return retval; 1103 } 1104 1105 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1106 { 1107 int i; 1108 struct msr_counter *mp; 1109 1110 t->tsc = 0; 1111 t->aperf = 0; 1112 t->mperf = 0; 1113 t->c1 = 0; 1114 1115 t->irq_count = 0; 1116 t->smi_count = 0; 1117 1118 /* tells format_counters to dump all fields from this set */ 1119 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1120 1121 c->c3 = 0; 1122 c->c6 = 0; 1123 c->c7 = 0; 1124 c->mc6_us = 0; 1125 c->core_temp_c = 0; 1126 1127 p->pkg_wtd_core_c0 = 0; 1128 p->pkg_any_core_c0 = 0; 1129 p->pkg_any_gfxe_c0 = 0; 1130 p->pkg_both_core_gfxe_c0 = 0; 1131 1132 p->pc2 = 0; 1133 if (DO_BIC(BIC_Pkgpc3)) 1134 p->pc3 = 0; 1135 if (DO_BIC(BIC_Pkgpc6)) 1136 p->pc6 = 0; 1137 if (DO_BIC(BIC_Pkgpc7)) 1138 p->pc7 = 0; 1139 p->pc8 = 0; 1140 p->pc9 = 0; 1141 p->pc10 = 0; 1142 1143 p->energy_pkg = 0; 1144 p->energy_dram = 0; 1145 p->energy_cores = 0; 1146 p->energy_gfx = 0; 1147 p->rapl_pkg_perf_status = 0; 1148 p->rapl_dram_perf_status = 0; 1149 p->pkg_temp_c = 0; 1150 1151 p->gfx_rc6_ms = 0; 1152 p->gfx_mhz = 0; 1153 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1154 t->counter[i] = 0; 1155 1156 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1157 c->counter[i] = 0; 1158 1159 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1160 p->counter[i] = 0; 1161 } 1162 int sum_counters(struct thread_data *t, struct core_data *c, 1163 struct pkg_data *p) 1164 { 1165 int i; 1166 struct msr_counter *mp; 1167 1168 average.threads.tsc += t->tsc; 1169 average.threads.aperf += t->aperf; 1170 average.threads.mperf += t->mperf; 1171 average.threads.c1 += t->c1; 1172 1173 average.threads.irq_count += t->irq_count; 1174 average.threads.smi_count += t->smi_count; 1175 1176 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1177 if (mp->format == FORMAT_RAW) 1178 continue; 1179 average.threads.counter[i] += t->counter[i]; 1180 } 1181 1182 /* sum per-core values only for 1st thread in core */ 1183 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1184 return 0; 1185 1186 average.cores.c3 += c->c3; 1187 average.cores.c6 += c->c6; 1188 average.cores.c7 += c->c7; 1189 average.cores.mc6_us += c->mc6_us; 1190 1191 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1192 1193 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1194 if (mp->format == FORMAT_RAW) 1195 continue; 1196 average.cores.counter[i] += c->counter[i]; 1197 } 1198 1199 /* sum per-pkg values only for 1st core in pkg */ 1200 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1201 return 0; 1202 1203 if (do_skl_residency) { 1204 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1205 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1206 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1207 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1208 } 1209 1210 average.packages.pc2 += p->pc2; 1211 if (DO_BIC(BIC_Pkgpc3)) 1212 average.packages.pc3 += p->pc3; 1213 if (DO_BIC(BIC_Pkgpc6)) 1214 average.packages.pc6 += p->pc6; 1215 if (DO_BIC(BIC_Pkgpc7)) 1216 average.packages.pc7 += p->pc7; 1217 average.packages.pc8 += p->pc8; 1218 average.packages.pc9 += p->pc9; 1219 average.packages.pc10 += p->pc10; 1220 1221 average.packages.energy_pkg += p->energy_pkg; 1222 average.packages.energy_dram += p->energy_dram; 1223 average.packages.energy_cores += p->energy_cores; 1224 average.packages.energy_gfx += p->energy_gfx; 1225 1226 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1227 average.packages.gfx_mhz = p->gfx_mhz; 1228 1229 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1230 1231 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1232 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1233 1234 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1235 if (mp->format == FORMAT_RAW) 1236 continue; 1237 average.packages.counter[i] += p->counter[i]; 1238 } 1239 return 0; 1240 } 1241 /* 1242 * sum the counters for all cpus in the system 1243 * compute the weighted average 1244 */ 1245 void compute_average(struct thread_data *t, struct core_data *c, 1246 struct pkg_data *p) 1247 { 1248 int i; 1249 struct msr_counter *mp; 1250 1251 clear_counters(&average.threads, &average.cores, &average.packages); 1252 1253 for_all_cpus(sum_counters, t, c, p); 1254 1255 average.threads.tsc /= topo.num_cpus; 1256 average.threads.aperf /= topo.num_cpus; 1257 average.threads.mperf /= topo.num_cpus; 1258 average.threads.c1 /= topo.num_cpus; 1259 1260 average.cores.c3 /= topo.num_cores; 1261 average.cores.c6 /= topo.num_cores; 1262 average.cores.c7 /= topo.num_cores; 1263 average.cores.mc6_us /= topo.num_cores; 1264 1265 if (do_skl_residency) { 1266 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1267 average.packages.pkg_any_core_c0 /= topo.num_packages; 1268 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1269 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1270 } 1271 1272 average.packages.pc2 /= topo.num_packages; 1273 if (DO_BIC(BIC_Pkgpc3)) 1274 average.packages.pc3 /= topo.num_packages; 1275 if (DO_BIC(BIC_Pkgpc6)) 1276 average.packages.pc6 /= topo.num_packages; 1277 if (DO_BIC(BIC_Pkgpc7)) 1278 average.packages.pc7 /= topo.num_packages; 1279 1280 average.packages.pc8 /= topo.num_packages; 1281 average.packages.pc9 /= topo.num_packages; 1282 average.packages.pc10 /= topo.num_packages; 1283 1284 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1285 if (mp->format == FORMAT_RAW) 1286 continue; 1287 average.threads.counter[i] /= topo.num_cpus; 1288 } 1289 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1290 if (mp->format == FORMAT_RAW) 1291 continue; 1292 average.cores.counter[i] /= topo.num_cores; 1293 } 1294 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1295 if (mp->format == FORMAT_RAW) 1296 continue; 1297 average.packages.counter[i] /= topo.num_packages; 1298 } 1299 } 1300 1301 static unsigned long long rdtsc(void) 1302 { 1303 unsigned int low, high; 1304 1305 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1306 1307 return low | ((unsigned long long)high) << 32; 1308 } 1309 1310 /* 1311 * get_counters(...) 1312 * migrate to cpu 1313 * acquire and record local counters for that cpu 1314 */ 1315 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1316 { 1317 int cpu = t->cpu_id; 1318 unsigned long long msr; 1319 int aperf_mperf_retry_count = 0; 1320 struct msr_counter *mp; 1321 int i; 1322 1323 if (cpu_migrate(cpu)) { 1324 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1325 return -1; 1326 } 1327 1328 retry: 1329 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1330 1331 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1332 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1333 1334 /* 1335 * The TSC, APERF and MPERF must be read together for 1336 * APERF/MPERF and MPERF/TSC to give accurate results. 1337 * 1338 * Unfortunately, APERF and MPERF are read by 1339 * individual system call, so delays may occur 1340 * between them. If the time to read them 1341 * varies by a large amount, we re-read them. 1342 */ 1343 1344 /* 1345 * This initial dummy APERF read has been seen to 1346 * reduce jitter in the subsequent reads. 1347 */ 1348 1349 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1350 return -3; 1351 1352 t->tsc = rdtsc(); /* re-read close to APERF */ 1353 1354 tsc_before = t->tsc; 1355 1356 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1357 return -3; 1358 1359 tsc_between = rdtsc(); 1360 1361 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1362 return -4; 1363 1364 tsc_after = rdtsc(); 1365 1366 aperf_time = tsc_between - tsc_before; 1367 mperf_time = tsc_after - tsc_between; 1368 1369 /* 1370 * If the system call latency to read APERF and MPERF 1371 * differ by more than 2x, then try again. 1372 */ 1373 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1374 aperf_mperf_retry_count++; 1375 if (aperf_mperf_retry_count < 5) 1376 goto retry; 1377 else 1378 warnx("cpu%d jitter %lld %lld", 1379 cpu, aperf_time, mperf_time); 1380 } 1381 aperf_mperf_retry_count = 0; 1382 1383 t->aperf = t->aperf * aperf_mperf_multiplier; 1384 t->mperf = t->mperf * aperf_mperf_multiplier; 1385 } 1386 1387 if (DO_BIC(BIC_IRQ)) 1388 t->irq_count = irqs_per_cpu[cpu]; 1389 if (DO_BIC(BIC_SMI)) { 1390 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1391 return -5; 1392 t->smi_count = msr & 0xFFFFFFFF; 1393 } 1394 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 1395 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 1396 return -6; 1397 } 1398 1399 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1400 if (get_msr(cpu, mp->msr_num, &t->counter[i])) 1401 return -10; 1402 } 1403 1404 1405 /* collect core counters only for 1st thread in core */ 1406 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1407 return 0; 1408 1409 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) { 1410 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1411 return -6; 1412 } 1413 1414 if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) { 1415 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1416 return -7; 1417 } else if (do_knl_cstates) { 1418 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1419 return -7; 1420 } 1421 1422 if (DO_BIC(BIC_CPU_c7)) 1423 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1424 return -8; 1425 1426 if (DO_BIC(BIC_Mod_c6)) 1427 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 1428 return -8; 1429 1430 if (DO_BIC(BIC_CoreTmp)) { 1431 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1432 return -9; 1433 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1434 } 1435 1436 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1437 if (get_msr(cpu, mp->msr_num, &c->counter[i])) 1438 return -10; 1439 } 1440 1441 /* collect package counters only for 1st core in package */ 1442 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1443 return 0; 1444 1445 if (do_skl_residency) { 1446 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 1447 return -10; 1448 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 1449 return -11; 1450 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 1451 return -12; 1452 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 1453 return -13; 1454 } 1455 if (DO_BIC(BIC_Pkgpc3)) 1456 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 1457 return -9; 1458 if (DO_BIC(BIC_Pkgpc6)) { 1459 if (do_slm_cstates) { 1460 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 1461 return -10; 1462 } else { 1463 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 1464 return -10; 1465 } 1466 } 1467 1468 if (DO_BIC(BIC_Pkgpc2)) 1469 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 1470 return -11; 1471 if (DO_BIC(BIC_Pkgpc7)) 1472 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 1473 return -12; 1474 if (DO_BIC(BIC_Pkgpc8)) 1475 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 1476 return -13; 1477 if (DO_BIC(BIC_Pkgpc9)) 1478 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 1479 return -13; 1480 if (DO_BIC(BIC_Pkgpc10)) 1481 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 1482 return -13; 1483 1484 if (do_rapl & RAPL_PKG) { 1485 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 1486 return -13; 1487 p->energy_pkg = msr & 0xFFFFFFFF; 1488 } 1489 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 1490 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 1491 return -14; 1492 p->energy_cores = msr & 0xFFFFFFFF; 1493 } 1494 if (do_rapl & RAPL_DRAM) { 1495 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 1496 return -15; 1497 p->energy_dram = msr & 0xFFFFFFFF; 1498 } 1499 if (do_rapl & RAPL_GFX) { 1500 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 1501 return -16; 1502 p->energy_gfx = msr & 0xFFFFFFFF; 1503 } 1504 if (do_rapl & RAPL_PKG_PERF_STATUS) { 1505 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 1506 return -16; 1507 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 1508 } 1509 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 1510 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 1511 return -16; 1512 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 1513 } 1514 if (DO_BIC(BIC_PkgTmp)) { 1515 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 1516 return -17; 1517 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1518 } 1519 1520 if (DO_BIC(BIC_GFX_rc6)) 1521 p->gfx_rc6_ms = gfx_cur_rc6_ms; 1522 1523 if (DO_BIC(BIC_GFXMHz)) 1524 p->gfx_mhz = gfx_cur_mhz; 1525 1526 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1527 if (get_msr(cpu, mp->msr_num, &p->counter[i])) 1528 return -10; 1529 } 1530 1531 return 0; 1532 } 1533 1534 /* 1535 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 1536 * If you change the values, note they are used both in comparisons 1537 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 1538 */ 1539 1540 #define PCLUKN 0 /* Unknown */ 1541 #define PCLRSV 1 /* Reserved */ 1542 #define PCL__0 2 /* PC0 */ 1543 #define PCL__1 3 /* PC1 */ 1544 #define PCL__2 4 /* PC2 */ 1545 #define PCL__3 5 /* PC3 */ 1546 #define PCL__4 6 /* PC4 */ 1547 #define PCL__6 7 /* PC6 */ 1548 #define PCL_6N 8 /* PC6 No Retention */ 1549 #define PCL_6R 9 /* PC6 Retention */ 1550 #define PCL__7 10 /* PC7 */ 1551 #define PCL_7S 11 /* PC7 Shrink */ 1552 #define PCL__8 12 /* PC8 */ 1553 #define PCL__9 13 /* PC9 */ 1554 #define PCLUNL 14 /* Unlimited */ 1555 1556 int pkg_cstate_limit = PCLUKN; 1557 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 1558 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"}; 1559 1560 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1561 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1562 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1563 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7}; 1564 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1565 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1566 int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1567 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1568 1569 1570 static void 1571 calculate_tsc_tweak() 1572 { 1573 tsc_tweak = base_hz / tsc_hz; 1574 } 1575 1576 static void 1577 dump_nhm_platform_info(void) 1578 { 1579 unsigned long long msr; 1580 unsigned int ratio; 1581 1582 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 1583 1584 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 1585 1586 ratio = (msr >> 40) & 0xFF; 1587 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", 1588 ratio, bclk, ratio * bclk); 1589 1590 ratio = (msr >> 8) & 0xFF; 1591 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 1592 ratio, bclk, ratio * bclk); 1593 1594 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 1595 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 1596 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 1597 1598 return; 1599 } 1600 1601 static void 1602 dump_hsw_turbo_ratio_limits(void) 1603 { 1604 unsigned long long msr; 1605 unsigned int ratio; 1606 1607 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 1608 1609 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 1610 1611 ratio = (msr >> 8) & 0xFF; 1612 if (ratio) 1613 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", 1614 ratio, bclk, ratio * bclk); 1615 1616 ratio = (msr >> 0) & 0xFF; 1617 if (ratio) 1618 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", 1619 ratio, bclk, ratio * bclk); 1620 return; 1621 } 1622 1623 static void 1624 dump_ivt_turbo_ratio_limits(void) 1625 { 1626 unsigned long long msr; 1627 unsigned int ratio; 1628 1629 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 1630 1631 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 1632 1633 ratio = (msr >> 56) & 0xFF; 1634 if (ratio) 1635 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", 1636 ratio, bclk, ratio * bclk); 1637 1638 ratio = (msr >> 48) & 0xFF; 1639 if (ratio) 1640 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", 1641 ratio, bclk, ratio * bclk); 1642 1643 ratio = (msr >> 40) & 0xFF; 1644 if (ratio) 1645 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", 1646 ratio, bclk, ratio * bclk); 1647 1648 ratio = (msr >> 32) & 0xFF; 1649 if (ratio) 1650 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", 1651 ratio, bclk, ratio * bclk); 1652 1653 ratio = (msr >> 24) & 0xFF; 1654 if (ratio) 1655 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", 1656 ratio, bclk, ratio * bclk); 1657 1658 ratio = (msr >> 16) & 0xFF; 1659 if (ratio) 1660 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", 1661 ratio, bclk, ratio * bclk); 1662 1663 ratio = (msr >> 8) & 0xFF; 1664 if (ratio) 1665 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", 1666 ratio, bclk, ratio * bclk); 1667 1668 ratio = (msr >> 0) & 0xFF; 1669 if (ratio) 1670 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", 1671 ratio, bclk, ratio * bclk); 1672 return; 1673 } 1674 1675 static void 1676 dump_nhm_turbo_ratio_limits(void) 1677 { 1678 unsigned long long msr; 1679 unsigned int ratio; 1680 1681 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 1682 1683 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 1684 1685 ratio = (msr >> 56) & 0xFF; 1686 if (ratio) 1687 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 8 active cores\n", 1688 ratio, bclk, ratio * bclk); 1689 1690 ratio = (msr >> 48) & 0xFF; 1691 if (ratio) 1692 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 7 active cores\n", 1693 ratio, bclk, ratio * bclk); 1694 1695 ratio = (msr >> 40) & 0xFF; 1696 if (ratio) 1697 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 6 active cores\n", 1698 ratio, bclk, ratio * bclk); 1699 1700 ratio = (msr >> 32) & 0xFF; 1701 if (ratio) 1702 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 5 active cores\n", 1703 ratio, bclk, ratio * bclk); 1704 1705 ratio = (msr >> 24) & 0xFF; 1706 if (ratio) 1707 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", 1708 ratio, bclk, ratio * bclk); 1709 1710 ratio = (msr >> 16) & 0xFF; 1711 if (ratio) 1712 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", 1713 ratio, bclk, ratio * bclk); 1714 1715 ratio = (msr >> 8) & 0xFF; 1716 if (ratio) 1717 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", 1718 ratio, bclk, ratio * bclk); 1719 1720 ratio = (msr >> 0) & 0xFF; 1721 if (ratio) 1722 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active cores\n", 1723 ratio, bclk, ratio * bclk); 1724 return; 1725 } 1726 1727 static void 1728 dump_atom_turbo_ratio_limits(void) 1729 { 1730 unsigned long long msr; 1731 unsigned int ratio; 1732 1733 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 1734 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 1735 1736 ratio = (msr >> 0) & 0x3F; 1737 if (ratio) 1738 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", 1739 ratio, bclk, ratio * bclk); 1740 1741 ratio = (msr >> 8) & 0x3F; 1742 if (ratio) 1743 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", 1744 ratio, bclk, ratio * bclk); 1745 1746 ratio = (msr >> 16) & 0x3F; 1747 if (ratio) 1748 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 1749 ratio, bclk, ratio * bclk); 1750 1751 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 1752 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 1753 1754 ratio = (msr >> 24) & 0x3F; 1755 if (ratio) 1756 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", 1757 ratio, bclk, ratio * bclk); 1758 1759 ratio = (msr >> 16) & 0x3F; 1760 if (ratio) 1761 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", 1762 ratio, bclk, ratio * bclk); 1763 1764 ratio = (msr >> 8) & 0x3F; 1765 if (ratio) 1766 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", 1767 ratio, bclk, ratio * bclk); 1768 1769 ratio = (msr >> 0) & 0x3F; 1770 if (ratio) 1771 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", 1772 ratio, bclk, ratio * bclk); 1773 } 1774 1775 static void 1776 dump_knl_turbo_ratio_limits(void) 1777 { 1778 const unsigned int buckets_no = 7; 1779 1780 unsigned long long msr; 1781 int delta_cores, delta_ratio; 1782 int i, b_nr; 1783 unsigned int cores[buckets_no]; 1784 unsigned int ratio[buckets_no]; 1785 1786 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 1787 1788 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 1789 base_cpu, msr); 1790 1791 /** 1792 * Turbo encoding in KNL is as follows: 1793 * [0] -- Reserved 1794 * [7:1] -- Base value of number of active cores of bucket 1. 1795 * [15:8] -- Base value of freq ratio of bucket 1. 1796 * [20:16] -- +ve delta of number of active cores of bucket 2. 1797 * i.e. active cores of bucket 2 = 1798 * active cores of bucket 1 + delta 1799 * [23:21] -- Negative delta of freq ratio of bucket 2. 1800 * i.e. freq ratio of bucket 2 = 1801 * freq ratio of bucket 1 - delta 1802 * [28:24]-- +ve delta of number of active cores of bucket 3. 1803 * [31:29]-- -ve delta of freq ratio of bucket 3. 1804 * [36:32]-- +ve delta of number of active cores of bucket 4. 1805 * [39:37]-- -ve delta of freq ratio of bucket 4. 1806 * [44:40]-- +ve delta of number of active cores of bucket 5. 1807 * [47:45]-- -ve delta of freq ratio of bucket 5. 1808 * [52:48]-- +ve delta of number of active cores of bucket 6. 1809 * [55:53]-- -ve delta of freq ratio of bucket 6. 1810 * [60:56]-- +ve delta of number of active cores of bucket 7. 1811 * [63:61]-- -ve delta of freq ratio of bucket 7. 1812 */ 1813 1814 b_nr = 0; 1815 cores[b_nr] = (msr & 0xFF) >> 1; 1816 ratio[b_nr] = (msr >> 8) & 0xFF; 1817 1818 for (i = 16; i < 64; i += 8) { 1819 delta_cores = (msr >> i) & 0x1F; 1820 delta_ratio = (msr >> (i + 5)) & 0x7; 1821 1822 cores[b_nr + 1] = cores[b_nr] + delta_cores; 1823 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 1824 b_nr++; 1825 } 1826 1827 for (i = buckets_no - 1; i >= 0; i--) 1828 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 1829 fprintf(outf, 1830 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 1831 ratio[i], bclk, ratio[i] * bclk, cores[i]); 1832 } 1833 1834 static void 1835 dump_nhm_cst_cfg(void) 1836 { 1837 unsigned long long msr; 1838 1839 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 1840 1841 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 1842 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 1843 1844 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 1845 1846 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n", 1847 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 1848 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 1849 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 1850 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 1851 (msr & (1 << 15)) ? "" : "UN", 1852 (unsigned int)msr & 0xF, 1853 pkg_cstate_limit_strings[pkg_cstate_limit]); 1854 return; 1855 } 1856 1857 static void 1858 dump_config_tdp(void) 1859 { 1860 unsigned long long msr; 1861 1862 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 1863 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 1864 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 1865 1866 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 1867 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 1868 if (msr) { 1869 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 1870 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 1871 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 1872 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 1873 } 1874 fprintf(outf, ")\n"); 1875 1876 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 1877 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 1878 if (msr) { 1879 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 1880 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 1881 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 1882 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 1883 } 1884 fprintf(outf, ")\n"); 1885 1886 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 1887 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 1888 if ((msr) & 0x3) 1889 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 1890 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 1891 fprintf(outf, ")\n"); 1892 1893 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 1894 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 1895 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 1896 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 1897 fprintf(outf, ")\n"); 1898 } 1899 1900 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 1901 1902 void print_irtl(void) 1903 { 1904 unsigned long long msr; 1905 1906 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 1907 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 1908 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1909 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1910 1911 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 1912 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 1913 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1914 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1915 1916 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 1917 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 1918 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1919 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1920 1921 if (!do_irtl_hsw) 1922 return; 1923 1924 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 1925 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 1926 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1927 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1928 1929 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 1930 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 1931 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1932 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1933 1934 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 1935 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 1936 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1937 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1938 1939 } 1940 void free_fd_percpu(void) 1941 { 1942 int i; 1943 1944 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 1945 if (fd_percpu[i] != 0) 1946 close(fd_percpu[i]); 1947 } 1948 1949 free(fd_percpu); 1950 } 1951 1952 void free_all_buffers(void) 1953 { 1954 CPU_FREE(cpu_present_set); 1955 cpu_present_set = NULL; 1956 cpu_present_setsize = 0; 1957 1958 CPU_FREE(cpu_affinity_set); 1959 cpu_affinity_set = NULL; 1960 cpu_affinity_setsize = 0; 1961 1962 free(thread_even); 1963 free(core_even); 1964 free(package_even); 1965 1966 thread_even = NULL; 1967 core_even = NULL; 1968 package_even = NULL; 1969 1970 free(thread_odd); 1971 free(core_odd); 1972 free(package_odd); 1973 1974 thread_odd = NULL; 1975 core_odd = NULL; 1976 package_odd = NULL; 1977 1978 free(output_buffer); 1979 output_buffer = NULL; 1980 outp = NULL; 1981 1982 free_fd_percpu(); 1983 1984 free(irq_column_2_cpu); 1985 free(irqs_per_cpu); 1986 } 1987 1988 /* 1989 * Open a file, and exit on failure 1990 */ 1991 FILE *fopen_or_die(const char *path, const char *mode) 1992 { 1993 FILE *filep = fopen(path, mode); 1994 if (!filep) 1995 err(1, "%s: open failed", path); 1996 return filep; 1997 } 1998 1999 /* 2000 * Parse a file containing a single int. 2001 */ 2002 int parse_int_file(const char *fmt, ...) 2003 { 2004 va_list args; 2005 char path[PATH_MAX]; 2006 FILE *filep; 2007 int value; 2008 2009 va_start(args, fmt); 2010 vsnprintf(path, sizeof(path), fmt, args); 2011 va_end(args); 2012 filep = fopen_or_die(path, "r"); 2013 if (fscanf(filep, "%d", &value) != 1) 2014 err(1, "%s: failed to parse number from file", path); 2015 fclose(filep); 2016 return value; 2017 } 2018 2019 /* 2020 * get_cpu_position_in_core(cpu) 2021 * return the position of the CPU among its HT siblings in the core 2022 * return -1 if the sibling is not in list 2023 */ 2024 int get_cpu_position_in_core(int cpu) 2025 { 2026 char path[64]; 2027 FILE *filep; 2028 int this_cpu; 2029 char character; 2030 int i; 2031 2032 sprintf(path, 2033 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", 2034 cpu); 2035 filep = fopen(path, "r"); 2036 if (filep == NULL) { 2037 perror(path); 2038 exit(1); 2039 } 2040 2041 for (i = 0; i < topo.num_threads_per_core; i++) { 2042 fscanf(filep, "%d", &this_cpu); 2043 if (this_cpu == cpu) { 2044 fclose(filep); 2045 return i; 2046 } 2047 2048 /* Account for no separator after last thread*/ 2049 if (i != (topo.num_threads_per_core - 1)) 2050 fscanf(filep, "%c", &character); 2051 } 2052 2053 fclose(filep); 2054 return -1; 2055 } 2056 2057 /* 2058 * cpu_is_first_core_in_package(cpu) 2059 * return 1 if given CPU is 1st core in package 2060 */ 2061 int cpu_is_first_core_in_package(int cpu) 2062 { 2063 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2064 } 2065 2066 int get_physical_package_id(int cpu) 2067 { 2068 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2069 } 2070 2071 int get_core_id(int cpu) 2072 { 2073 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2074 } 2075 2076 int get_num_ht_siblings(int cpu) 2077 { 2078 char path[80]; 2079 FILE *filep; 2080 int sib1; 2081 int matches = 0; 2082 char character; 2083 char str[100]; 2084 char *ch; 2085 2086 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu); 2087 filep = fopen_or_die(path, "r"); 2088 2089 /* 2090 * file format: 2091 * A ',' separated or '-' separated set of numbers 2092 * (eg 1-2 or 1,3,4,5) 2093 */ 2094 fscanf(filep, "%d%c\n", &sib1, &character); 2095 fseek(filep, 0, SEEK_SET); 2096 fgets(str, 100, filep); 2097 ch = strchr(str, character); 2098 while (ch != NULL) { 2099 matches++; 2100 ch = strchr(ch+1, character); 2101 } 2102 2103 fclose(filep); 2104 return matches+1; 2105 } 2106 2107 /* 2108 * run func(thread, core, package) in topology order 2109 * skip non-present cpus 2110 */ 2111 2112 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 2113 struct pkg_data *, struct thread_data *, struct core_data *, 2114 struct pkg_data *), struct thread_data *thread_base, 2115 struct core_data *core_base, struct pkg_data *pkg_base, 2116 struct thread_data *thread_base2, struct core_data *core_base2, 2117 struct pkg_data *pkg_base2) 2118 { 2119 int retval, pkg_no, core_no, thread_no; 2120 2121 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2122 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { 2123 for (thread_no = 0; thread_no < 2124 topo.num_threads_per_core; ++thread_no) { 2125 struct thread_data *t, *t2; 2126 struct core_data *c, *c2; 2127 struct pkg_data *p, *p2; 2128 2129 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); 2130 2131 if (cpu_is_not_present(t->cpu_id)) 2132 continue; 2133 2134 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no); 2135 2136 c = GET_CORE(core_base, core_no, pkg_no); 2137 c2 = GET_CORE(core_base2, core_no, pkg_no); 2138 2139 p = GET_PKG(pkg_base, pkg_no); 2140 p2 = GET_PKG(pkg_base2, pkg_no); 2141 2142 retval = func(t, c, p, t2, c2, p2); 2143 if (retval) 2144 return retval; 2145 } 2146 } 2147 } 2148 return 0; 2149 } 2150 2151 /* 2152 * run func(cpu) on every cpu in /proc/stat 2153 * return max_cpu number 2154 */ 2155 int for_all_proc_cpus(int (func)(int)) 2156 { 2157 FILE *fp; 2158 int cpu_num; 2159 int retval; 2160 2161 fp = fopen_or_die(proc_stat, "r"); 2162 2163 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 2164 if (retval != 0) 2165 err(1, "%s: failed to parse format", proc_stat); 2166 2167 while (1) { 2168 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 2169 if (retval != 1) 2170 break; 2171 2172 retval = func(cpu_num); 2173 if (retval) { 2174 fclose(fp); 2175 return(retval); 2176 } 2177 } 2178 fclose(fp); 2179 return 0; 2180 } 2181 2182 void re_initialize(void) 2183 { 2184 free_all_buffers(); 2185 setup_all_buffers(); 2186 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2187 } 2188 2189 2190 /* 2191 * count_cpus() 2192 * remember the last one seen, it will be the max 2193 */ 2194 int count_cpus(int cpu) 2195 { 2196 if (topo.max_cpu_num < cpu) 2197 topo.max_cpu_num = cpu; 2198 2199 topo.num_cpus += 1; 2200 return 0; 2201 } 2202 int mark_cpu_present(int cpu) 2203 { 2204 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 2205 return 0; 2206 } 2207 2208 /* 2209 * snapshot_proc_interrupts() 2210 * 2211 * read and record summary of /proc/interrupts 2212 * 2213 * return 1 if config change requires a restart, else return 0 2214 */ 2215 int snapshot_proc_interrupts(void) 2216 { 2217 static FILE *fp; 2218 int column, retval; 2219 2220 if (fp == NULL) 2221 fp = fopen_or_die("/proc/interrupts", "r"); 2222 else 2223 rewind(fp); 2224 2225 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 2226 for (column = 0; column < topo.num_cpus; ++column) { 2227 int cpu_number; 2228 2229 retval = fscanf(fp, " CPU%d", &cpu_number); 2230 if (retval != 1) 2231 break; 2232 2233 if (cpu_number > topo.max_cpu_num) { 2234 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 2235 return 1; 2236 } 2237 2238 irq_column_2_cpu[column] = cpu_number; 2239 irqs_per_cpu[cpu_number] = 0; 2240 } 2241 2242 /* read /proc/interrupt count lines and sum up irqs per cpu */ 2243 while (1) { 2244 int column; 2245 char buf[64]; 2246 2247 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 2248 if (retval != 1) 2249 break; 2250 2251 /* read the count per cpu */ 2252 for (column = 0; column < topo.num_cpus; ++column) { 2253 2254 int cpu_number, irq_count; 2255 2256 retval = fscanf(fp, " %d", &irq_count); 2257 if (retval != 1) 2258 break; 2259 2260 cpu_number = irq_column_2_cpu[column]; 2261 irqs_per_cpu[cpu_number] += irq_count; 2262 2263 } 2264 2265 while (getc(fp) != '\n') 2266 ; /* flush interrupt description */ 2267 2268 } 2269 return 0; 2270 } 2271 /* 2272 * snapshot_gfx_rc6_ms() 2273 * 2274 * record snapshot of 2275 * /sys/class/drm/card0/power/rc6_residency_ms 2276 * 2277 * return 1 if config change requires a restart, else return 0 2278 */ 2279 int snapshot_gfx_rc6_ms(void) 2280 { 2281 FILE *fp; 2282 int retval; 2283 2284 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 2285 2286 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 2287 if (retval != 1) 2288 err(1, "GFX rc6"); 2289 2290 fclose(fp); 2291 2292 return 0; 2293 } 2294 /* 2295 * snapshot_gfx_mhz() 2296 * 2297 * record snapshot of 2298 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 2299 * 2300 * return 1 if config change requires a restart, else return 0 2301 */ 2302 int snapshot_gfx_mhz(void) 2303 { 2304 static FILE *fp; 2305 int retval; 2306 2307 if (fp == NULL) 2308 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 2309 else 2310 rewind(fp); 2311 2312 retval = fscanf(fp, "%d", &gfx_cur_mhz); 2313 if (retval != 1) 2314 err(1, "GFX MHz"); 2315 2316 return 0; 2317 } 2318 2319 /* 2320 * snapshot /proc and /sys files 2321 * 2322 * return 1 if configuration restart needed, else return 0 2323 */ 2324 int snapshot_proc_sysfs_files(void) 2325 { 2326 if (snapshot_proc_interrupts()) 2327 return 1; 2328 2329 if (DO_BIC(BIC_GFX_rc6)) 2330 snapshot_gfx_rc6_ms(); 2331 2332 if (DO_BIC(BIC_GFXMHz)) 2333 snapshot_gfx_mhz(); 2334 2335 return 0; 2336 } 2337 2338 void turbostat_loop() 2339 { 2340 int retval; 2341 int restarted = 0; 2342 2343 restart: 2344 restarted++; 2345 2346 snapshot_proc_sysfs_files(); 2347 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2348 if (retval < -1) { 2349 exit(retval); 2350 } else if (retval == -1) { 2351 if (restarted > 1) { 2352 exit(retval); 2353 } 2354 re_initialize(); 2355 goto restart; 2356 } 2357 restarted = 0; 2358 gettimeofday(&tv_even, (struct timezone *)NULL); 2359 2360 while (1) { 2361 if (for_all_proc_cpus(cpu_is_not_present)) { 2362 re_initialize(); 2363 goto restart; 2364 } 2365 nanosleep(&interval_ts, NULL); 2366 if (snapshot_proc_sysfs_files()) 2367 goto restart; 2368 retval = for_all_cpus(get_counters, ODD_COUNTERS); 2369 if (retval < -1) { 2370 exit(retval); 2371 } else if (retval == -1) { 2372 re_initialize(); 2373 goto restart; 2374 } 2375 gettimeofday(&tv_odd, (struct timezone *)NULL); 2376 timersub(&tv_odd, &tv_even, &tv_delta); 2377 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 2378 re_initialize(); 2379 goto restart; 2380 } 2381 compute_average(EVEN_COUNTERS); 2382 format_all_counters(EVEN_COUNTERS); 2383 flush_output_stdout(); 2384 nanosleep(&interval_ts, NULL); 2385 if (snapshot_proc_sysfs_files()) 2386 goto restart; 2387 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2388 if (retval < -1) { 2389 exit(retval); 2390 } else if (retval == -1) { 2391 re_initialize(); 2392 goto restart; 2393 } 2394 gettimeofday(&tv_even, (struct timezone *)NULL); 2395 timersub(&tv_even, &tv_odd, &tv_delta); 2396 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 2397 re_initialize(); 2398 goto restart; 2399 } 2400 compute_average(ODD_COUNTERS); 2401 format_all_counters(ODD_COUNTERS); 2402 flush_output_stdout(); 2403 } 2404 } 2405 2406 void check_dev_msr() 2407 { 2408 struct stat sb; 2409 char pathname[32]; 2410 2411 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 2412 if (stat(pathname, &sb)) 2413 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 2414 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 2415 } 2416 2417 void check_permissions() 2418 { 2419 struct __user_cap_header_struct cap_header_data; 2420 cap_user_header_t cap_header = &cap_header_data; 2421 struct __user_cap_data_struct cap_data_data; 2422 cap_user_data_t cap_data = &cap_data_data; 2423 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); 2424 int do_exit = 0; 2425 char pathname[32]; 2426 2427 /* check for CAP_SYS_RAWIO */ 2428 cap_header->pid = getpid(); 2429 cap_header->version = _LINUX_CAPABILITY_VERSION; 2430 if (capget(cap_header, cap_data) < 0) 2431 err(-6, "capget(2) failed"); 2432 2433 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { 2434 do_exit++; 2435 warnx("capget(CAP_SYS_RAWIO) failed," 2436 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 2437 } 2438 2439 /* test file permissions */ 2440 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 2441 if (euidaccess(pathname, R_OK)) { 2442 do_exit++; 2443 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 2444 } 2445 2446 /* if all else fails, thell them to be root */ 2447 if (do_exit) 2448 if (getuid() != 0) 2449 warnx("... or simply run as root"); 2450 2451 if (do_exit) 2452 exit(-6); 2453 } 2454 2455 /* 2456 * NHM adds support for additional MSRs: 2457 * 2458 * MSR_SMI_COUNT 0x00000034 2459 * 2460 * MSR_PLATFORM_INFO 0x000000ce 2461 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 2462 * 2463 * MSR_MISC_PWR_MGMT 0x000001aa 2464 * 2465 * MSR_PKG_C3_RESIDENCY 0x000003f8 2466 * MSR_PKG_C6_RESIDENCY 0x000003f9 2467 * MSR_CORE_C3_RESIDENCY 0x000003fc 2468 * MSR_CORE_C6_RESIDENCY 0x000003fd 2469 * 2470 * Side effect: 2471 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 2472 * sets has_misc_feature_control 2473 */ 2474 int probe_nhm_msrs(unsigned int family, unsigned int model) 2475 { 2476 unsigned long long msr; 2477 unsigned int base_ratio; 2478 int *pkg_cstate_limits; 2479 2480 if (!genuine_intel) 2481 return 0; 2482 2483 if (family != 6) 2484 return 0; 2485 2486 bclk = discover_bclk(family, model); 2487 2488 switch (model) { 2489 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 2490 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 2491 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 2492 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 2493 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 2494 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 2495 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 2496 pkg_cstate_limits = nhm_pkg_cstate_limits; 2497 break; 2498 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 2499 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 2500 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 2501 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 2502 pkg_cstate_limits = snb_pkg_cstate_limits; 2503 has_misc_feature_control = 1; 2504 break; 2505 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 2506 case INTEL_FAM6_HASWELL_X: /* HSX */ 2507 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 2508 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 2509 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 2510 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 2511 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2512 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2513 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 2514 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 2515 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 2516 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 2517 pkg_cstate_limits = hsw_pkg_cstate_limits; 2518 has_misc_feature_control = 1; 2519 break; 2520 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 2521 pkg_cstate_limits = skx_pkg_cstate_limits; 2522 has_misc_feature_control = 1; 2523 break; 2524 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 2525 no_MSR_MISC_PWR_MGMT = 1; 2526 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 2527 pkg_cstate_limits = slv_pkg_cstate_limits; 2528 break; 2529 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 2530 pkg_cstate_limits = amt_pkg_cstate_limits; 2531 no_MSR_MISC_PWR_MGMT = 1; 2532 break; 2533 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 2534 case INTEL_FAM6_XEON_PHI_KNM: 2535 pkg_cstate_limits = phi_pkg_cstate_limits; 2536 break; 2537 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 2538 case INTEL_FAM6_ATOM_GEMINI_LAKE: 2539 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 2540 pkg_cstate_limits = bxt_pkg_cstate_limits; 2541 break; 2542 default: 2543 return 0; 2544 } 2545 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2546 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 2547 2548 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2549 base_ratio = (msr >> 8) & 0xFF; 2550 2551 base_hz = base_ratio * bclk * 1000000; 2552 has_base_hz = 1; 2553 return 1; 2554 } 2555 /* 2556 * SLV client has supporet for unique MSRs: 2557 * 2558 * MSR_CC6_DEMOTION_POLICY_CONFIG 2559 * MSR_MC6_DEMOTION_POLICY_CONFIG 2560 */ 2561 2562 int has_slv_msrs(unsigned int family, unsigned int model) 2563 { 2564 if (!genuine_intel) 2565 return 0; 2566 2567 switch (model) { 2568 case INTEL_FAM6_ATOM_SILVERMONT1: 2569 case INTEL_FAM6_ATOM_MERRIFIELD: 2570 case INTEL_FAM6_ATOM_MOOREFIELD: 2571 return 1; 2572 } 2573 return 0; 2574 } 2575 2576 int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model) 2577 { 2578 if (has_slv_msrs(family, model)) 2579 return 0; 2580 2581 switch (model) { 2582 /* Nehalem compatible, but do not include turbo-ratio limit support */ 2583 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 2584 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 2585 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 2586 case INTEL_FAM6_XEON_PHI_KNM: 2587 return 0; 2588 default: 2589 return 1; 2590 } 2591 } 2592 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 2593 { 2594 if (has_slv_msrs(family, model)) 2595 return 1; 2596 2597 return 0; 2598 } 2599 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 2600 { 2601 if (!genuine_intel) 2602 return 0; 2603 2604 if (family != 6) 2605 return 0; 2606 2607 switch (model) { 2608 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 2609 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 2610 return 1; 2611 default: 2612 return 0; 2613 } 2614 } 2615 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 2616 { 2617 if (!genuine_intel) 2618 return 0; 2619 2620 if (family != 6) 2621 return 0; 2622 2623 switch (model) { 2624 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 2625 return 1; 2626 default: 2627 return 0; 2628 } 2629 } 2630 2631 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 2632 { 2633 if (!genuine_intel) 2634 return 0; 2635 2636 if (family != 6) 2637 return 0; 2638 2639 switch (model) { 2640 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 2641 case INTEL_FAM6_XEON_PHI_KNM: 2642 return 1; 2643 default: 2644 return 0; 2645 } 2646 } 2647 int has_config_tdp(unsigned int family, unsigned int model) 2648 { 2649 if (!genuine_intel) 2650 return 0; 2651 2652 if (family != 6) 2653 return 0; 2654 2655 switch (model) { 2656 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 2657 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 2658 case INTEL_FAM6_HASWELL_X: /* HSX */ 2659 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 2660 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 2661 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 2662 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 2663 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2664 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2665 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 2666 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 2667 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 2668 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 2669 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 2670 2671 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 2672 case INTEL_FAM6_XEON_PHI_KNM: 2673 return 1; 2674 default: 2675 return 0; 2676 } 2677 } 2678 2679 static void 2680 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 2681 { 2682 if (!do_nhm_platform_info) 2683 return; 2684 2685 dump_nhm_platform_info(); 2686 2687 if (has_hsw_turbo_ratio_limit(family, model)) 2688 dump_hsw_turbo_ratio_limits(); 2689 2690 if (has_ivt_turbo_ratio_limit(family, model)) 2691 dump_ivt_turbo_ratio_limits(); 2692 2693 if (has_nhm_turbo_ratio_limit(family, model)) 2694 dump_nhm_turbo_ratio_limits(); 2695 2696 if (has_atom_turbo_ratio_limit(family, model)) 2697 dump_atom_turbo_ratio_limits(); 2698 2699 if (has_knl_turbo_ratio_limit(family, model)) 2700 dump_knl_turbo_ratio_limits(); 2701 2702 if (has_config_tdp(family, model)) 2703 dump_config_tdp(); 2704 2705 dump_nhm_cst_cfg(); 2706 } 2707 2708 2709 /* 2710 * print_epb() 2711 * Decode the ENERGY_PERF_BIAS MSR 2712 */ 2713 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2714 { 2715 unsigned long long msr; 2716 char *epb_string; 2717 int cpu; 2718 2719 if (!has_epb) 2720 return 0; 2721 2722 cpu = t->cpu_id; 2723 2724 /* EPB is per-package */ 2725 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2726 return 0; 2727 2728 if (cpu_migrate(cpu)) { 2729 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2730 return -1; 2731 } 2732 2733 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) 2734 return 0; 2735 2736 switch (msr & 0xF) { 2737 case ENERGY_PERF_BIAS_PERFORMANCE: 2738 epb_string = "performance"; 2739 break; 2740 case ENERGY_PERF_BIAS_NORMAL: 2741 epb_string = "balanced"; 2742 break; 2743 case ENERGY_PERF_BIAS_POWERSAVE: 2744 epb_string = "powersave"; 2745 break; 2746 default: 2747 epb_string = "custom"; 2748 break; 2749 } 2750 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); 2751 2752 return 0; 2753 } 2754 /* 2755 * print_hwp() 2756 * Decode the MSR_HWP_CAPABILITIES 2757 */ 2758 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2759 { 2760 unsigned long long msr; 2761 int cpu; 2762 2763 if (!has_hwp) 2764 return 0; 2765 2766 cpu = t->cpu_id; 2767 2768 /* MSR_HWP_CAPABILITIES is per-package */ 2769 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2770 return 0; 2771 2772 if (cpu_migrate(cpu)) { 2773 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2774 return -1; 2775 } 2776 2777 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 2778 return 0; 2779 2780 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 2781 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 2782 2783 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 2784 if ((msr & (1 << 0)) == 0) 2785 return 0; 2786 2787 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 2788 return 0; 2789 2790 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 2791 "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n", 2792 cpu, msr, 2793 (unsigned int)HWP_HIGHEST_PERF(msr), 2794 (unsigned int)HWP_GUARANTEED_PERF(msr), 2795 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 2796 (unsigned int)HWP_LOWEST_PERF(msr)); 2797 2798 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 2799 return 0; 2800 2801 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 2802 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n", 2803 cpu, msr, 2804 (unsigned int)(((msr) >> 0) & 0xff), 2805 (unsigned int)(((msr) >> 8) & 0xff), 2806 (unsigned int)(((msr) >> 16) & 0xff), 2807 (unsigned int)(((msr) >> 24) & 0xff), 2808 (unsigned int)(((msr) >> 32) & 0xff3), 2809 (unsigned int)(((msr) >> 42) & 0x1)); 2810 2811 if (has_hwp_pkg) { 2812 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 2813 return 0; 2814 2815 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 2816 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n", 2817 cpu, msr, 2818 (unsigned int)(((msr) >> 0) & 0xff), 2819 (unsigned int)(((msr) >> 8) & 0xff), 2820 (unsigned int)(((msr) >> 16) & 0xff), 2821 (unsigned int)(((msr) >> 24) & 0xff), 2822 (unsigned int)(((msr) >> 32) & 0xff3)); 2823 } 2824 if (has_hwp_notify) { 2825 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 2826 return 0; 2827 2828 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 2829 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 2830 cpu, msr, 2831 ((msr) & 0x1) ? "EN" : "Dis", 2832 ((msr) & 0x2) ? "EN" : "Dis"); 2833 } 2834 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 2835 return 0; 2836 2837 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 2838 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 2839 cpu, msr, 2840 ((msr) & 0x1) ? "" : "No-", 2841 ((msr) & 0x2) ? "" : "No-"); 2842 2843 return 0; 2844 } 2845 2846 /* 2847 * print_perf_limit() 2848 */ 2849 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2850 { 2851 unsigned long long msr; 2852 int cpu; 2853 2854 cpu = t->cpu_id; 2855 2856 /* per-package */ 2857 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2858 return 0; 2859 2860 if (cpu_migrate(cpu)) { 2861 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2862 return -1; 2863 } 2864 2865 if (do_core_perf_limit_reasons) { 2866 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 2867 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2868 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 2869 (msr & 1 << 15) ? "bit15, " : "", 2870 (msr & 1 << 14) ? "bit14, " : "", 2871 (msr & 1 << 13) ? "Transitions, " : "", 2872 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 2873 (msr & 1 << 11) ? "PkgPwrL2, " : "", 2874 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2875 (msr & 1 << 9) ? "CorePwr, " : "", 2876 (msr & 1 << 8) ? "Amps, " : "", 2877 (msr & 1 << 6) ? "VR-Therm, " : "", 2878 (msr & 1 << 5) ? "Auto-HWP, " : "", 2879 (msr & 1 << 4) ? "Graphics, " : "", 2880 (msr & 1 << 2) ? "bit2, " : "", 2881 (msr & 1 << 1) ? "ThermStatus, " : "", 2882 (msr & 1 << 0) ? "PROCHOT, " : ""); 2883 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 2884 (msr & 1 << 31) ? "bit31, " : "", 2885 (msr & 1 << 30) ? "bit30, " : "", 2886 (msr & 1 << 29) ? "Transitions, " : "", 2887 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 2888 (msr & 1 << 27) ? "PkgPwrL2, " : "", 2889 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2890 (msr & 1 << 25) ? "CorePwr, " : "", 2891 (msr & 1 << 24) ? "Amps, " : "", 2892 (msr & 1 << 22) ? "VR-Therm, " : "", 2893 (msr & 1 << 21) ? "Auto-HWP, " : "", 2894 (msr & 1 << 20) ? "Graphics, " : "", 2895 (msr & 1 << 18) ? "bit18, " : "", 2896 (msr & 1 << 17) ? "ThermStatus, " : "", 2897 (msr & 1 << 16) ? "PROCHOT, " : ""); 2898 2899 } 2900 if (do_gfx_perf_limit_reasons) { 2901 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 2902 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2903 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 2904 (msr & 1 << 0) ? "PROCHOT, " : "", 2905 (msr & 1 << 1) ? "ThermStatus, " : "", 2906 (msr & 1 << 4) ? "Graphics, " : "", 2907 (msr & 1 << 6) ? "VR-Therm, " : "", 2908 (msr & 1 << 8) ? "Amps, " : "", 2909 (msr & 1 << 9) ? "GFXPwr, " : "", 2910 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2911 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 2912 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 2913 (msr & 1 << 16) ? "PROCHOT, " : "", 2914 (msr & 1 << 17) ? "ThermStatus, " : "", 2915 (msr & 1 << 20) ? "Graphics, " : "", 2916 (msr & 1 << 22) ? "VR-Therm, " : "", 2917 (msr & 1 << 24) ? "Amps, " : "", 2918 (msr & 1 << 25) ? "GFXPwr, " : "", 2919 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2920 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 2921 } 2922 if (do_ring_perf_limit_reasons) { 2923 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 2924 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2925 fprintf(outf, " (Active: %s%s%s%s%s%s)", 2926 (msr & 1 << 0) ? "PROCHOT, " : "", 2927 (msr & 1 << 1) ? "ThermStatus, " : "", 2928 (msr & 1 << 6) ? "VR-Therm, " : "", 2929 (msr & 1 << 8) ? "Amps, " : "", 2930 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2931 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 2932 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 2933 (msr & 1 << 16) ? "PROCHOT, " : "", 2934 (msr & 1 << 17) ? "ThermStatus, " : "", 2935 (msr & 1 << 22) ? "VR-Therm, " : "", 2936 (msr & 1 << 24) ? "Amps, " : "", 2937 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2938 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 2939 } 2940 return 0; 2941 } 2942 2943 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 2944 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 2945 2946 double get_tdp(unsigned int model) 2947 { 2948 unsigned long long msr; 2949 2950 if (do_rapl & RAPL_PKG_POWER_INFO) 2951 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 2952 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 2953 2954 switch (model) { 2955 case INTEL_FAM6_ATOM_SILVERMONT1: 2956 case INTEL_FAM6_ATOM_SILVERMONT2: 2957 return 30.0; 2958 default: 2959 return 135.0; 2960 } 2961 } 2962 2963 /* 2964 * rapl_dram_energy_units_probe() 2965 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 2966 */ 2967 static double 2968 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 2969 { 2970 /* only called for genuine_intel, family 6 */ 2971 2972 switch (model) { 2973 case INTEL_FAM6_HASWELL_X: /* HSX */ 2974 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2975 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2976 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 2977 case INTEL_FAM6_XEON_PHI_KNM: 2978 return (rapl_dram_energy_units = 15.3 / 1000000); 2979 default: 2980 return (rapl_energy_units); 2981 } 2982 } 2983 2984 2985 /* 2986 * rapl_probe() 2987 * 2988 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 2989 */ 2990 void rapl_probe(unsigned int family, unsigned int model) 2991 { 2992 unsigned long long msr; 2993 unsigned int time_unit; 2994 double tdp; 2995 2996 if (!genuine_intel) 2997 return; 2998 2999 if (family != 6) 3000 return; 3001 3002 switch (model) { 3003 case INTEL_FAM6_SANDYBRIDGE: 3004 case INTEL_FAM6_IVYBRIDGE: 3005 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3006 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3007 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3008 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3009 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3010 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 3011 if (rapl_joules) { 3012 BIC_PRESENT(BIC_Pkg_J); 3013 BIC_PRESENT(BIC_Cor_J); 3014 BIC_PRESENT(BIC_GFX_J); 3015 } else { 3016 BIC_PRESENT(BIC_PkgWatt); 3017 BIC_PRESENT(BIC_CorWatt); 3018 BIC_PRESENT(BIC_GFXWatt); 3019 } 3020 break; 3021 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3022 case INTEL_FAM6_ATOM_GEMINI_LAKE: 3023 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 3024 if (rapl_joules) 3025 BIC_PRESENT(BIC_Pkg_J); 3026 else 3027 BIC_PRESENT(BIC_PkgWatt); 3028 break; 3029 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3030 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3031 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3032 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3033 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 3034 BIC_PRESENT(BIC_PKG__); 3035 BIC_PRESENT(BIC_RAM__); 3036 if (rapl_joules) { 3037 BIC_PRESENT(BIC_Pkg_J); 3038 BIC_PRESENT(BIC_Cor_J); 3039 BIC_PRESENT(BIC_RAM_J); 3040 } else { 3041 BIC_PRESENT(BIC_PkgWatt); 3042 BIC_PRESENT(BIC_CorWatt); 3043 BIC_PRESENT(BIC_RAMWatt); 3044 } 3045 break; 3046 case INTEL_FAM6_HASWELL_X: /* HSX */ 3047 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3048 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3049 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3050 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3051 case INTEL_FAM6_XEON_PHI_KNM: 3052 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 3053 BIC_PRESENT(BIC_PKG__); 3054 BIC_PRESENT(BIC_RAM__); 3055 if (rapl_joules) { 3056 BIC_PRESENT(BIC_Pkg_J); 3057 BIC_PRESENT(BIC_RAM_J); 3058 } else { 3059 BIC_PRESENT(BIC_PkgWatt); 3060 BIC_PRESENT(BIC_RAMWatt); 3061 } 3062 break; 3063 case INTEL_FAM6_SANDYBRIDGE_X: 3064 case INTEL_FAM6_IVYBRIDGE_X: 3065 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 3066 BIC_PRESENT(BIC_PKG__); 3067 BIC_PRESENT(BIC_RAM__); 3068 if (rapl_joules) { 3069 BIC_PRESENT(BIC_Pkg_J); 3070 BIC_PRESENT(BIC_Cor_J); 3071 BIC_PRESENT(BIC_RAM_J); 3072 } else { 3073 BIC_PRESENT(BIC_PkgWatt); 3074 BIC_PRESENT(BIC_CorWatt); 3075 BIC_PRESENT(BIC_RAMWatt); 3076 } 3077 break; 3078 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 3079 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 3080 do_rapl = RAPL_PKG | RAPL_CORES; 3081 if (rapl_joules) { 3082 BIC_PRESENT(BIC_Pkg_J); 3083 BIC_PRESENT(BIC_Cor_J); 3084 } else { 3085 BIC_PRESENT(BIC_PkgWatt); 3086 BIC_PRESENT(BIC_CorWatt); 3087 } 3088 break; 3089 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3090 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 3091 BIC_PRESENT(BIC_PKG__); 3092 BIC_PRESENT(BIC_RAM__); 3093 if (rapl_joules) { 3094 BIC_PRESENT(BIC_Pkg_J); 3095 BIC_PRESENT(BIC_Cor_J); 3096 BIC_PRESENT(BIC_RAM_J); 3097 } else { 3098 BIC_PRESENT(BIC_PkgWatt); 3099 BIC_PRESENT(BIC_CorWatt); 3100 BIC_PRESENT(BIC_RAMWatt); 3101 } 3102 break; 3103 default: 3104 return; 3105 } 3106 3107 /* units on package 0, verify later other packages match */ 3108 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 3109 return; 3110 3111 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 3112 if (model == INTEL_FAM6_ATOM_SILVERMONT1) 3113 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 3114 else 3115 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 3116 3117 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 3118 3119 time_unit = msr >> 16 & 0xF; 3120 if (time_unit == 0) 3121 time_unit = 0xA; 3122 3123 rapl_time_units = 1.0 / (1 << (time_unit)); 3124 3125 tdp = get_tdp(model); 3126 3127 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 3128 if (!quiet) 3129 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 3130 3131 return; 3132 } 3133 3134 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 3135 { 3136 if (!genuine_intel) 3137 return; 3138 3139 if (family != 6) 3140 return; 3141 3142 switch (model) { 3143 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3144 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3145 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3146 do_gfx_perf_limit_reasons = 1; 3147 case INTEL_FAM6_HASWELL_X: /* HSX */ 3148 do_core_perf_limit_reasons = 1; 3149 do_ring_perf_limit_reasons = 1; 3150 default: 3151 return; 3152 } 3153 } 3154 3155 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3156 { 3157 unsigned long long msr; 3158 unsigned int dts; 3159 int cpu; 3160 3161 if (!(do_dts || do_ptm)) 3162 return 0; 3163 3164 cpu = t->cpu_id; 3165 3166 /* DTS is per-core, no need to print for each thread */ 3167 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 3168 return 0; 3169 3170 if (cpu_migrate(cpu)) { 3171 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3172 return -1; 3173 } 3174 3175 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 3176 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 3177 return 0; 3178 3179 dts = (msr >> 16) & 0x7F; 3180 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 3181 cpu, msr, tcc_activation_temp - dts); 3182 3183 #ifdef THERM_DEBUG 3184 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 3185 return 0; 3186 3187 dts = (msr >> 16) & 0x7F; 3188 dts2 = (msr >> 8) & 0x7F; 3189 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 3190 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 3191 #endif 3192 } 3193 3194 3195 if (do_dts) { 3196 unsigned int resolution; 3197 3198 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 3199 return 0; 3200 3201 dts = (msr >> 16) & 0x7F; 3202 resolution = (msr >> 27) & 0xF; 3203 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 3204 cpu, msr, tcc_activation_temp - dts, resolution); 3205 3206 #ifdef THERM_DEBUG 3207 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 3208 return 0; 3209 3210 dts = (msr >> 16) & 0x7F; 3211 dts2 = (msr >> 8) & 0x7F; 3212 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 3213 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 3214 #endif 3215 } 3216 3217 return 0; 3218 } 3219 3220 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 3221 { 3222 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 3223 cpu, label, 3224 ((msr >> 15) & 1) ? "EN" : "DIS", 3225 ((msr >> 0) & 0x7FFF) * rapl_power_units, 3226 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 3227 (((msr >> 16) & 1) ? "EN" : "DIS")); 3228 3229 return; 3230 } 3231 3232 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3233 { 3234 unsigned long long msr; 3235 int cpu; 3236 3237 if (!do_rapl) 3238 return 0; 3239 3240 /* RAPL counters are per package, so print only for 1st thread/package */ 3241 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3242 return 0; 3243 3244 cpu = t->cpu_id; 3245 if (cpu_migrate(cpu)) { 3246 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3247 return -1; 3248 } 3249 3250 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 3251 return -1; 3252 3253 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr, 3254 rapl_power_units, rapl_energy_units, rapl_time_units); 3255 3256 if (do_rapl & RAPL_PKG_POWER_INFO) { 3257 3258 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 3259 return -5; 3260 3261 3262 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 3263 cpu, msr, 3264 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3265 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3266 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3267 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 3268 3269 } 3270 if (do_rapl & RAPL_PKG) { 3271 3272 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 3273 return -9; 3274 3275 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 3276 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 3277 3278 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 3279 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 3280 cpu, 3281 ((msr >> 47) & 1) ? "EN" : "DIS", 3282 ((msr >> 32) & 0x7FFF) * rapl_power_units, 3283 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 3284 ((msr >> 48) & 1) ? "EN" : "DIS"); 3285 } 3286 3287 if (do_rapl & RAPL_DRAM_POWER_INFO) { 3288 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 3289 return -6; 3290 3291 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 3292 cpu, msr, 3293 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3294 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3295 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3296 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 3297 } 3298 if (do_rapl & RAPL_DRAM) { 3299 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 3300 return -9; 3301 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 3302 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 3303 3304 print_power_limit_msr(cpu, msr, "DRAM Limit"); 3305 } 3306 if (do_rapl & RAPL_CORE_POLICY) { 3307 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 3308 return -7; 3309 3310 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 3311 } 3312 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 3313 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 3314 return -9; 3315 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 3316 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 3317 print_power_limit_msr(cpu, msr, "Cores Limit"); 3318 } 3319 if (do_rapl & RAPL_GFX) { 3320 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 3321 return -8; 3322 3323 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 3324 3325 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 3326 return -9; 3327 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 3328 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 3329 print_power_limit_msr(cpu, msr, "GFX Limit"); 3330 } 3331 return 0; 3332 } 3333 3334 /* 3335 * SNB adds support for additional MSRs: 3336 * 3337 * MSR_PKG_C7_RESIDENCY 0x000003fa 3338 * MSR_CORE_C7_RESIDENCY 0x000003fe 3339 * MSR_PKG_C2_RESIDENCY 0x0000060d 3340 */ 3341 3342 int has_snb_msrs(unsigned int family, unsigned int model) 3343 { 3344 if (!genuine_intel) 3345 return 0; 3346 3347 switch (model) { 3348 case INTEL_FAM6_SANDYBRIDGE: 3349 case INTEL_FAM6_SANDYBRIDGE_X: 3350 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3351 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3352 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3353 case INTEL_FAM6_HASWELL_X: /* HSW */ 3354 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3355 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3356 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3357 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3358 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3359 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3360 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3361 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3362 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3363 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3364 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3365 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3366 case INTEL_FAM6_ATOM_GEMINI_LAKE: 3367 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3368 return 1; 3369 } 3370 return 0; 3371 } 3372 3373 /* 3374 * HSW adds support for additional MSRs: 3375 * 3376 * MSR_PKG_C8_RESIDENCY 0x00000630 3377 * MSR_PKG_C9_RESIDENCY 0x00000631 3378 * MSR_PKG_C10_RESIDENCY 0x00000632 3379 * 3380 * MSR_PKGC8_IRTL 0x00000633 3381 * MSR_PKGC9_IRTL 0x00000634 3382 * MSR_PKGC10_IRTL 0x00000635 3383 * 3384 */ 3385 int has_hsw_msrs(unsigned int family, unsigned int model) 3386 { 3387 if (!genuine_intel) 3388 return 0; 3389 3390 switch (model) { 3391 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3392 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3393 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3394 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3395 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3396 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3397 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3398 case INTEL_FAM6_ATOM_GEMINI_LAKE: 3399 return 1; 3400 } 3401 return 0; 3402 } 3403 3404 /* 3405 * SKL adds support for additional MSRS: 3406 * 3407 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 3408 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 3409 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 3410 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 3411 */ 3412 int has_skl_msrs(unsigned int family, unsigned int model) 3413 { 3414 if (!genuine_intel) 3415 return 0; 3416 3417 switch (model) { 3418 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3419 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3420 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3421 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3422 return 1; 3423 } 3424 return 0; 3425 } 3426 3427 int is_slm(unsigned int family, unsigned int model) 3428 { 3429 if (!genuine_intel) 3430 return 0; 3431 switch (model) { 3432 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 3433 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 3434 return 1; 3435 } 3436 return 0; 3437 } 3438 3439 int is_knl(unsigned int family, unsigned int model) 3440 { 3441 if (!genuine_intel) 3442 return 0; 3443 switch (model) { 3444 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3445 case INTEL_FAM6_XEON_PHI_KNM: 3446 return 1; 3447 } 3448 return 0; 3449 } 3450 3451 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 3452 { 3453 if (is_knl(family, model)) 3454 return 1024; 3455 return 1; 3456 } 3457 3458 #define SLM_BCLK_FREQS 5 3459 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 3460 3461 double slm_bclk(void) 3462 { 3463 unsigned long long msr = 3; 3464 unsigned int i; 3465 double freq; 3466 3467 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 3468 fprintf(outf, "SLM BCLK: unknown\n"); 3469 3470 i = msr & 0xf; 3471 if (i >= SLM_BCLK_FREQS) { 3472 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 3473 i = 3; 3474 } 3475 freq = slm_freq_table[i]; 3476 3477 if (!quiet) 3478 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 3479 3480 return freq; 3481 } 3482 3483 double discover_bclk(unsigned int family, unsigned int model) 3484 { 3485 if (has_snb_msrs(family, model) || is_knl(family, model)) 3486 return 100.00; 3487 else if (is_slm(family, model)) 3488 return slm_bclk(); 3489 else 3490 return 133.33; 3491 } 3492 3493 /* 3494 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 3495 * the Thermal Control Circuit (TCC) activates. 3496 * This is usually equal to tjMax. 3497 * 3498 * Older processors do not have this MSR, so there we guess, 3499 * but also allow cmdline over-ride with -T. 3500 * 3501 * Several MSR temperature values are in units of degrees-C 3502 * below this value, including the Digital Thermal Sensor (DTS), 3503 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 3504 */ 3505 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3506 { 3507 unsigned long long msr; 3508 unsigned int target_c_local; 3509 int cpu; 3510 3511 /* tcc_activation_temp is used only for dts or ptm */ 3512 if (!(do_dts || do_ptm)) 3513 return 0; 3514 3515 /* this is a per-package concept */ 3516 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3517 return 0; 3518 3519 cpu = t->cpu_id; 3520 if (cpu_migrate(cpu)) { 3521 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3522 return -1; 3523 } 3524 3525 if (tcc_activation_temp_override != 0) { 3526 tcc_activation_temp = tcc_activation_temp_override; 3527 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 3528 cpu, tcc_activation_temp); 3529 return 0; 3530 } 3531 3532 /* Temperature Target MSR is Nehalem and newer only */ 3533 if (!do_nhm_platform_info) 3534 goto guess; 3535 3536 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 3537 goto guess; 3538 3539 target_c_local = (msr >> 16) & 0xFF; 3540 3541 if (!quiet) 3542 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 3543 cpu, msr, target_c_local); 3544 3545 if (!target_c_local) 3546 goto guess; 3547 3548 tcc_activation_temp = target_c_local; 3549 3550 return 0; 3551 3552 guess: 3553 tcc_activation_temp = TJMAX_DEFAULT; 3554 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 3555 cpu, tcc_activation_temp); 3556 3557 return 0; 3558 } 3559 3560 void decode_feature_control_msr(void) 3561 { 3562 unsigned long long msr; 3563 3564 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) 3565 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 3566 base_cpu, msr, 3567 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", 3568 msr & (1 << 18) ? "SGX" : ""); 3569 } 3570 3571 void decode_misc_enable_msr(void) 3572 { 3573 unsigned long long msr; 3574 3575 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 3576 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 3577 base_cpu, msr, 3578 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 3579 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 3580 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "No-" : "", 3581 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 3582 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 3583 } 3584 3585 void decode_misc_feature_control(void) 3586 { 3587 unsigned long long msr; 3588 3589 if (!has_misc_feature_control) 3590 return; 3591 3592 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 3593 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 3594 base_cpu, msr, 3595 msr & (0 << 0) ? "No-" : "", 3596 msr & (1 << 0) ? "No-" : "", 3597 msr & (2 << 0) ? "No-" : "", 3598 msr & (3 << 0) ? "No-" : ""); 3599 } 3600 /* 3601 * Decode MSR_MISC_PWR_MGMT 3602 * 3603 * Decode the bits according to the Nehalem documentation 3604 * bit[0] seems to continue to have same meaning going forward 3605 * bit[1] less so... 3606 */ 3607 void decode_misc_pwr_mgmt_msr(void) 3608 { 3609 unsigned long long msr; 3610 3611 if (!do_nhm_platform_info) 3612 return; 3613 3614 if (no_MSR_MISC_PWR_MGMT) 3615 return; 3616 3617 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 3618 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 3619 base_cpu, msr, 3620 msr & (1 << 0) ? "DIS" : "EN", 3621 msr & (1 << 1) ? "EN" : "DIS", 3622 msr & (1 << 8) ? "EN" : "DIS"); 3623 } 3624 /* 3625 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 3626 * 3627 * This MSRs are present on Silvermont processors, 3628 * Intel Atom processor E3000 series (Baytrail), and friends. 3629 */ 3630 void decode_c6_demotion_policy_msr(void) 3631 { 3632 unsigned long long msr; 3633 3634 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 3635 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 3636 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 3637 3638 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 3639 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 3640 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 3641 } 3642 3643 void process_cpuid() 3644 { 3645 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level; 3646 unsigned int fms, family, model, stepping; 3647 unsigned int has_turbo; 3648 3649 eax = ebx = ecx = edx = 0; 3650 3651 __cpuid(0, max_level, ebx, ecx, edx); 3652 3653 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) 3654 genuine_intel = 1; 3655 3656 if (!quiet) 3657 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 3658 (char *)&ebx, (char *)&edx, (char *)&ecx); 3659 3660 __cpuid(1, fms, ebx, ecx, edx); 3661 family = (fms >> 8) & 0xf; 3662 model = (fms >> 4) & 0xf; 3663 stepping = fms & 0xf; 3664 if (family == 6 || family == 0xf) 3665 model += ((fms >> 16) & 0xf) << 4; 3666 3667 if (!quiet) { 3668 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 3669 max_level, family, model, stepping, family, model, stepping); 3670 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n", 3671 ecx & (1 << 0) ? "SSE3" : "-", 3672 ecx & (1 << 3) ? "MONITOR" : "-", 3673 ecx & (1 << 6) ? "SMX" : "-", 3674 ecx & (1 << 7) ? "EIST" : "-", 3675 ecx & (1 << 8) ? "TM2" : "-", 3676 edx & (1 << 4) ? "TSC" : "-", 3677 edx & (1 << 5) ? "MSR" : "-", 3678 edx & (1 << 22) ? "ACPI-TM" : "-", 3679 edx & (1 << 29) ? "TM" : "-"); 3680 } 3681 3682 if (!(edx & (1 << 5))) 3683 errx(1, "CPUID: no MSR"); 3684 3685 /* 3686 * check max extended function levels of CPUID. 3687 * This is needed to check for invariant TSC. 3688 * This check is valid for both Intel and AMD. 3689 */ 3690 ebx = ecx = edx = 0; 3691 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 3692 3693 if (max_extended_level >= 0x80000007) { 3694 3695 /* 3696 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 3697 * this check is valid for both Intel and AMD 3698 */ 3699 __cpuid(0x80000007, eax, ebx, ecx, edx); 3700 has_invariant_tsc = edx & (1 << 8); 3701 } 3702 3703 /* 3704 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 3705 * this check is valid for both Intel and AMD 3706 */ 3707 3708 __cpuid(0x6, eax, ebx, ecx, edx); 3709 has_aperf = ecx & (1 << 0); 3710 if (has_aperf) { 3711 BIC_PRESENT(BIC_Avg_MHz); 3712 BIC_PRESENT(BIC_Busy); 3713 BIC_PRESENT(BIC_Bzy_MHz); 3714 } 3715 do_dts = eax & (1 << 0); 3716 if (do_dts) 3717 BIC_PRESENT(BIC_CoreTmp); 3718 has_turbo = eax & (1 << 1); 3719 do_ptm = eax & (1 << 6); 3720 if (do_ptm) 3721 BIC_PRESENT(BIC_PkgTmp); 3722 has_hwp = eax & (1 << 7); 3723 has_hwp_notify = eax & (1 << 8); 3724 has_hwp_activity_window = eax & (1 << 9); 3725 has_hwp_epp = eax & (1 << 10); 3726 has_hwp_pkg = eax & (1 << 11); 3727 has_epb = ecx & (1 << 3); 3728 3729 if (!quiet) 3730 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 3731 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 3732 has_aperf ? "" : "No-", 3733 has_turbo ? "" : "No-", 3734 do_dts ? "" : "No-", 3735 do_ptm ? "" : "No-", 3736 has_hwp ? "" : "No-", 3737 has_hwp_notify ? "" : "No-", 3738 has_hwp_activity_window ? "" : "No-", 3739 has_hwp_epp ? "" : "No-", 3740 has_hwp_pkg ? "" : "No-", 3741 has_epb ? "" : "No-"); 3742 3743 if (!quiet) 3744 decode_misc_enable_msr(); 3745 3746 3747 if (max_level >= 0x7 && !quiet) { 3748 int has_sgx; 3749 3750 ecx = 0; 3751 3752 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 3753 3754 has_sgx = ebx & (1 << 2); 3755 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 3756 3757 if (has_sgx) 3758 decode_feature_control_msr(); 3759 } 3760 3761 if (max_level >= 0x15) { 3762 unsigned int eax_crystal; 3763 unsigned int ebx_tsc; 3764 3765 /* 3766 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 3767 */ 3768 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 3769 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 3770 3771 if (ebx_tsc != 0) { 3772 3773 if (!quiet && (ebx != 0)) 3774 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 3775 eax_crystal, ebx_tsc, crystal_hz); 3776 3777 if (crystal_hz == 0) 3778 switch(model) { 3779 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3780 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3781 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3782 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3783 crystal_hz = 24000000; /* 24.0 MHz */ 3784 break; 3785 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3786 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3787 crystal_hz = 25000000; /* 25.0 MHz */ 3788 break; 3789 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3790 case INTEL_FAM6_ATOM_GEMINI_LAKE: 3791 crystal_hz = 19200000; /* 19.2 MHz */ 3792 break; 3793 default: 3794 crystal_hz = 0; 3795 } 3796 3797 if (crystal_hz) { 3798 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 3799 if (!quiet) 3800 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 3801 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 3802 } 3803 } 3804 } 3805 if (max_level >= 0x16) { 3806 unsigned int base_mhz, max_mhz, bus_mhz, edx; 3807 3808 /* 3809 * CPUID 16H Base MHz, Max MHz, Bus MHz 3810 */ 3811 base_mhz = max_mhz = bus_mhz = edx = 0; 3812 3813 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 3814 if (!quiet) 3815 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 3816 base_mhz, max_mhz, bus_mhz); 3817 } 3818 3819 if (has_aperf) 3820 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 3821 3822 BIC_PRESENT(BIC_IRQ); 3823 BIC_PRESENT(BIC_TSC_MHz); 3824 3825 if (probe_nhm_msrs(family, model)) { 3826 do_nhm_platform_info = 1; 3827 BIC_PRESENT(BIC_CPU_c1); 3828 BIC_PRESENT(BIC_CPU_c3); 3829 BIC_PRESENT(BIC_CPU_c6); 3830 BIC_PRESENT(BIC_SMI); 3831 } 3832 do_snb_cstates = has_snb_msrs(family, model); 3833 3834 if (do_snb_cstates) 3835 BIC_PRESENT(BIC_CPU_c7); 3836 3837 do_irtl_snb = has_snb_msrs(family, model); 3838 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 3839 BIC_PRESENT(BIC_Pkgpc2); 3840 if (pkg_cstate_limit >= PCL__3) 3841 BIC_PRESENT(BIC_Pkgpc3); 3842 if (pkg_cstate_limit >= PCL__6) 3843 BIC_PRESENT(BIC_Pkgpc6); 3844 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 3845 BIC_PRESENT(BIC_Pkgpc7); 3846 if (has_slv_msrs(family, model)) { 3847 BIC_NOT_PRESENT(BIC_Pkgpc2); 3848 BIC_NOT_PRESENT(BIC_Pkgpc3); 3849 BIC_PRESENT(BIC_Pkgpc6); 3850 BIC_NOT_PRESENT(BIC_Pkgpc7); 3851 BIC_PRESENT(BIC_Mod_c6); 3852 use_c1_residency_msr = 1; 3853 } 3854 if (has_hsw_msrs(family, model)) { 3855 BIC_PRESENT(BIC_Pkgpc8); 3856 BIC_PRESENT(BIC_Pkgpc9); 3857 BIC_PRESENT(BIC_Pkgpc10); 3858 } 3859 do_irtl_hsw = has_hsw_msrs(family, model); 3860 do_skl_residency = has_skl_msrs(family, model); 3861 do_slm_cstates = is_slm(family, model); 3862 do_knl_cstates = is_knl(family, model); 3863 3864 if (!quiet) 3865 decode_misc_pwr_mgmt_msr(); 3866 3867 if (!quiet && has_slv_msrs(family, model)) 3868 decode_c6_demotion_policy_msr(); 3869 3870 rapl_probe(family, model); 3871 perf_limit_reasons_probe(family, model); 3872 3873 if (!quiet) 3874 dump_cstate_pstate_config_info(family, model); 3875 3876 if (has_skl_msrs(family, model)) 3877 calculate_tsc_tweak(); 3878 3879 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 3880 BIC_PRESENT(BIC_GFX_rc6); 3881 3882 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 3883 BIC_PRESENT(BIC_GFXMHz); 3884 3885 if (!quiet) 3886 decode_misc_feature_control(); 3887 3888 return; 3889 } 3890 3891 void help() 3892 { 3893 fprintf(outf, 3894 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 3895 "\n" 3896 "Turbostat forks the specified COMMAND and prints statistics\n" 3897 "when COMMAND completes.\n" 3898 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 3899 "to print statistics, until interrupted.\n" 3900 "--add add a counter\n" 3901 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 3902 "--quiet skip decoding system configuration header\n" 3903 "--interval sec Override default 5-second measurement interval\n" 3904 "--help print this help message\n" 3905 "--out file create or truncate \"file\" for all output\n" 3906 "--version print version information\n" 3907 "\n" 3908 "For more help, run \"man turbostat\"\n"); 3909 } 3910 3911 3912 /* 3913 * in /dev/cpu/ return success for names that are numbers 3914 * ie. filter out ".", "..", "microcode". 3915 */ 3916 int dir_filter(const struct dirent *dirp) 3917 { 3918 if (isdigit(dirp->d_name[0])) 3919 return 1; 3920 else 3921 return 0; 3922 } 3923 3924 int open_dev_cpu_msr(int dummy1) 3925 { 3926 return 0; 3927 } 3928 3929 void topology_probe() 3930 { 3931 int i; 3932 int max_core_id = 0; 3933 int max_package_id = 0; 3934 int max_siblings = 0; 3935 struct cpu_topology { 3936 int core_id; 3937 int physical_package_id; 3938 } *cpus; 3939 3940 /* Initialize num_cpus, max_cpu_num */ 3941 topo.num_cpus = 0; 3942 topo.max_cpu_num = 0; 3943 for_all_proc_cpus(count_cpus); 3944 if (!summary_only && topo.num_cpus > 1) 3945 BIC_PRESENT(BIC_CPU); 3946 3947 if (debug > 1) 3948 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 3949 3950 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 3951 if (cpus == NULL) 3952 err(1, "calloc cpus"); 3953 3954 /* 3955 * Allocate and initialize cpu_present_set 3956 */ 3957 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 3958 if (cpu_present_set == NULL) 3959 err(3, "CPU_ALLOC"); 3960 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3961 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 3962 for_all_proc_cpus(mark_cpu_present); 3963 3964 /* 3965 * Allocate and initialize cpu_affinity_set 3966 */ 3967 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 3968 if (cpu_affinity_set == NULL) 3969 err(3, "CPU_ALLOC"); 3970 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3971 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 3972 3973 3974 /* 3975 * For online cpus 3976 * find max_core_id, max_package_id 3977 */ 3978 for (i = 0; i <= topo.max_cpu_num; ++i) { 3979 int siblings; 3980 3981 if (cpu_is_not_present(i)) { 3982 if (debug > 1) 3983 fprintf(outf, "cpu%d NOT PRESENT\n", i); 3984 continue; 3985 } 3986 cpus[i].core_id = get_core_id(i); 3987 if (cpus[i].core_id > max_core_id) 3988 max_core_id = cpus[i].core_id; 3989 3990 cpus[i].physical_package_id = get_physical_package_id(i); 3991 if (cpus[i].physical_package_id > max_package_id) 3992 max_package_id = cpus[i].physical_package_id; 3993 3994 siblings = get_num_ht_siblings(i); 3995 if (siblings > max_siblings) 3996 max_siblings = siblings; 3997 if (debug > 1) 3998 fprintf(outf, "cpu %d pkg %d core %d\n", 3999 i, cpus[i].physical_package_id, cpus[i].core_id); 4000 } 4001 topo.num_cores_per_pkg = max_core_id + 1; 4002 if (debug > 1) 4003 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 4004 max_core_id, topo.num_cores_per_pkg); 4005 if (!summary_only && topo.num_cores_per_pkg > 1) 4006 BIC_PRESENT(BIC_Core); 4007 4008 topo.num_packages = max_package_id + 1; 4009 if (debug > 1) 4010 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 4011 max_package_id, topo.num_packages); 4012 if (debug && !summary_only && topo.num_packages > 1) 4013 BIC_PRESENT(BIC_Package); 4014 4015 topo.num_threads_per_core = max_siblings; 4016 if (debug > 1) 4017 fprintf(outf, "max_siblings %d\n", max_siblings); 4018 4019 free(cpus); 4020 } 4021 4022 void 4023 allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) 4024 { 4025 int i; 4026 4027 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg * 4028 topo.num_packages, sizeof(struct thread_data)); 4029 if (*t == NULL) 4030 goto error; 4031 4032 for (i = 0; i < topo.num_threads_per_core * 4033 topo.num_cores_per_pkg * topo.num_packages; i++) 4034 (*t)[i].cpu_id = -1; 4035 4036 *c = calloc(topo.num_cores_per_pkg * topo.num_packages, 4037 sizeof(struct core_data)); 4038 if (*c == NULL) 4039 goto error; 4040 4041 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++) 4042 (*c)[i].core_id = -1; 4043 4044 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 4045 if (*p == NULL) 4046 goto error; 4047 4048 for (i = 0; i < topo.num_packages; i++) 4049 (*p)[i].package_id = i; 4050 4051 return; 4052 error: 4053 err(1, "calloc counters"); 4054 } 4055 /* 4056 * init_counter() 4057 * 4058 * set cpu_id, core_num, pkg_num 4059 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 4060 * 4061 * increment topo.num_cores when 1st core in pkg seen 4062 */ 4063 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 4064 struct pkg_data *pkg_base, int thread_num, int core_num, 4065 int pkg_num, int cpu_id) 4066 { 4067 struct thread_data *t; 4068 struct core_data *c; 4069 struct pkg_data *p; 4070 4071 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num); 4072 c = GET_CORE(core_base, core_num, pkg_num); 4073 p = GET_PKG(pkg_base, pkg_num); 4074 4075 t->cpu_id = cpu_id; 4076 if (thread_num == 0) { 4077 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 4078 if (cpu_is_first_core_in_package(cpu_id)) 4079 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 4080 } 4081 4082 c->core_id = core_num; 4083 p->package_id = pkg_num; 4084 } 4085 4086 4087 int initialize_counters(int cpu_id) 4088 { 4089 int my_thread_id, my_core_id, my_package_id; 4090 4091 my_package_id = get_physical_package_id(cpu_id); 4092 my_core_id = get_core_id(cpu_id); 4093 my_thread_id = get_cpu_position_in_core(cpu_id); 4094 if (!my_thread_id) 4095 topo.num_cores++; 4096 4097 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); 4098 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); 4099 return 0; 4100 } 4101 4102 void allocate_output_buffer() 4103 { 4104 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); 4105 outp = output_buffer; 4106 if (outp == NULL) 4107 err(-1, "calloc output buffer"); 4108 } 4109 void allocate_fd_percpu(void) 4110 { 4111 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 4112 if (fd_percpu == NULL) 4113 err(-1, "calloc fd_percpu"); 4114 } 4115 void allocate_irq_buffers(void) 4116 { 4117 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 4118 if (irq_column_2_cpu == NULL) 4119 err(-1, "calloc %d", topo.num_cpus); 4120 4121 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 4122 if (irqs_per_cpu == NULL) 4123 err(-1, "calloc %d", topo.max_cpu_num + 1); 4124 } 4125 void setup_all_buffers(void) 4126 { 4127 topology_probe(); 4128 allocate_irq_buffers(); 4129 allocate_fd_percpu(); 4130 allocate_counters(&thread_even, &core_even, &package_even); 4131 allocate_counters(&thread_odd, &core_odd, &package_odd); 4132 allocate_output_buffer(); 4133 for_all_proc_cpus(initialize_counters); 4134 } 4135 4136 void set_base_cpu(void) 4137 { 4138 base_cpu = sched_getcpu(); 4139 if (base_cpu < 0) 4140 err(-ENODEV, "No valid cpus found"); 4141 4142 if (debug > 1) 4143 fprintf(outf, "base_cpu = %d\n", base_cpu); 4144 } 4145 4146 void turbostat_init() 4147 { 4148 setup_all_buffers(); 4149 set_base_cpu(); 4150 check_dev_msr(); 4151 check_permissions(); 4152 process_cpuid(); 4153 4154 4155 if (!quiet) 4156 for_all_cpus(print_hwp, ODD_COUNTERS); 4157 4158 if (!quiet) 4159 for_all_cpus(print_epb, ODD_COUNTERS); 4160 4161 if (!quiet) 4162 for_all_cpus(print_perf_limit, ODD_COUNTERS); 4163 4164 if (!quiet) 4165 for_all_cpus(print_rapl, ODD_COUNTERS); 4166 4167 for_all_cpus(set_temperature_target, ODD_COUNTERS); 4168 4169 if (!quiet) 4170 for_all_cpus(print_thermal, ODD_COUNTERS); 4171 4172 if (!quiet && do_irtl_snb) 4173 print_irtl(); 4174 } 4175 4176 int fork_it(char **argv) 4177 { 4178 pid_t child_pid; 4179 int status; 4180 4181 status = for_all_cpus(get_counters, EVEN_COUNTERS); 4182 if (status) 4183 exit(status); 4184 /* clear affinity side-effect of get_counters() */ 4185 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 4186 gettimeofday(&tv_even, (struct timezone *)NULL); 4187 4188 child_pid = fork(); 4189 if (!child_pid) { 4190 /* child */ 4191 execvp(argv[0], argv); 4192 } else { 4193 4194 /* parent */ 4195 if (child_pid == -1) 4196 err(1, "fork"); 4197 4198 signal(SIGINT, SIG_IGN); 4199 signal(SIGQUIT, SIG_IGN); 4200 if (waitpid(child_pid, &status, 0) == -1) 4201 err(status, "waitpid"); 4202 } 4203 /* 4204 * n.b. fork_it() does not check for errors from for_all_cpus() 4205 * because re-starting is problematic when forking 4206 */ 4207 for_all_cpus(get_counters, ODD_COUNTERS); 4208 gettimeofday(&tv_odd, (struct timezone *)NULL); 4209 timersub(&tv_odd, &tv_even, &tv_delta); 4210 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 4211 fprintf(outf, "%s: Counter reset detected\n", progname); 4212 else { 4213 compute_average(EVEN_COUNTERS); 4214 format_all_counters(EVEN_COUNTERS); 4215 } 4216 4217 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 4218 4219 flush_output_stderr(); 4220 4221 return status; 4222 } 4223 4224 int get_and_dump_counters(void) 4225 { 4226 int status; 4227 4228 status = for_all_cpus(get_counters, ODD_COUNTERS); 4229 if (status) 4230 return status; 4231 4232 status = for_all_cpus(dump_counters, ODD_COUNTERS); 4233 if (status) 4234 return status; 4235 4236 flush_output_stdout(); 4237 4238 return status; 4239 } 4240 4241 void print_version() { 4242 fprintf(outf, "turbostat version 4.17 10 Jan 2017" 4243 " - Len Brown <lenb@kernel.org>\n"); 4244 } 4245 4246 int add_counter(unsigned int msr_num, char *name, unsigned int width, 4247 enum counter_scope scope, enum counter_type type, 4248 enum counter_format format) 4249 { 4250 struct msr_counter *msrp; 4251 4252 msrp = calloc(1, sizeof(struct msr_counter)); 4253 if (msrp == NULL) { 4254 perror("calloc"); 4255 exit(1); 4256 } 4257 4258 msrp->msr_num = msr_num; 4259 strncpy(msrp->name, name, NAME_BYTES); 4260 msrp->width = width; 4261 msrp->type = type; 4262 msrp->format = format; 4263 4264 switch (scope) { 4265 4266 case SCOPE_CPU: 4267 msrp->next = sys.tp; 4268 sys.tp = msrp; 4269 sys.added_thread_counters++; 4270 if (sys.added_thread_counters > MAX_ADDED_COUNTERS) { 4271 fprintf(stderr, "exceeded max %d added thread counters\n", 4272 MAX_ADDED_COUNTERS); 4273 exit(-1); 4274 } 4275 break; 4276 4277 case SCOPE_CORE: 4278 msrp->next = sys.cp; 4279 sys.cp = msrp; 4280 sys.added_core_counters++; 4281 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 4282 fprintf(stderr, "exceeded max %d added core counters\n", 4283 MAX_ADDED_COUNTERS); 4284 exit(-1); 4285 } 4286 break; 4287 4288 case SCOPE_PACKAGE: 4289 msrp->next = sys.pp; 4290 sys.pp = msrp; 4291 sys.added_package_counters++; 4292 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 4293 fprintf(stderr, "exceeded max %d added package counters\n", 4294 MAX_ADDED_COUNTERS); 4295 exit(-1); 4296 } 4297 break; 4298 } 4299 4300 return 0; 4301 } 4302 4303 void parse_add_command(char *add_command) 4304 { 4305 int msr_num = 0; 4306 char name_buffer[NAME_BYTES] = ""; 4307 int width = 64; 4308 int fail = 0; 4309 enum counter_scope scope = SCOPE_CPU; 4310 enum counter_type type = COUNTER_CYCLES; 4311 enum counter_format format = FORMAT_DELTA; 4312 4313 while (add_command) { 4314 4315 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 4316 goto next; 4317 4318 if (sscanf(add_command, "msr%d", &msr_num) == 1) 4319 goto next; 4320 4321 if (sscanf(add_command, "u%d", &width) == 1) { 4322 if ((width == 32) || (width == 64)) 4323 goto next; 4324 width = 64; 4325 } 4326 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 4327 scope = SCOPE_CPU; 4328 goto next; 4329 } 4330 if (!strncmp(add_command, "core", strlen("core"))) { 4331 scope = SCOPE_CORE; 4332 goto next; 4333 } 4334 if (!strncmp(add_command, "package", strlen("package"))) { 4335 scope = SCOPE_PACKAGE; 4336 goto next; 4337 } 4338 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 4339 type = COUNTER_CYCLES; 4340 goto next; 4341 } 4342 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 4343 type = COUNTER_SECONDS; 4344 goto next; 4345 } 4346 if (!strncmp(add_command, "raw", strlen("raw"))) { 4347 format = FORMAT_RAW; 4348 goto next; 4349 } 4350 if (!strncmp(add_command, "delta", strlen("delta"))) { 4351 format = FORMAT_DELTA; 4352 goto next; 4353 } 4354 if (!strncmp(add_command, "percent", strlen("percent"))) { 4355 format = FORMAT_PERCENT; 4356 goto next; 4357 } 4358 4359 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 4360 char *eos; 4361 4362 eos = strchr(name_buffer, ','); 4363 if (eos) 4364 *eos = '\0'; 4365 goto next; 4366 } 4367 4368 next: 4369 add_command = strchr(add_command, ','); 4370 if (add_command) 4371 add_command++; 4372 4373 } 4374 if (msr_num == 0) { 4375 fprintf(stderr, "--add: (msrDDD | msr0xXXX) required\n"); 4376 fail++; 4377 } 4378 4379 /* generate default column header */ 4380 if (*name_buffer == '\0') { 4381 if (format == FORMAT_RAW) { 4382 if (width == 32) 4383 sprintf(name_buffer, "msr%d", msr_num); 4384 else 4385 sprintf(name_buffer, "MSR%d", msr_num); 4386 } else if (format == FORMAT_DELTA) { 4387 if (width == 32) 4388 sprintf(name_buffer, "cnt%d", msr_num); 4389 else 4390 sprintf(name_buffer, "CNT%d", msr_num); 4391 } else if (format == FORMAT_PERCENT) { 4392 if (width == 32) 4393 sprintf(name_buffer, "msr%d%%", msr_num); 4394 else 4395 sprintf(name_buffer, "MSR%d%%", msr_num); 4396 } 4397 } 4398 4399 if (add_counter(msr_num, name_buffer, width, scope, type, format)) 4400 fail++; 4401 4402 if (fail) { 4403 help(); 4404 exit(1); 4405 } 4406 } 4407 /* 4408 * HIDE_LIST - hide this list of counters, show the rest [default] 4409 * SHOW_LIST - show this list of counters, hide the rest 4410 */ 4411 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 4412 4413 int shown; 4414 /* 4415 * parse_show_hide() - process cmdline to set default counter action 4416 */ 4417 void parse_show_hide(char *optarg, enum show_hide_mode new_mode) 4418 { 4419 /* 4420 * --show: show only those specified 4421 * The 1st invocation will clear and replace the enabled mask 4422 * subsequent invocations can add to it. 4423 */ 4424 if (new_mode == SHOW_LIST) { 4425 if (shown == 0) 4426 bic_enabled = bic_lookup(optarg); 4427 else 4428 bic_enabled |= bic_lookup(optarg); 4429 shown = 1; 4430 4431 return; 4432 } 4433 4434 /* 4435 * --hide: do not show those specified 4436 * multiple invocations simply clear more bits in enabled mask 4437 */ 4438 bic_enabled &= ~bic_lookup(optarg); 4439 } 4440 4441 void cmdline(int argc, char **argv) 4442 { 4443 int opt; 4444 int option_index = 0; 4445 static struct option long_options[] = { 4446 {"add", required_argument, 0, 'a'}, 4447 {"Dump", no_argument, 0, 'D'}, 4448 {"debug", no_argument, 0, 'd'}, /* internal, not documented */ 4449 {"interval", required_argument, 0, 'i'}, 4450 {"help", no_argument, 0, 'h'}, 4451 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help 4452 {"Joules", no_argument, 0, 'J'}, 4453 {"out", required_argument, 0, 'o'}, 4454 {"Package", no_argument, 0, 'p'}, 4455 {"processor", no_argument, 0, 'p'}, 4456 {"quiet", no_argument, 0, 'q'}, 4457 {"show", required_argument, 0, 's'}, 4458 {"Summary", no_argument, 0, 'S'}, 4459 {"TCC", required_argument, 0, 'T'}, 4460 {"version", no_argument, 0, 'v' }, 4461 {0, 0, 0, 0 } 4462 }; 4463 4464 progname = argv[0]; 4465 4466 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpqST:v", 4467 long_options, &option_index)) != -1) { 4468 switch (opt) { 4469 case 'a': 4470 parse_add_command(optarg); 4471 break; 4472 case 'D': 4473 dump_only++; 4474 break; 4475 case 'd': 4476 debug++; 4477 break; 4478 case 'H': 4479 parse_show_hide(optarg, HIDE_LIST); 4480 break; 4481 case 'h': 4482 default: 4483 help(); 4484 exit(1); 4485 case 'i': 4486 { 4487 double interval = strtod(optarg, NULL); 4488 4489 if (interval < 0.001) { 4490 fprintf(outf, "interval %f seconds is too small\n", 4491 interval); 4492 exit(2); 4493 } 4494 4495 interval_ts.tv_sec = interval; 4496 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 4497 } 4498 break; 4499 case 'J': 4500 rapl_joules++; 4501 break; 4502 case 'o': 4503 outf = fopen_or_die(optarg, "w"); 4504 break; 4505 case 'P': 4506 show_pkg_only++; 4507 break; 4508 case 'p': 4509 show_core_only++; 4510 break; 4511 case 'q': 4512 quiet = 1; 4513 break; 4514 case 's': 4515 parse_show_hide(optarg, SHOW_LIST); 4516 break; 4517 case 'S': 4518 summary_only++; 4519 break; 4520 case 'T': 4521 tcc_activation_temp_override = atoi(optarg); 4522 break; 4523 case 'v': 4524 print_version(); 4525 exit(0); 4526 break; 4527 } 4528 } 4529 } 4530 4531 int main(int argc, char **argv) 4532 { 4533 outf = stderr; 4534 4535 cmdline(argc, argv); 4536 4537 if (!quiet) 4538 print_version(); 4539 4540 turbostat_init(); 4541 4542 /* dump counters and exit */ 4543 if (dump_only) 4544 return get_and_dump_counters(); 4545 4546 /* 4547 * if any params left, it must be a command to fork 4548 */ 4549 if (argc - optind) 4550 return fork_it(argv + optind); 4551 else 4552 turbostat_loop(); 4553 4554 return 0; 4555 } 4556