1 /* 2 * turbostat -- show CPU frequency and C-state residency 3 * on modern Intel turbo-capable processors. 4 * 5 * Copyright (c) 2013 Intel Corporation. 6 * Len Brown <len.brown@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #define _GNU_SOURCE 23 #include MSRHEADER 24 #include INTEL_FAMILY_HEADER 25 #include <stdarg.h> 26 #include <stdio.h> 27 #include <err.h> 28 #include <unistd.h> 29 #include <sys/types.h> 30 #include <sys/wait.h> 31 #include <sys/stat.h> 32 #include <sys/resource.h> 33 #include <fcntl.h> 34 #include <signal.h> 35 #include <sys/time.h> 36 #include <stdlib.h> 37 #include <getopt.h> 38 #include <dirent.h> 39 #include <string.h> 40 #include <ctype.h> 41 #include <sched.h> 42 #include <time.h> 43 #include <cpuid.h> 44 #include <linux/capability.h> 45 #include <errno.h> 46 47 char *proc_stat = "/proc/stat"; 48 FILE *outf; 49 int *fd_percpu; 50 struct timespec interval_ts = {5, 0}; 51 unsigned int debug; 52 unsigned int rapl_joules; 53 unsigned int summary_only; 54 unsigned int dump_only; 55 unsigned int do_snb_cstates; 56 unsigned int do_knl_cstates; 57 unsigned int do_pc2; 58 unsigned int do_pc3; 59 unsigned int do_pc6; 60 unsigned int do_pc7; 61 unsigned int do_c8_c9_c10; 62 unsigned int do_skl_residency; 63 unsigned int do_slm_cstates; 64 unsigned int use_c1_residency_msr; 65 unsigned int has_aperf; 66 unsigned int has_epb; 67 unsigned int do_irtl_snb; 68 unsigned int do_irtl_hsw; 69 unsigned int units = 1000000; /* MHz etc */ 70 unsigned int genuine_intel; 71 unsigned int has_invariant_tsc; 72 unsigned int do_nhm_platform_info; 73 unsigned int no_MSR_MISC_PWR_MGMT; 74 unsigned int aperf_mperf_multiplier = 1; 75 double bclk; 76 double base_hz; 77 unsigned int has_base_hz; 78 double tsc_tweak = 1.0; 79 unsigned int show_pkg_only; 80 unsigned int show_core_only; 81 char *output_buffer, *outp; 82 unsigned int do_rapl; 83 unsigned int do_dts; 84 unsigned int do_ptm; 85 unsigned long long gfx_cur_rc6_ms; 86 unsigned int gfx_cur_mhz; 87 unsigned int tcc_activation_temp; 88 unsigned int tcc_activation_temp_override; 89 double rapl_power_units, rapl_time_units; 90 double rapl_dram_energy_units, rapl_energy_units; 91 double rapl_joule_counter_range; 92 unsigned int do_core_perf_limit_reasons; 93 unsigned int do_gfx_perf_limit_reasons; 94 unsigned int do_ring_perf_limit_reasons; 95 unsigned int crystal_hz; 96 unsigned long long tsc_hz; 97 int base_cpu; 98 double discover_bclk(unsigned int family, unsigned int model); 99 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 100 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 101 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 102 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 103 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 104 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 105 unsigned int has_misc_feature_control; 106 107 #define RAPL_PKG (1 << 0) 108 /* 0x610 MSR_PKG_POWER_LIMIT */ 109 /* 0x611 MSR_PKG_ENERGY_STATUS */ 110 #define RAPL_PKG_PERF_STATUS (1 << 1) 111 /* 0x613 MSR_PKG_PERF_STATUS */ 112 #define RAPL_PKG_POWER_INFO (1 << 2) 113 /* 0x614 MSR_PKG_POWER_INFO */ 114 115 #define RAPL_DRAM (1 << 3) 116 /* 0x618 MSR_DRAM_POWER_LIMIT */ 117 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 118 #define RAPL_DRAM_PERF_STATUS (1 << 4) 119 /* 0x61b MSR_DRAM_PERF_STATUS */ 120 #define RAPL_DRAM_POWER_INFO (1 << 5) 121 /* 0x61c MSR_DRAM_POWER_INFO */ 122 123 #define RAPL_CORES_POWER_LIMIT (1 << 6) 124 /* 0x638 MSR_PP0_POWER_LIMIT */ 125 #define RAPL_CORE_POLICY (1 << 7) 126 /* 0x63a MSR_PP0_POLICY */ 127 128 #define RAPL_GFX (1 << 8) 129 /* 0x640 MSR_PP1_POWER_LIMIT */ 130 /* 0x641 MSR_PP1_ENERGY_STATUS */ 131 /* 0x642 MSR_PP1_POLICY */ 132 133 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 134 /* 0x639 MSR_PP0_ENERGY_STATUS */ 135 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 136 #define TJMAX_DEFAULT 100 137 138 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 139 140 /* 141 * buffer size used by sscanf() for added column names 142 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 143 */ 144 #define NAME_BYTES 20 145 146 int backwards_count; 147 char *progname; 148 149 cpu_set_t *cpu_present_set, *cpu_affinity_set; 150 size_t cpu_present_setsize, cpu_affinity_setsize; 151 #define MAX_ADDED_COUNTERS 16 152 153 struct thread_data { 154 unsigned long long tsc; 155 unsigned long long aperf; 156 unsigned long long mperf; 157 unsigned long long c1; 158 unsigned int irq_count; 159 unsigned int smi_count; 160 unsigned int cpu_id; 161 unsigned int flags; 162 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 163 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 164 unsigned long long counter[MAX_ADDED_COUNTERS]; 165 } *thread_even, *thread_odd; 166 167 struct core_data { 168 unsigned long long c3; 169 unsigned long long c6; 170 unsigned long long c7; 171 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 172 unsigned int core_temp_c; 173 unsigned int core_id; 174 unsigned long long counter[MAX_ADDED_COUNTERS]; 175 } *core_even, *core_odd; 176 177 struct pkg_data { 178 unsigned long long pc2; 179 unsigned long long pc3; 180 unsigned long long pc6; 181 unsigned long long pc7; 182 unsigned long long pc8; 183 unsigned long long pc9; 184 unsigned long long pc10; 185 unsigned long long pkg_wtd_core_c0; 186 unsigned long long pkg_any_core_c0; 187 unsigned long long pkg_any_gfxe_c0; 188 unsigned long long pkg_both_core_gfxe_c0; 189 long long gfx_rc6_ms; 190 unsigned int gfx_mhz; 191 unsigned int package_id; 192 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 193 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 194 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 195 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 196 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 197 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 198 unsigned int pkg_temp_c; 199 unsigned long long counter[MAX_ADDED_COUNTERS]; 200 } *package_even, *package_odd; 201 202 #define ODD_COUNTERS thread_odd, core_odd, package_odd 203 #define EVEN_COUNTERS thread_even, core_even, package_even 204 205 #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \ 206 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \ 207 topo.num_threads_per_core + \ 208 (core_no) * topo.num_threads_per_core + (thread_no)) 209 #define GET_CORE(core_base, core_no, pkg_no) \ 210 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no)) 211 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 212 213 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; 214 enum counter_type {COUNTER_CYCLES, COUNTER_SECONDS}; 215 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; 216 217 struct msr_counter { 218 unsigned int msr_num; 219 char name[NAME_BYTES]; 220 unsigned int width; 221 enum counter_type type; 222 enum counter_format format; 223 struct msr_counter *next; 224 unsigned int flags; 225 #define FLAGS_HIDE (1 << 0) 226 #define FLAGS_SHOW (1 << 1) 227 }; 228 229 struct sys_counters { 230 unsigned int added_thread_counters; 231 unsigned int added_core_counters; 232 unsigned int added_package_counters; 233 struct msr_counter *tp; 234 struct msr_counter *cp; 235 struct msr_counter *pp; 236 } sys; 237 238 struct system_summary { 239 struct thread_data threads; 240 struct core_data cores; 241 struct pkg_data packages; 242 } average; 243 244 245 struct topo_params { 246 int num_packages; 247 int num_cpus; 248 int num_cores; 249 int max_cpu_num; 250 int num_cores_per_pkg; 251 int num_threads_per_core; 252 } topo; 253 254 struct timeval tv_even, tv_odd, tv_delta; 255 256 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 257 int *irqs_per_cpu; /* indexed by cpu_num */ 258 259 void setup_all_buffers(void); 260 261 int cpu_is_not_present(int cpu) 262 { 263 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 264 } 265 /* 266 * run func(thread, core, package) in topology order 267 * skip non-present cpus 268 */ 269 270 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 271 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 272 { 273 int retval, pkg_no, core_no, thread_no; 274 275 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 276 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { 277 for (thread_no = 0; thread_no < 278 topo.num_threads_per_core; ++thread_no) { 279 struct thread_data *t; 280 struct core_data *c; 281 struct pkg_data *p; 282 283 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); 284 285 if (cpu_is_not_present(t->cpu_id)) 286 continue; 287 288 c = GET_CORE(core_base, core_no, pkg_no); 289 p = GET_PKG(pkg_base, pkg_no); 290 291 retval = func(t, c, p); 292 if (retval) 293 return retval; 294 } 295 } 296 } 297 return 0; 298 } 299 300 int cpu_migrate(int cpu) 301 { 302 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 303 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 304 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 305 return -1; 306 else 307 return 0; 308 } 309 int get_msr_fd(int cpu) 310 { 311 char pathname[32]; 312 int fd; 313 314 fd = fd_percpu[cpu]; 315 316 if (fd) 317 return fd; 318 319 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 320 fd = open(pathname, O_RDONLY); 321 if (fd < 0) 322 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 323 324 fd_percpu[cpu] = fd; 325 326 return fd; 327 } 328 329 int get_msr(int cpu, off_t offset, unsigned long long *msr) 330 { 331 ssize_t retval; 332 333 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 334 335 if (retval != sizeof *msr) 336 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 337 338 return 0; 339 } 340 341 /* 342 * Each string in this array is compared in --show and --hide cmdline. 343 * Thus, strings that are proper sub-sets must follow their more specific peers. 344 */ 345 struct msr_counter bic[] = { 346 { 0x0, "Package" }, 347 { 0x0, "Avg_MHz" }, 348 { 0x0, "Bzy_MHz" }, 349 { 0x0, "TSC_MHz" }, 350 { 0x0, "IRQ" }, 351 { 0x0, "SMI", 32, 0, FORMAT_DELTA, NULL}, 352 { 0x0, "Busy%" }, 353 { 0x0, "CPU%c1" }, 354 { 0x0, "CPU%c3" }, 355 { 0x0, "CPU%c6" }, 356 { 0x0, "CPU%c7" }, 357 { 0x0, "ThreadC" }, 358 { 0x0, "CoreTmp" }, 359 { 0x0, "CoreCnt" }, 360 { 0x0, "PkgTmp" }, 361 { 0x0, "GFX%rc6" }, 362 { 0x0, "GFXMHz" }, 363 { 0x0, "Pkg%pc2" }, 364 { 0x0, "Pkg%pc3" }, 365 { 0x0, "Pkg%pc6" }, 366 { 0x0, "Pkg%pc7" }, 367 { 0x0, "PkgWatt" }, 368 { 0x0, "CorWatt" }, 369 { 0x0, "GFXWatt" }, 370 { 0x0, "PkgCnt" }, 371 { 0x0, "RAMWatt" }, 372 { 0x0, "PKG_%" }, 373 { 0x0, "RAM_%" }, 374 { 0x0, "Pkg_J" }, 375 { 0x0, "Cor_J" }, 376 { 0x0, "GFX_J" }, 377 { 0x0, "RAM_J" }, 378 { 0x0, "Core" }, 379 { 0x0, "CPU" }, 380 { 0x0, "Mod%c6" }, 381 }; 382 383 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 384 #define BIC_Package (1ULL << 0) 385 #define BIC_Avg_MHz (1ULL << 1) 386 #define BIC_Bzy_MHz (1ULL << 2) 387 #define BIC_TSC_MHz (1ULL << 3) 388 #define BIC_IRQ (1ULL << 4) 389 #define BIC_SMI (1ULL << 5) 390 #define BIC_Busy (1ULL << 6) 391 #define BIC_CPU_c1 (1ULL << 7) 392 #define BIC_CPU_c3 (1ULL << 8) 393 #define BIC_CPU_c6 (1ULL << 9) 394 #define BIC_CPU_c7 (1ULL << 10) 395 #define BIC_ThreadC (1ULL << 11) 396 #define BIC_CoreTmp (1ULL << 12) 397 #define BIC_CoreCnt (1ULL << 13) 398 #define BIC_PkgTmp (1ULL << 14) 399 #define BIC_GFX_rc6 (1ULL << 15) 400 #define BIC_GFXMHz (1ULL << 16) 401 #define BIC_Pkgpc2 (1ULL << 17) 402 #define BIC_Pkgpc3 (1ULL << 18) 403 #define BIC_Pkgpc6 (1ULL << 19) 404 #define BIC_Pkgpc7 (1ULL << 20) 405 #define BIC_PkgWatt (1ULL << 21) 406 #define BIC_CorWatt (1ULL << 22) 407 #define BIC_GFXWatt (1ULL << 23) 408 #define BIC_PkgCnt (1ULL << 24) 409 #define BIC_RAMWatt (1ULL << 27) 410 #define BIC_PKG__ (1ULL << 28) 411 #define BIC_RAM__ (1ULL << 29) 412 #define BIC_Pkg_J (1ULL << 30) 413 #define BIC_Cor_J (1ULL << 31) 414 #define BIC_GFX_J (1ULL << 30) 415 #define BIC_RAM_J (1ULL << 31) 416 #define BIC_Core (1ULL << 32) 417 #define BIC_CPU (1ULL << 33) 418 #define BIC_Mod_c6 (1ULL << 34) 419 420 unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL; 421 unsigned long long bic_present; 422 423 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 424 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 425 426 /* 427 * bic_lookup 428 * for all the strings in comma separate name_list, 429 * set the approprate bit in return value. 430 */ 431 unsigned long long bic_lookup(char *name_list) 432 { 433 int i; 434 unsigned long long retval = 0; 435 436 while (name_list) { 437 char *comma; 438 439 comma = strchr(name_list, ','); 440 441 if (comma) 442 *comma = '\0'; 443 444 for (i = 0; i < MAX_BIC; ++i) { 445 if (!strcmp(name_list, bic[i].name)) { 446 retval |= (1ULL << i); 447 break; 448 } 449 } 450 if (i == MAX_BIC) { 451 fprintf(stderr, "Invalid counter name: %s\n", name_list); 452 exit(-1); 453 } 454 455 name_list = comma; 456 if (name_list) 457 name_list++; 458 459 } 460 return retval; 461 } 462 463 void print_header(void) 464 { 465 struct msr_counter *mp; 466 467 if (DO_BIC(BIC_Package)) 468 outp += sprintf(outp, "\tPackage"); 469 if (DO_BIC(BIC_Core)) 470 outp += sprintf(outp, "\tCore"); 471 if (DO_BIC(BIC_CPU)) 472 outp += sprintf(outp, "\tCPU"); 473 if (DO_BIC(BIC_Avg_MHz)) 474 outp += sprintf(outp, "\tAvg_MHz"); 475 if (DO_BIC(BIC_Busy)) 476 outp += sprintf(outp, "\tBusy%%"); 477 if (DO_BIC(BIC_Bzy_MHz)) 478 outp += sprintf(outp, "\tBzy_MHz"); 479 if (DO_BIC(BIC_TSC_MHz)) 480 outp += sprintf(outp, "\tTSC_MHz"); 481 482 if (DO_BIC(BIC_IRQ)) 483 outp += sprintf(outp, "\tIRQ"); 484 if (DO_BIC(BIC_SMI)) 485 outp += sprintf(outp, "\tSMI"); 486 487 if (DO_BIC(BIC_CPU_c1)) 488 outp += sprintf(outp, "\tCPU%%c1"); 489 490 for (mp = sys.tp; mp; mp = mp->next) { 491 if (mp->format == FORMAT_RAW) { 492 if (mp->width == 64) 493 outp += sprintf(outp, "\t%18.18s", mp->name); 494 else 495 outp += sprintf(outp, "\t%10.10s", mp->name); 496 } else { 497 outp += sprintf(outp, "\t%-7.7s", mp->name); 498 } 499 } 500 501 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) 502 outp += sprintf(outp, "\tCPU%%c3"); 503 if (DO_BIC(BIC_CPU_c6)) 504 outp += sprintf(outp, "\tCPU%%c6"); 505 if (DO_BIC(BIC_CPU_c7)) 506 outp += sprintf(outp, "\tCPU%%c7"); 507 508 if (DO_BIC(BIC_Mod_c6)) 509 outp += sprintf(outp, "\tMod%%c6"); 510 511 if (DO_BIC(BIC_CoreTmp)) 512 outp += sprintf(outp, "\tCoreTmp"); 513 514 for (mp = sys.cp; mp; mp = mp->next) { 515 if (mp->format == FORMAT_RAW) { 516 if (mp->width == 64) 517 outp += sprintf(outp, "\t%18.18s", mp->name); 518 else 519 outp += sprintf(outp, "\t%10.10s", mp->name); 520 } else { 521 outp += sprintf(outp, "\t%-7.7s", mp->name); 522 } 523 } 524 525 if (DO_BIC(BIC_PkgTmp)) 526 outp += sprintf(outp, "\tPkgTmp"); 527 528 if (DO_BIC(BIC_GFX_rc6)) 529 outp += sprintf(outp, "\tGFX%%rc6"); 530 531 if (DO_BIC(BIC_GFXMHz)) 532 outp += sprintf(outp, "\tGFXMHz"); 533 534 if (do_skl_residency) { 535 outp += sprintf(outp, "\tTotl%%C0"); 536 outp += sprintf(outp, "\tAny%%C0"); 537 outp += sprintf(outp, "\tGFX%%C0"); 538 outp += sprintf(outp, "\tCPUGFX%%"); 539 } 540 541 if (do_pc2) 542 outp += sprintf(outp, "\tPkg%%pc2"); 543 if (do_pc3) 544 outp += sprintf(outp, "\tPkg%%pc3"); 545 if (do_pc6) 546 outp += sprintf(outp, "\tPkg%%pc6"); 547 if (do_pc7) 548 outp += sprintf(outp, "\tPkg%%pc7"); 549 if (do_c8_c9_c10) { 550 outp += sprintf(outp, "\tPkg%%pc8"); 551 outp += sprintf(outp, "\tPkg%%pc9"); 552 outp += sprintf(outp, "\tPk%%pc10"); 553 } 554 555 if (do_rapl && !rapl_joules) { 556 if (DO_BIC(BIC_PkgWatt)) 557 outp += sprintf(outp, "\tPkgWatt"); 558 if (DO_BIC(BIC_CorWatt)) 559 outp += sprintf(outp, "\tCorWatt"); 560 if (DO_BIC(BIC_GFXWatt)) 561 outp += sprintf(outp, "\tGFXWatt"); 562 if (DO_BIC(BIC_RAMWatt)) 563 outp += sprintf(outp, "\tRAMWatt"); 564 if (DO_BIC(BIC_PKG__)) 565 outp += sprintf(outp, "\tPKG_%%"); 566 if (DO_BIC(BIC_RAM__)) 567 outp += sprintf(outp, "\tRAM_%%"); 568 } else if (do_rapl && rapl_joules) { 569 if (DO_BIC(BIC_Pkg_J)) 570 outp += sprintf(outp, "\tPkg_J"); 571 if (DO_BIC(BIC_Cor_J)) 572 outp += sprintf(outp, "\tCor_J"); 573 if (DO_BIC(BIC_GFX_J)) 574 outp += sprintf(outp, "\tGFX_J"); 575 if (DO_BIC(BIC_RAM_J)) 576 outp += sprintf(outp, "\tRAM_J"); 577 if (DO_BIC(BIC_PKG__)) 578 outp += sprintf(outp, "\tPKG_%%"); 579 if (DO_BIC(BIC_RAM__)) 580 outp += sprintf(outp, "\tRAM_%%"); 581 } 582 for (mp = sys.pp; mp; mp = mp->next) { 583 if (mp->format == FORMAT_RAW) { 584 if (mp->width == 64) 585 outp += sprintf(outp, "\t%18.18s", mp->name); 586 else 587 outp += sprintf(outp, "\t%10.10s", mp->name); 588 } else { 589 outp += sprintf(outp, "\t%-7.7s", mp->name); 590 } 591 } 592 593 outp += sprintf(outp, "\n"); 594 } 595 596 int dump_counters(struct thread_data *t, struct core_data *c, 597 struct pkg_data *p) 598 { 599 int i; 600 struct msr_counter *mp; 601 602 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 603 604 if (t) { 605 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 606 t->cpu_id, t->flags); 607 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 608 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 609 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 610 outp += sprintf(outp, "c1: %016llX\n", t->c1); 611 612 if (DO_BIC(BIC_IRQ)) 613 outp += sprintf(outp, "IRQ: %08X\n", t->irq_count); 614 if (DO_BIC(BIC_SMI)) 615 outp += sprintf(outp, "SMI: %08X\n", t->smi_count); 616 617 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 618 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", 619 i, mp->msr_num, t->counter[i]); 620 } 621 } 622 623 if (c) { 624 outp += sprintf(outp, "core: %d\n", c->core_id); 625 outp += sprintf(outp, "c3: %016llX\n", c->c3); 626 outp += sprintf(outp, "c6: %016llX\n", c->c6); 627 outp += sprintf(outp, "c7: %016llX\n", c->c7); 628 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 629 630 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 631 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", 632 i, mp->msr_num, c->counter[i]); 633 } 634 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 635 } 636 637 if (p) { 638 outp += sprintf(outp, "package: %d\n", p->package_id); 639 640 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 641 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 642 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 643 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 644 645 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 646 if (do_pc3) 647 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 648 if (do_pc6) 649 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 650 if (do_pc7) 651 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 652 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 653 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 654 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 655 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); 656 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); 657 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); 658 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); 659 outp += sprintf(outp, "Throttle PKG: %0X\n", 660 p->rapl_pkg_perf_status); 661 outp += sprintf(outp, "Throttle RAM: %0X\n", 662 p->rapl_dram_perf_status); 663 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 664 665 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 666 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", 667 i, mp->msr_num, p->counter[i]); 668 } 669 } 670 671 outp += sprintf(outp, "\n"); 672 673 return 0; 674 } 675 676 /* 677 * column formatting convention & formats 678 */ 679 int format_counters(struct thread_data *t, struct core_data *c, 680 struct pkg_data *p) 681 { 682 double interval_float; 683 char *fmt8; 684 int i; 685 struct msr_counter *mp; 686 687 /* if showing only 1st thread in core and this isn't one, bail out */ 688 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 689 return 0; 690 691 /* if showing only 1st thread in pkg and this isn't one, bail out */ 692 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 693 return 0; 694 695 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; 696 697 /* topo columns, print blanks on 1st (average) line */ 698 if (t == &average.threads) { 699 if (DO_BIC(BIC_Package)) 700 outp += sprintf(outp, "\t-"); 701 if (DO_BIC(BIC_Core)) 702 outp += sprintf(outp, "\t-"); 703 if (DO_BIC(BIC_CPU)) 704 outp += sprintf(outp, "\t-"); 705 } else { 706 if (DO_BIC(BIC_Package)) { 707 if (p) 708 outp += sprintf(outp, "\t%d", p->package_id); 709 else 710 outp += sprintf(outp, "\t-"); 711 } 712 if (DO_BIC(BIC_Core)) { 713 if (c) 714 outp += sprintf(outp, "\t%d", c->core_id); 715 else 716 outp += sprintf(outp, "\t-"); 717 } 718 if (DO_BIC(BIC_CPU)) 719 outp += sprintf(outp, "\t%d", t->cpu_id); 720 } 721 722 if (DO_BIC(BIC_Avg_MHz)) 723 outp += sprintf(outp, "\t%.0f", 724 1.0 / units * t->aperf / interval_float); 725 726 if (DO_BIC(BIC_Busy)) 727 outp += sprintf(outp, "\t%.2f", 100.0 * t->mperf/t->tsc/tsc_tweak); 728 729 if (DO_BIC(BIC_Bzy_MHz)) { 730 if (has_base_hz) 731 outp += sprintf(outp, "\t%.0f", base_hz / units * t->aperf / t->mperf); 732 else 733 outp += sprintf(outp, "\t%.0f", 734 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float); 735 } 736 737 if (DO_BIC(BIC_TSC_MHz)) 738 outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float); 739 740 /* IRQ */ 741 if (DO_BIC(BIC_IRQ)) 742 outp += sprintf(outp, "\t%d", t->irq_count); 743 744 /* SMI */ 745 if (DO_BIC(BIC_SMI)) 746 outp += sprintf(outp, "\t%d", t->smi_count); 747 748 /* C1 */ 749 if (DO_BIC(BIC_CPU_c1)) 750 outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/t->tsc); 751 752 /* Added counters */ 753 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 754 if (mp->format == FORMAT_RAW) { 755 if (mp->width == 32) 756 outp += sprintf(outp, "\t0x%08lx", (unsigned long) t->counter[i]); 757 else 758 outp += sprintf(outp, "\t0x%016llx", t->counter[i]); 759 } else if (mp->format == FORMAT_DELTA) { 760 outp += sprintf(outp, "\t%lld", t->counter[i]); 761 } else if (mp->format == FORMAT_PERCENT) { 762 outp += sprintf(outp, "\t%.2f", 100.0 * t->counter[i]/t->tsc); 763 } 764 } 765 766 /* print per-core data only for 1st thread in core */ 767 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 768 goto done; 769 770 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) 771 outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/t->tsc); 772 if (DO_BIC(BIC_CPU_c6)) 773 outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/t->tsc); 774 if (DO_BIC(BIC_CPU_c7)) 775 outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc); 776 777 /* Mod%c6 */ 778 if (DO_BIC(BIC_Mod_c6)) 779 outp += sprintf(outp, "\t%.2f", 100.0 * c->mc6_us / t->tsc); 780 781 if (DO_BIC(BIC_CoreTmp)) 782 outp += sprintf(outp, "\t%d", c->core_temp_c); 783 784 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 785 if (mp->format == FORMAT_RAW) { 786 if (mp->width == 32) 787 outp += sprintf(outp, "\t0x%08lx", (unsigned long) c->counter[i]); 788 else 789 outp += sprintf(outp, "\t0x%016llx", c->counter[i]); 790 } else if (mp->format == FORMAT_DELTA) { 791 outp += sprintf(outp, "\t%lld", c->counter[i]); 792 } else if (mp->format == FORMAT_PERCENT) { 793 outp += sprintf(outp, "\t%.2f", 100.0 * c->counter[i]/t->tsc); 794 } 795 } 796 797 /* print per-package data only for 1st core in package */ 798 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 799 goto done; 800 801 /* PkgTmp */ 802 if (DO_BIC(BIC_PkgTmp)) 803 outp += sprintf(outp, "\t%d", p->pkg_temp_c); 804 805 /* GFXrc6 */ 806 if (DO_BIC(BIC_GFX_rc6)) { 807 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 808 outp += sprintf(outp, "\t**.**"); 809 } else { 810 outp += sprintf(outp, "\t%.2f", 811 p->gfx_rc6_ms / 10.0 / interval_float); 812 } 813 } 814 815 /* GFXMHz */ 816 if (DO_BIC(BIC_GFXMHz)) 817 outp += sprintf(outp, "\t%d", p->gfx_mhz); 818 819 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 820 if (do_skl_residency) { 821 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc); 822 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_core_c0/t->tsc); 823 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc); 824 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc); 825 } 826 827 if (do_pc2) 828 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc2/t->tsc); 829 if (do_pc3) 830 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc3/t->tsc); 831 if (do_pc6) 832 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc6/t->tsc); 833 if (do_pc7) 834 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc7/t->tsc); 835 if (do_c8_c9_c10) { 836 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc8/t->tsc); 837 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc9/t->tsc); 838 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc10/t->tsc); 839 } 840 841 /* 842 * If measurement interval exceeds minimum RAPL Joule Counter range, 843 * indicate that results are suspect by printing "**" in fraction place. 844 */ 845 if (interval_float < rapl_joule_counter_range) 846 fmt8 = "\t%.2f"; 847 else 848 fmt8 = "%6.0f**"; 849 850 if (DO_BIC(BIC_PkgWatt)) 851 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float); 852 if (DO_BIC(BIC_CorWatt)) 853 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float); 854 if (DO_BIC(BIC_GFXWatt)) 855 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float); 856 if (DO_BIC(BIC_RAMWatt)) 857 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float); 858 if (DO_BIC(BIC_Pkg_J)) 859 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units); 860 if (DO_BIC(BIC_Cor_J)) 861 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units); 862 if (DO_BIC(BIC_GFX_J)) 863 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units); 864 if (DO_BIC(BIC_RAM_J)) 865 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units); 866 if (DO_BIC(BIC_PKG__)) 867 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 868 if (DO_BIC(BIC_RAM__)) 869 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 870 871 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 872 if (mp->format == FORMAT_RAW) { 873 if (mp->width == 32) 874 outp += sprintf(outp, "\t0x%08lx", (unsigned long) p->counter[i]); 875 else 876 outp += sprintf(outp, "\t0x%016llx", p->counter[i]); 877 } else if (mp->format == FORMAT_DELTA) { 878 outp += sprintf(outp, "\t%lld", p->counter[i]); 879 } else if (mp->format == FORMAT_PERCENT) { 880 outp += sprintf(outp, "\t%.2f", 100.0 * p->counter[i]/t->tsc); 881 } 882 } 883 884 done: 885 outp += sprintf(outp, "\n"); 886 887 return 0; 888 } 889 890 void flush_output_stdout(void) 891 { 892 FILE *filep; 893 894 if (outf == stderr) 895 filep = stdout; 896 else 897 filep = outf; 898 899 fputs(output_buffer, filep); 900 fflush(filep); 901 902 outp = output_buffer; 903 } 904 void flush_output_stderr(void) 905 { 906 fputs(output_buffer, outf); 907 fflush(outf); 908 outp = output_buffer; 909 } 910 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 911 { 912 static int printed; 913 914 if (!printed || !summary_only) 915 print_header(); 916 917 if (topo.num_cpus > 1) 918 format_counters(&average.threads, &average.cores, 919 &average.packages); 920 921 printed = 1; 922 923 if (summary_only) 924 return; 925 926 for_all_cpus(format_counters, t, c, p); 927 } 928 929 #define DELTA_WRAP32(new, old) \ 930 if (new > old) { \ 931 old = new - old; \ 932 } else { \ 933 old = 0x100000000 + new - old; \ 934 } 935 936 int 937 delta_package(struct pkg_data *new, struct pkg_data *old) 938 { 939 int i; 940 struct msr_counter *mp; 941 942 if (do_skl_residency) { 943 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 944 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 945 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 946 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 947 } 948 old->pc2 = new->pc2 - old->pc2; 949 if (do_pc3) 950 old->pc3 = new->pc3 - old->pc3; 951 if (do_pc6) 952 old->pc6 = new->pc6 - old->pc6; 953 if (do_pc7) 954 old->pc7 = new->pc7 - old->pc7; 955 old->pc8 = new->pc8 - old->pc8; 956 old->pc9 = new->pc9 - old->pc9; 957 old->pc10 = new->pc10 - old->pc10; 958 old->pkg_temp_c = new->pkg_temp_c; 959 960 /* flag an error when rc6 counter resets/wraps */ 961 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 962 old->gfx_rc6_ms = -1; 963 else 964 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 965 966 old->gfx_mhz = new->gfx_mhz; 967 968 DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 969 DELTA_WRAP32(new->energy_cores, old->energy_cores); 970 DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 971 DELTA_WRAP32(new->energy_dram, old->energy_dram); 972 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 973 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 974 975 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 976 if (mp->format == FORMAT_RAW) 977 old->counter[i] = new->counter[i]; 978 else 979 old->counter[i] = new->counter[i] - old->counter[i]; 980 } 981 982 return 0; 983 } 984 985 void 986 delta_core(struct core_data *new, struct core_data *old) 987 { 988 int i; 989 struct msr_counter *mp; 990 991 old->c3 = new->c3 - old->c3; 992 old->c6 = new->c6 - old->c6; 993 old->c7 = new->c7 - old->c7; 994 old->core_temp_c = new->core_temp_c; 995 old->mc6_us = new->mc6_us - old->mc6_us; 996 997 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 998 if (mp->format == FORMAT_RAW) 999 old->counter[i] = new->counter[i]; 1000 else 1001 old->counter[i] = new->counter[i] - old->counter[i]; 1002 } 1003 } 1004 1005 /* 1006 * old = new - old 1007 */ 1008 int 1009 delta_thread(struct thread_data *new, struct thread_data *old, 1010 struct core_data *core_delta) 1011 { 1012 int i; 1013 struct msr_counter *mp; 1014 1015 old->tsc = new->tsc - old->tsc; 1016 1017 /* check for TSC < 1 Mcycles over interval */ 1018 if (old->tsc < (1000 * 1000)) 1019 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1020 "You can disable all c-states by booting with \"idle=poll\"\n" 1021 "or just the deep ones with \"processor.max_cstate=1\""); 1022 1023 old->c1 = new->c1 - old->c1; 1024 1025 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1026 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1027 old->aperf = new->aperf - old->aperf; 1028 old->mperf = new->mperf - old->mperf; 1029 } else { 1030 return -1; 1031 } 1032 } 1033 1034 1035 if (use_c1_residency_msr) { 1036 /* 1037 * Some models have a dedicated C1 residency MSR, 1038 * which should be more accurate than the derivation below. 1039 */ 1040 } else { 1041 /* 1042 * As counter collection is not atomic, 1043 * it is possible for mperf's non-halted cycles + idle states 1044 * to exceed TSC's all cycles: show c1 = 0% in that case. 1045 */ 1046 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc) 1047 old->c1 = 0; 1048 else { 1049 /* normal case, derive c1 */ 1050 old->c1 = old->tsc - old->mperf - core_delta->c3 1051 - core_delta->c6 - core_delta->c7; 1052 } 1053 } 1054 1055 if (old->mperf == 0) { 1056 if (debug > 1) 1057 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1058 old->mperf = 1; /* divide by 0 protection */ 1059 } 1060 1061 if (DO_BIC(BIC_IRQ)) 1062 old->irq_count = new->irq_count - old->irq_count; 1063 1064 if (DO_BIC(BIC_SMI)) 1065 old->smi_count = new->smi_count - old->smi_count; 1066 1067 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1068 if (mp->format == FORMAT_RAW) 1069 old->counter[i] = new->counter[i]; 1070 else 1071 old->counter[i] = new->counter[i] - old->counter[i]; 1072 } 1073 return 0; 1074 } 1075 1076 int delta_cpu(struct thread_data *t, struct core_data *c, 1077 struct pkg_data *p, struct thread_data *t2, 1078 struct core_data *c2, struct pkg_data *p2) 1079 { 1080 int retval = 0; 1081 1082 /* calculate core delta only for 1st thread in core */ 1083 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1084 delta_core(c, c2); 1085 1086 /* always calculate thread delta */ 1087 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1088 if (retval) 1089 return retval; 1090 1091 /* calculate package delta only for 1st core in package */ 1092 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1093 retval = delta_package(p, p2); 1094 1095 return retval; 1096 } 1097 1098 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1099 { 1100 int i; 1101 struct msr_counter *mp; 1102 1103 t->tsc = 0; 1104 t->aperf = 0; 1105 t->mperf = 0; 1106 t->c1 = 0; 1107 1108 t->irq_count = 0; 1109 t->smi_count = 0; 1110 1111 /* tells format_counters to dump all fields from this set */ 1112 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1113 1114 c->c3 = 0; 1115 c->c6 = 0; 1116 c->c7 = 0; 1117 c->mc6_us = 0; 1118 c->core_temp_c = 0; 1119 1120 p->pkg_wtd_core_c0 = 0; 1121 p->pkg_any_core_c0 = 0; 1122 p->pkg_any_gfxe_c0 = 0; 1123 p->pkg_both_core_gfxe_c0 = 0; 1124 1125 p->pc2 = 0; 1126 if (do_pc3) 1127 p->pc3 = 0; 1128 if (do_pc6) 1129 p->pc6 = 0; 1130 if (do_pc7) 1131 p->pc7 = 0; 1132 p->pc8 = 0; 1133 p->pc9 = 0; 1134 p->pc10 = 0; 1135 1136 p->energy_pkg = 0; 1137 p->energy_dram = 0; 1138 p->energy_cores = 0; 1139 p->energy_gfx = 0; 1140 p->rapl_pkg_perf_status = 0; 1141 p->rapl_dram_perf_status = 0; 1142 p->pkg_temp_c = 0; 1143 1144 p->gfx_rc6_ms = 0; 1145 p->gfx_mhz = 0; 1146 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1147 t->counter[i] = 0; 1148 1149 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1150 c->counter[i] = 0; 1151 1152 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1153 p->counter[i] = 0; 1154 } 1155 int sum_counters(struct thread_data *t, struct core_data *c, 1156 struct pkg_data *p) 1157 { 1158 int i; 1159 struct msr_counter *mp; 1160 1161 average.threads.tsc += t->tsc; 1162 average.threads.aperf += t->aperf; 1163 average.threads.mperf += t->mperf; 1164 average.threads.c1 += t->c1; 1165 1166 average.threads.irq_count += t->irq_count; 1167 average.threads.smi_count += t->smi_count; 1168 1169 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1170 if (mp->format == FORMAT_RAW) 1171 continue; 1172 average.threads.counter[i] += t->counter[i]; 1173 } 1174 1175 /* sum per-core values only for 1st thread in core */ 1176 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1177 return 0; 1178 1179 average.cores.c3 += c->c3; 1180 average.cores.c6 += c->c6; 1181 average.cores.c7 += c->c7; 1182 average.cores.mc6_us += c->mc6_us; 1183 1184 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1185 1186 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1187 if (mp->format == FORMAT_RAW) 1188 continue; 1189 average.cores.counter[i] += c->counter[i]; 1190 } 1191 1192 /* sum per-pkg values only for 1st core in pkg */ 1193 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1194 return 0; 1195 1196 if (do_skl_residency) { 1197 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1198 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1199 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1200 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1201 } 1202 1203 average.packages.pc2 += p->pc2; 1204 if (do_pc3) 1205 average.packages.pc3 += p->pc3; 1206 if (do_pc6) 1207 average.packages.pc6 += p->pc6; 1208 if (do_pc7) 1209 average.packages.pc7 += p->pc7; 1210 average.packages.pc8 += p->pc8; 1211 average.packages.pc9 += p->pc9; 1212 average.packages.pc10 += p->pc10; 1213 1214 average.packages.energy_pkg += p->energy_pkg; 1215 average.packages.energy_dram += p->energy_dram; 1216 average.packages.energy_cores += p->energy_cores; 1217 average.packages.energy_gfx += p->energy_gfx; 1218 1219 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1220 average.packages.gfx_mhz = p->gfx_mhz; 1221 1222 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1223 1224 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1225 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1226 1227 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1228 if (mp->format == FORMAT_RAW) 1229 continue; 1230 average.packages.counter[i] += p->counter[i]; 1231 } 1232 return 0; 1233 } 1234 /* 1235 * sum the counters for all cpus in the system 1236 * compute the weighted average 1237 */ 1238 void compute_average(struct thread_data *t, struct core_data *c, 1239 struct pkg_data *p) 1240 { 1241 int i; 1242 struct msr_counter *mp; 1243 1244 clear_counters(&average.threads, &average.cores, &average.packages); 1245 1246 for_all_cpus(sum_counters, t, c, p); 1247 1248 average.threads.tsc /= topo.num_cpus; 1249 average.threads.aperf /= topo.num_cpus; 1250 average.threads.mperf /= topo.num_cpus; 1251 average.threads.c1 /= topo.num_cpus; 1252 1253 average.cores.c3 /= topo.num_cores; 1254 average.cores.c6 /= topo.num_cores; 1255 average.cores.c7 /= topo.num_cores; 1256 average.cores.mc6_us /= topo.num_cores; 1257 1258 if (do_skl_residency) { 1259 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1260 average.packages.pkg_any_core_c0 /= topo.num_packages; 1261 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1262 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1263 } 1264 1265 average.packages.pc2 /= topo.num_packages; 1266 if (do_pc3) 1267 average.packages.pc3 /= topo.num_packages; 1268 if (do_pc6) 1269 average.packages.pc6 /= topo.num_packages; 1270 if (do_pc7) 1271 average.packages.pc7 /= topo.num_packages; 1272 1273 average.packages.pc8 /= topo.num_packages; 1274 average.packages.pc9 /= topo.num_packages; 1275 average.packages.pc10 /= topo.num_packages; 1276 1277 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1278 if (mp->format == FORMAT_RAW) 1279 continue; 1280 average.threads.counter[i] /= topo.num_cpus; 1281 } 1282 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1283 if (mp->format == FORMAT_RAW) 1284 continue; 1285 average.cores.counter[i] /= topo.num_cores; 1286 } 1287 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1288 if (mp->format == FORMAT_RAW) 1289 continue; 1290 average.packages.counter[i] /= topo.num_packages; 1291 } 1292 } 1293 1294 static unsigned long long rdtsc(void) 1295 { 1296 unsigned int low, high; 1297 1298 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1299 1300 return low | ((unsigned long long)high) << 32; 1301 } 1302 1303 /* 1304 * get_counters(...) 1305 * migrate to cpu 1306 * acquire and record local counters for that cpu 1307 */ 1308 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1309 { 1310 int cpu = t->cpu_id; 1311 unsigned long long msr; 1312 int aperf_mperf_retry_count = 0; 1313 struct msr_counter *mp; 1314 int i; 1315 1316 if (cpu_migrate(cpu)) { 1317 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1318 return -1; 1319 } 1320 1321 retry: 1322 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1323 1324 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1325 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1326 1327 /* 1328 * The TSC, APERF and MPERF must be read together for 1329 * APERF/MPERF and MPERF/TSC to give accurate results. 1330 * 1331 * Unfortunately, APERF and MPERF are read by 1332 * individual system call, so delays may occur 1333 * between them. If the time to read them 1334 * varies by a large amount, we re-read them. 1335 */ 1336 1337 /* 1338 * This initial dummy APERF read has been seen to 1339 * reduce jitter in the subsequent reads. 1340 */ 1341 1342 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1343 return -3; 1344 1345 t->tsc = rdtsc(); /* re-read close to APERF */ 1346 1347 tsc_before = t->tsc; 1348 1349 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1350 return -3; 1351 1352 tsc_between = rdtsc(); 1353 1354 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1355 return -4; 1356 1357 tsc_after = rdtsc(); 1358 1359 aperf_time = tsc_between - tsc_before; 1360 mperf_time = tsc_after - tsc_between; 1361 1362 /* 1363 * If the system call latency to read APERF and MPERF 1364 * differ by more than 2x, then try again. 1365 */ 1366 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1367 aperf_mperf_retry_count++; 1368 if (aperf_mperf_retry_count < 5) 1369 goto retry; 1370 else 1371 warnx("cpu%d jitter %lld %lld", 1372 cpu, aperf_time, mperf_time); 1373 } 1374 aperf_mperf_retry_count = 0; 1375 1376 t->aperf = t->aperf * aperf_mperf_multiplier; 1377 t->mperf = t->mperf * aperf_mperf_multiplier; 1378 } 1379 1380 if (DO_BIC(BIC_IRQ)) 1381 t->irq_count = irqs_per_cpu[cpu]; 1382 if (DO_BIC(BIC_SMI)) { 1383 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1384 return -5; 1385 t->smi_count = msr & 0xFFFFFFFF; 1386 } 1387 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 1388 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 1389 return -6; 1390 } 1391 1392 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1393 if (get_msr(cpu, mp->msr_num, &t->counter[i])) 1394 return -10; 1395 } 1396 1397 1398 /* collect core counters only for 1st thread in core */ 1399 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1400 return 0; 1401 1402 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) { 1403 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1404 return -6; 1405 } 1406 1407 if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) { 1408 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1409 return -7; 1410 } else if (do_knl_cstates) { 1411 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1412 return -7; 1413 } 1414 1415 if (DO_BIC(BIC_CPU_c7)) 1416 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1417 return -8; 1418 1419 if (DO_BIC(BIC_Mod_c6)) 1420 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 1421 return -8; 1422 1423 if (DO_BIC(BIC_CoreTmp)) { 1424 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1425 return -9; 1426 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1427 } 1428 1429 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1430 if (get_msr(cpu, mp->msr_num, &c->counter[i])) 1431 return -10; 1432 } 1433 1434 /* collect package counters only for 1st core in package */ 1435 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1436 return 0; 1437 1438 if (do_skl_residency) { 1439 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 1440 return -10; 1441 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 1442 return -11; 1443 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 1444 return -12; 1445 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 1446 return -13; 1447 } 1448 if (do_pc3) 1449 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 1450 return -9; 1451 if (do_pc6) { 1452 if (do_slm_cstates) { 1453 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 1454 return -10; 1455 } else { 1456 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 1457 return -10; 1458 } 1459 } 1460 1461 if (do_pc2) 1462 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 1463 return -11; 1464 if (do_pc7) 1465 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 1466 return -12; 1467 if (do_c8_c9_c10) { 1468 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 1469 return -13; 1470 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 1471 return -13; 1472 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 1473 return -13; 1474 } 1475 if (do_rapl & RAPL_PKG) { 1476 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 1477 return -13; 1478 p->energy_pkg = msr & 0xFFFFFFFF; 1479 } 1480 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 1481 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 1482 return -14; 1483 p->energy_cores = msr & 0xFFFFFFFF; 1484 } 1485 if (do_rapl & RAPL_DRAM) { 1486 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 1487 return -15; 1488 p->energy_dram = msr & 0xFFFFFFFF; 1489 } 1490 if (do_rapl & RAPL_GFX) { 1491 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 1492 return -16; 1493 p->energy_gfx = msr & 0xFFFFFFFF; 1494 } 1495 if (do_rapl & RAPL_PKG_PERF_STATUS) { 1496 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 1497 return -16; 1498 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 1499 } 1500 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 1501 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 1502 return -16; 1503 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 1504 } 1505 if (DO_BIC(BIC_PkgTmp)) { 1506 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 1507 return -17; 1508 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1509 } 1510 1511 if (DO_BIC(BIC_GFX_rc6)) 1512 p->gfx_rc6_ms = gfx_cur_rc6_ms; 1513 1514 if (DO_BIC(BIC_GFXMHz)) 1515 p->gfx_mhz = gfx_cur_mhz; 1516 1517 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1518 if (get_msr(cpu, mp->msr_num, &p->counter[i])) 1519 return -10; 1520 } 1521 1522 return 0; 1523 } 1524 1525 /* 1526 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 1527 * If you change the values, note they are used both in comparisons 1528 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 1529 */ 1530 1531 #define PCLUKN 0 /* Unknown */ 1532 #define PCLRSV 1 /* Reserved */ 1533 #define PCL__0 2 /* PC0 */ 1534 #define PCL__1 3 /* PC1 */ 1535 #define PCL__2 4 /* PC2 */ 1536 #define PCL__3 5 /* PC3 */ 1537 #define PCL__4 6 /* PC4 */ 1538 #define PCL__6 7 /* PC6 */ 1539 #define PCL_6N 8 /* PC6 No Retention */ 1540 #define PCL_6R 9 /* PC6 Retention */ 1541 #define PCL__7 10 /* PC7 */ 1542 #define PCL_7S 11 /* PC7 Shrink */ 1543 #define PCL__8 12 /* PC8 */ 1544 #define PCL__9 13 /* PC9 */ 1545 #define PCLUNL 14 /* Unlimited */ 1546 1547 int pkg_cstate_limit = PCLUKN; 1548 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 1549 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"}; 1550 1551 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1552 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1553 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1554 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7}; 1555 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1556 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1557 int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1558 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1559 1560 1561 static void 1562 calculate_tsc_tweak() 1563 { 1564 tsc_tweak = base_hz / tsc_hz; 1565 } 1566 1567 static void 1568 dump_nhm_platform_info(void) 1569 { 1570 unsigned long long msr; 1571 unsigned int ratio; 1572 1573 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 1574 1575 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 1576 1577 ratio = (msr >> 40) & 0xFF; 1578 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", 1579 ratio, bclk, ratio * bclk); 1580 1581 ratio = (msr >> 8) & 0xFF; 1582 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 1583 ratio, bclk, ratio * bclk); 1584 1585 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 1586 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 1587 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 1588 1589 return; 1590 } 1591 1592 static void 1593 dump_hsw_turbo_ratio_limits(void) 1594 { 1595 unsigned long long msr; 1596 unsigned int ratio; 1597 1598 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 1599 1600 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 1601 1602 ratio = (msr >> 8) & 0xFF; 1603 if (ratio) 1604 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", 1605 ratio, bclk, ratio * bclk); 1606 1607 ratio = (msr >> 0) & 0xFF; 1608 if (ratio) 1609 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", 1610 ratio, bclk, ratio * bclk); 1611 return; 1612 } 1613 1614 static void 1615 dump_ivt_turbo_ratio_limits(void) 1616 { 1617 unsigned long long msr; 1618 unsigned int ratio; 1619 1620 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 1621 1622 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 1623 1624 ratio = (msr >> 56) & 0xFF; 1625 if (ratio) 1626 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", 1627 ratio, bclk, ratio * bclk); 1628 1629 ratio = (msr >> 48) & 0xFF; 1630 if (ratio) 1631 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", 1632 ratio, bclk, ratio * bclk); 1633 1634 ratio = (msr >> 40) & 0xFF; 1635 if (ratio) 1636 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", 1637 ratio, bclk, ratio * bclk); 1638 1639 ratio = (msr >> 32) & 0xFF; 1640 if (ratio) 1641 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", 1642 ratio, bclk, ratio * bclk); 1643 1644 ratio = (msr >> 24) & 0xFF; 1645 if (ratio) 1646 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", 1647 ratio, bclk, ratio * bclk); 1648 1649 ratio = (msr >> 16) & 0xFF; 1650 if (ratio) 1651 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", 1652 ratio, bclk, ratio * bclk); 1653 1654 ratio = (msr >> 8) & 0xFF; 1655 if (ratio) 1656 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", 1657 ratio, bclk, ratio * bclk); 1658 1659 ratio = (msr >> 0) & 0xFF; 1660 if (ratio) 1661 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", 1662 ratio, bclk, ratio * bclk); 1663 return; 1664 } 1665 1666 static void 1667 dump_nhm_turbo_ratio_limits(void) 1668 { 1669 unsigned long long msr; 1670 unsigned int ratio; 1671 1672 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 1673 1674 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 1675 1676 ratio = (msr >> 56) & 0xFF; 1677 if (ratio) 1678 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 8 active cores\n", 1679 ratio, bclk, ratio * bclk); 1680 1681 ratio = (msr >> 48) & 0xFF; 1682 if (ratio) 1683 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 7 active cores\n", 1684 ratio, bclk, ratio * bclk); 1685 1686 ratio = (msr >> 40) & 0xFF; 1687 if (ratio) 1688 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 6 active cores\n", 1689 ratio, bclk, ratio * bclk); 1690 1691 ratio = (msr >> 32) & 0xFF; 1692 if (ratio) 1693 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 5 active cores\n", 1694 ratio, bclk, ratio * bclk); 1695 1696 ratio = (msr >> 24) & 0xFF; 1697 if (ratio) 1698 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", 1699 ratio, bclk, ratio * bclk); 1700 1701 ratio = (msr >> 16) & 0xFF; 1702 if (ratio) 1703 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", 1704 ratio, bclk, ratio * bclk); 1705 1706 ratio = (msr >> 8) & 0xFF; 1707 if (ratio) 1708 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", 1709 ratio, bclk, ratio * bclk); 1710 1711 ratio = (msr >> 0) & 0xFF; 1712 if (ratio) 1713 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active cores\n", 1714 ratio, bclk, ratio * bclk); 1715 return; 1716 } 1717 1718 static void 1719 dump_atom_turbo_ratio_limits(void) 1720 { 1721 unsigned long long msr; 1722 unsigned int ratio; 1723 1724 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 1725 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 1726 1727 ratio = (msr >> 0) & 0x3F; 1728 if (ratio) 1729 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", 1730 ratio, bclk, ratio * bclk); 1731 1732 ratio = (msr >> 8) & 0x3F; 1733 if (ratio) 1734 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", 1735 ratio, bclk, ratio * bclk); 1736 1737 ratio = (msr >> 16) & 0x3F; 1738 if (ratio) 1739 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 1740 ratio, bclk, ratio * bclk); 1741 1742 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 1743 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 1744 1745 ratio = (msr >> 24) & 0x3F; 1746 if (ratio) 1747 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", 1748 ratio, bclk, ratio * bclk); 1749 1750 ratio = (msr >> 16) & 0x3F; 1751 if (ratio) 1752 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", 1753 ratio, bclk, ratio * bclk); 1754 1755 ratio = (msr >> 8) & 0x3F; 1756 if (ratio) 1757 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", 1758 ratio, bclk, ratio * bclk); 1759 1760 ratio = (msr >> 0) & 0x3F; 1761 if (ratio) 1762 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", 1763 ratio, bclk, ratio * bclk); 1764 } 1765 1766 static void 1767 dump_knl_turbo_ratio_limits(void) 1768 { 1769 const unsigned int buckets_no = 7; 1770 1771 unsigned long long msr; 1772 int delta_cores, delta_ratio; 1773 int i, b_nr; 1774 unsigned int cores[buckets_no]; 1775 unsigned int ratio[buckets_no]; 1776 1777 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 1778 1779 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 1780 base_cpu, msr); 1781 1782 /** 1783 * Turbo encoding in KNL is as follows: 1784 * [0] -- Reserved 1785 * [7:1] -- Base value of number of active cores of bucket 1. 1786 * [15:8] -- Base value of freq ratio of bucket 1. 1787 * [20:16] -- +ve delta of number of active cores of bucket 2. 1788 * i.e. active cores of bucket 2 = 1789 * active cores of bucket 1 + delta 1790 * [23:21] -- Negative delta of freq ratio of bucket 2. 1791 * i.e. freq ratio of bucket 2 = 1792 * freq ratio of bucket 1 - delta 1793 * [28:24]-- +ve delta of number of active cores of bucket 3. 1794 * [31:29]-- -ve delta of freq ratio of bucket 3. 1795 * [36:32]-- +ve delta of number of active cores of bucket 4. 1796 * [39:37]-- -ve delta of freq ratio of bucket 4. 1797 * [44:40]-- +ve delta of number of active cores of bucket 5. 1798 * [47:45]-- -ve delta of freq ratio of bucket 5. 1799 * [52:48]-- +ve delta of number of active cores of bucket 6. 1800 * [55:53]-- -ve delta of freq ratio of bucket 6. 1801 * [60:56]-- +ve delta of number of active cores of bucket 7. 1802 * [63:61]-- -ve delta of freq ratio of bucket 7. 1803 */ 1804 1805 b_nr = 0; 1806 cores[b_nr] = (msr & 0xFF) >> 1; 1807 ratio[b_nr] = (msr >> 8) & 0xFF; 1808 1809 for (i = 16; i < 64; i += 8) { 1810 delta_cores = (msr >> i) & 0x1F; 1811 delta_ratio = (msr >> (i + 5)) & 0x7; 1812 1813 cores[b_nr + 1] = cores[b_nr] + delta_cores; 1814 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 1815 b_nr++; 1816 } 1817 1818 for (i = buckets_no - 1; i >= 0; i--) 1819 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 1820 fprintf(outf, 1821 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 1822 ratio[i], bclk, ratio[i] * bclk, cores[i]); 1823 } 1824 1825 static void 1826 dump_nhm_cst_cfg(void) 1827 { 1828 unsigned long long msr; 1829 1830 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 1831 1832 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 1833 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 1834 1835 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 1836 1837 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n", 1838 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 1839 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 1840 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 1841 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 1842 (msr & (1 << 15)) ? "" : "UN", 1843 (unsigned int)msr & 0xF, 1844 pkg_cstate_limit_strings[pkg_cstate_limit]); 1845 return; 1846 } 1847 1848 static void 1849 dump_config_tdp(void) 1850 { 1851 unsigned long long msr; 1852 1853 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 1854 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 1855 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 1856 1857 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 1858 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 1859 if (msr) { 1860 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 1861 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 1862 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 1863 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 1864 } 1865 fprintf(outf, ")\n"); 1866 1867 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 1868 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 1869 if (msr) { 1870 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 1871 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 1872 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 1873 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 1874 } 1875 fprintf(outf, ")\n"); 1876 1877 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 1878 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 1879 if ((msr) & 0x3) 1880 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 1881 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 1882 fprintf(outf, ")\n"); 1883 1884 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 1885 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 1886 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 1887 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 1888 fprintf(outf, ")\n"); 1889 } 1890 1891 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 1892 1893 void print_irtl(void) 1894 { 1895 unsigned long long msr; 1896 1897 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 1898 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 1899 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1900 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1901 1902 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 1903 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 1904 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1905 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1906 1907 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 1908 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 1909 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1910 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1911 1912 if (!do_irtl_hsw) 1913 return; 1914 1915 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 1916 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 1917 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1918 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1919 1920 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 1921 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 1922 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1923 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1924 1925 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 1926 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 1927 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1928 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1929 1930 } 1931 void free_fd_percpu(void) 1932 { 1933 int i; 1934 1935 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 1936 if (fd_percpu[i] != 0) 1937 close(fd_percpu[i]); 1938 } 1939 1940 free(fd_percpu); 1941 } 1942 1943 void free_all_buffers(void) 1944 { 1945 CPU_FREE(cpu_present_set); 1946 cpu_present_set = NULL; 1947 cpu_present_setsize = 0; 1948 1949 CPU_FREE(cpu_affinity_set); 1950 cpu_affinity_set = NULL; 1951 cpu_affinity_setsize = 0; 1952 1953 free(thread_even); 1954 free(core_even); 1955 free(package_even); 1956 1957 thread_even = NULL; 1958 core_even = NULL; 1959 package_even = NULL; 1960 1961 free(thread_odd); 1962 free(core_odd); 1963 free(package_odd); 1964 1965 thread_odd = NULL; 1966 core_odd = NULL; 1967 package_odd = NULL; 1968 1969 free(output_buffer); 1970 output_buffer = NULL; 1971 outp = NULL; 1972 1973 free_fd_percpu(); 1974 1975 free(irq_column_2_cpu); 1976 free(irqs_per_cpu); 1977 } 1978 1979 /* 1980 * Open a file, and exit on failure 1981 */ 1982 FILE *fopen_or_die(const char *path, const char *mode) 1983 { 1984 FILE *filep = fopen(path, mode); 1985 if (!filep) 1986 err(1, "%s: open failed", path); 1987 return filep; 1988 } 1989 1990 /* 1991 * Parse a file containing a single int. 1992 */ 1993 int parse_int_file(const char *fmt, ...) 1994 { 1995 va_list args; 1996 char path[PATH_MAX]; 1997 FILE *filep; 1998 int value; 1999 2000 va_start(args, fmt); 2001 vsnprintf(path, sizeof(path), fmt, args); 2002 va_end(args); 2003 filep = fopen_or_die(path, "r"); 2004 if (fscanf(filep, "%d", &value) != 1) 2005 err(1, "%s: failed to parse number from file", path); 2006 fclose(filep); 2007 return value; 2008 } 2009 2010 /* 2011 * get_cpu_position_in_core(cpu) 2012 * return the position of the CPU among its HT siblings in the core 2013 * return -1 if the sibling is not in list 2014 */ 2015 int get_cpu_position_in_core(int cpu) 2016 { 2017 char path[64]; 2018 FILE *filep; 2019 int this_cpu; 2020 char character; 2021 int i; 2022 2023 sprintf(path, 2024 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", 2025 cpu); 2026 filep = fopen(path, "r"); 2027 if (filep == NULL) { 2028 perror(path); 2029 exit(1); 2030 } 2031 2032 for (i = 0; i < topo.num_threads_per_core; i++) { 2033 fscanf(filep, "%d", &this_cpu); 2034 if (this_cpu == cpu) { 2035 fclose(filep); 2036 return i; 2037 } 2038 2039 /* Account for no separator after last thread*/ 2040 if (i != (topo.num_threads_per_core - 1)) 2041 fscanf(filep, "%c", &character); 2042 } 2043 2044 fclose(filep); 2045 return -1; 2046 } 2047 2048 /* 2049 * cpu_is_first_core_in_package(cpu) 2050 * return 1 if given CPU is 1st core in package 2051 */ 2052 int cpu_is_first_core_in_package(int cpu) 2053 { 2054 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2055 } 2056 2057 int get_physical_package_id(int cpu) 2058 { 2059 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2060 } 2061 2062 int get_core_id(int cpu) 2063 { 2064 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2065 } 2066 2067 int get_num_ht_siblings(int cpu) 2068 { 2069 char path[80]; 2070 FILE *filep; 2071 int sib1; 2072 int matches = 0; 2073 char character; 2074 char str[100]; 2075 char *ch; 2076 2077 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu); 2078 filep = fopen_or_die(path, "r"); 2079 2080 /* 2081 * file format: 2082 * A ',' separated or '-' separated set of numbers 2083 * (eg 1-2 or 1,3,4,5) 2084 */ 2085 fscanf(filep, "%d%c\n", &sib1, &character); 2086 fseek(filep, 0, SEEK_SET); 2087 fgets(str, 100, filep); 2088 ch = strchr(str, character); 2089 while (ch != NULL) { 2090 matches++; 2091 ch = strchr(ch+1, character); 2092 } 2093 2094 fclose(filep); 2095 return matches+1; 2096 } 2097 2098 /* 2099 * run func(thread, core, package) in topology order 2100 * skip non-present cpus 2101 */ 2102 2103 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 2104 struct pkg_data *, struct thread_data *, struct core_data *, 2105 struct pkg_data *), struct thread_data *thread_base, 2106 struct core_data *core_base, struct pkg_data *pkg_base, 2107 struct thread_data *thread_base2, struct core_data *core_base2, 2108 struct pkg_data *pkg_base2) 2109 { 2110 int retval, pkg_no, core_no, thread_no; 2111 2112 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2113 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { 2114 for (thread_no = 0; thread_no < 2115 topo.num_threads_per_core; ++thread_no) { 2116 struct thread_data *t, *t2; 2117 struct core_data *c, *c2; 2118 struct pkg_data *p, *p2; 2119 2120 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); 2121 2122 if (cpu_is_not_present(t->cpu_id)) 2123 continue; 2124 2125 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no); 2126 2127 c = GET_CORE(core_base, core_no, pkg_no); 2128 c2 = GET_CORE(core_base2, core_no, pkg_no); 2129 2130 p = GET_PKG(pkg_base, pkg_no); 2131 p2 = GET_PKG(pkg_base2, pkg_no); 2132 2133 retval = func(t, c, p, t2, c2, p2); 2134 if (retval) 2135 return retval; 2136 } 2137 } 2138 } 2139 return 0; 2140 } 2141 2142 /* 2143 * run func(cpu) on every cpu in /proc/stat 2144 * return max_cpu number 2145 */ 2146 int for_all_proc_cpus(int (func)(int)) 2147 { 2148 FILE *fp; 2149 int cpu_num; 2150 int retval; 2151 2152 fp = fopen_or_die(proc_stat, "r"); 2153 2154 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 2155 if (retval != 0) 2156 err(1, "%s: failed to parse format", proc_stat); 2157 2158 while (1) { 2159 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 2160 if (retval != 1) 2161 break; 2162 2163 retval = func(cpu_num); 2164 if (retval) { 2165 fclose(fp); 2166 return(retval); 2167 } 2168 } 2169 fclose(fp); 2170 return 0; 2171 } 2172 2173 void re_initialize(void) 2174 { 2175 free_all_buffers(); 2176 setup_all_buffers(); 2177 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2178 } 2179 2180 2181 /* 2182 * count_cpus() 2183 * remember the last one seen, it will be the max 2184 */ 2185 int count_cpus(int cpu) 2186 { 2187 if (topo.max_cpu_num < cpu) 2188 topo.max_cpu_num = cpu; 2189 2190 topo.num_cpus += 1; 2191 return 0; 2192 } 2193 int mark_cpu_present(int cpu) 2194 { 2195 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 2196 return 0; 2197 } 2198 2199 /* 2200 * snapshot_proc_interrupts() 2201 * 2202 * read and record summary of /proc/interrupts 2203 * 2204 * return 1 if config change requires a restart, else return 0 2205 */ 2206 int snapshot_proc_interrupts(void) 2207 { 2208 static FILE *fp; 2209 int column, retval; 2210 2211 if (fp == NULL) 2212 fp = fopen_or_die("/proc/interrupts", "r"); 2213 else 2214 rewind(fp); 2215 2216 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 2217 for (column = 0; column < topo.num_cpus; ++column) { 2218 int cpu_number; 2219 2220 retval = fscanf(fp, " CPU%d", &cpu_number); 2221 if (retval != 1) 2222 break; 2223 2224 if (cpu_number > topo.max_cpu_num) { 2225 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 2226 return 1; 2227 } 2228 2229 irq_column_2_cpu[column] = cpu_number; 2230 irqs_per_cpu[cpu_number] = 0; 2231 } 2232 2233 /* read /proc/interrupt count lines and sum up irqs per cpu */ 2234 while (1) { 2235 int column; 2236 char buf[64]; 2237 2238 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 2239 if (retval != 1) 2240 break; 2241 2242 /* read the count per cpu */ 2243 for (column = 0; column < topo.num_cpus; ++column) { 2244 2245 int cpu_number, irq_count; 2246 2247 retval = fscanf(fp, " %d", &irq_count); 2248 if (retval != 1) 2249 break; 2250 2251 cpu_number = irq_column_2_cpu[column]; 2252 irqs_per_cpu[cpu_number] += irq_count; 2253 2254 } 2255 2256 while (getc(fp) != '\n') 2257 ; /* flush interrupt description */ 2258 2259 } 2260 return 0; 2261 } 2262 /* 2263 * snapshot_gfx_rc6_ms() 2264 * 2265 * record snapshot of 2266 * /sys/class/drm/card0/power/rc6_residency_ms 2267 * 2268 * return 1 if config change requires a restart, else return 0 2269 */ 2270 int snapshot_gfx_rc6_ms(void) 2271 { 2272 FILE *fp; 2273 int retval; 2274 2275 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 2276 2277 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 2278 if (retval != 1) 2279 err(1, "GFX rc6"); 2280 2281 fclose(fp); 2282 2283 return 0; 2284 } 2285 /* 2286 * snapshot_gfx_mhz() 2287 * 2288 * record snapshot of 2289 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 2290 * 2291 * return 1 if config change requires a restart, else return 0 2292 */ 2293 int snapshot_gfx_mhz(void) 2294 { 2295 static FILE *fp; 2296 int retval; 2297 2298 if (fp == NULL) 2299 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 2300 else 2301 rewind(fp); 2302 2303 retval = fscanf(fp, "%d", &gfx_cur_mhz); 2304 if (retval != 1) 2305 err(1, "GFX MHz"); 2306 2307 return 0; 2308 } 2309 2310 /* 2311 * snapshot /proc and /sys files 2312 * 2313 * return 1 if configuration restart needed, else return 0 2314 */ 2315 int snapshot_proc_sysfs_files(void) 2316 { 2317 if (snapshot_proc_interrupts()) 2318 return 1; 2319 2320 if (DO_BIC(BIC_GFX_rc6)) 2321 snapshot_gfx_rc6_ms(); 2322 2323 if (DO_BIC(BIC_GFXMHz)) 2324 snapshot_gfx_mhz(); 2325 2326 return 0; 2327 } 2328 2329 void turbostat_loop() 2330 { 2331 int retval; 2332 int restarted = 0; 2333 2334 restart: 2335 restarted++; 2336 2337 snapshot_proc_sysfs_files(); 2338 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2339 if (retval < -1) { 2340 exit(retval); 2341 } else if (retval == -1) { 2342 if (restarted > 1) { 2343 exit(retval); 2344 } 2345 re_initialize(); 2346 goto restart; 2347 } 2348 restarted = 0; 2349 gettimeofday(&tv_even, (struct timezone *)NULL); 2350 2351 while (1) { 2352 if (for_all_proc_cpus(cpu_is_not_present)) { 2353 re_initialize(); 2354 goto restart; 2355 } 2356 nanosleep(&interval_ts, NULL); 2357 if (snapshot_proc_sysfs_files()) 2358 goto restart; 2359 retval = for_all_cpus(get_counters, ODD_COUNTERS); 2360 if (retval < -1) { 2361 exit(retval); 2362 } else if (retval == -1) { 2363 re_initialize(); 2364 goto restart; 2365 } 2366 gettimeofday(&tv_odd, (struct timezone *)NULL); 2367 timersub(&tv_odd, &tv_even, &tv_delta); 2368 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 2369 re_initialize(); 2370 goto restart; 2371 } 2372 compute_average(EVEN_COUNTERS); 2373 format_all_counters(EVEN_COUNTERS); 2374 flush_output_stdout(); 2375 nanosleep(&interval_ts, NULL); 2376 if (snapshot_proc_sysfs_files()) 2377 goto restart; 2378 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2379 if (retval < -1) { 2380 exit(retval); 2381 } else if (retval == -1) { 2382 re_initialize(); 2383 goto restart; 2384 } 2385 gettimeofday(&tv_even, (struct timezone *)NULL); 2386 timersub(&tv_even, &tv_odd, &tv_delta); 2387 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 2388 re_initialize(); 2389 goto restart; 2390 } 2391 compute_average(ODD_COUNTERS); 2392 format_all_counters(ODD_COUNTERS); 2393 flush_output_stdout(); 2394 } 2395 } 2396 2397 void check_dev_msr() 2398 { 2399 struct stat sb; 2400 char pathname[32]; 2401 2402 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 2403 if (stat(pathname, &sb)) 2404 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 2405 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 2406 } 2407 2408 void check_permissions() 2409 { 2410 struct __user_cap_header_struct cap_header_data; 2411 cap_user_header_t cap_header = &cap_header_data; 2412 struct __user_cap_data_struct cap_data_data; 2413 cap_user_data_t cap_data = &cap_data_data; 2414 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); 2415 int do_exit = 0; 2416 char pathname[32]; 2417 2418 /* check for CAP_SYS_RAWIO */ 2419 cap_header->pid = getpid(); 2420 cap_header->version = _LINUX_CAPABILITY_VERSION; 2421 if (capget(cap_header, cap_data) < 0) 2422 err(-6, "capget(2) failed"); 2423 2424 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { 2425 do_exit++; 2426 warnx("capget(CAP_SYS_RAWIO) failed," 2427 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 2428 } 2429 2430 /* test file permissions */ 2431 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 2432 if (euidaccess(pathname, R_OK)) { 2433 do_exit++; 2434 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 2435 } 2436 2437 /* if all else fails, thell them to be root */ 2438 if (do_exit) 2439 if (getuid() != 0) 2440 warnx("... or simply run as root"); 2441 2442 if (do_exit) 2443 exit(-6); 2444 } 2445 2446 /* 2447 * NHM adds support for additional MSRs: 2448 * 2449 * MSR_SMI_COUNT 0x00000034 2450 * 2451 * MSR_PLATFORM_INFO 0x000000ce 2452 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 2453 * 2454 * MSR_MISC_PWR_MGMT 0x000001aa 2455 * 2456 * MSR_PKG_C3_RESIDENCY 0x000003f8 2457 * MSR_PKG_C6_RESIDENCY 0x000003f9 2458 * MSR_CORE_C3_RESIDENCY 0x000003fc 2459 * MSR_CORE_C6_RESIDENCY 0x000003fd 2460 * 2461 * Side effect: 2462 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 2463 * sets has_misc_feature_control 2464 */ 2465 int probe_nhm_msrs(unsigned int family, unsigned int model) 2466 { 2467 unsigned long long msr; 2468 unsigned int base_ratio; 2469 int *pkg_cstate_limits; 2470 2471 if (!genuine_intel) 2472 return 0; 2473 2474 if (family != 6) 2475 return 0; 2476 2477 bclk = discover_bclk(family, model); 2478 2479 switch (model) { 2480 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 2481 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 2482 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 2483 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 2484 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 2485 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 2486 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 2487 pkg_cstate_limits = nhm_pkg_cstate_limits; 2488 break; 2489 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 2490 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 2491 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 2492 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 2493 pkg_cstate_limits = snb_pkg_cstate_limits; 2494 has_misc_feature_control = 1; 2495 break; 2496 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 2497 case INTEL_FAM6_HASWELL_X: /* HSX */ 2498 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 2499 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 2500 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 2501 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 2502 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2503 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2504 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 2505 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 2506 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 2507 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 2508 pkg_cstate_limits = hsw_pkg_cstate_limits; 2509 has_misc_feature_control = 1; 2510 break; 2511 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 2512 pkg_cstate_limits = skx_pkg_cstate_limits; 2513 has_misc_feature_control = 1; 2514 break; 2515 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 2516 no_MSR_MISC_PWR_MGMT = 1; 2517 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 2518 pkg_cstate_limits = slv_pkg_cstate_limits; 2519 break; 2520 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 2521 pkg_cstate_limits = amt_pkg_cstate_limits; 2522 no_MSR_MISC_PWR_MGMT = 1; 2523 break; 2524 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 2525 case INTEL_FAM6_XEON_PHI_KNM: 2526 pkg_cstate_limits = phi_pkg_cstate_limits; 2527 break; 2528 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 2529 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 2530 pkg_cstate_limits = bxt_pkg_cstate_limits; 2531 break; 2532 default: 2533 return 0; 2534 } 2535 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2536 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 2537 2538 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2539 base_ratio = (msr >> 8) & 0xFF; 2540 2541 base_hz = base_ratio * bclk * 1000000; 2542 has_base_hz = 1; 2543 return 1; 2544 } 2545 /* 2546 * SLV client has supporet for unique MSRs: 2547 * 2548 * MSR_CC6_DEMOTION_POLICY_CONFIG 2549 * MSR_MC6_DEMOTION_POLICY_CONFIG 2550 */ 2551 2552 int has_slv_msrs(unsigned int family, unsigned int model) 2553 { 2554 if (!genuine_intel) 2555 return 0; 2556 2557 switch (model) { 2558 case INTEL_FAM6_ATOM_SILVERMONT1: 2559 case INTEL_FAM6_ATOM_MERRIFIELD: 2560 case INTEL_FAM6_ATOM_MOOREFIELD: 2561 return 1; 2562 } 2563 return 0; 2564 } 2565 2566 int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model) 2567 { 2568 if (has_slv_msrs(family, model)) 2569 return 0; 2570 2571 switch (model) { 2572 /* Nehalem compatible, but do not include turbo-ratio limit support */ 2573 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 2574 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 2575 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 2576 case INTEL_FAM6_XEON_PHI_KNM: 2577 return 0; 2578 default: 2579 return 1; 2580 } 2581 } 2582 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 2583 { 2584 if (has_slv_msrs(family, model)) 2585 return 1; 2586 2587 return 0; 2588 } 2589 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 2590 { 2591 if (!genuine_intel) 2592 return 0; 2593 2594 if (family != 6) 2595 return 0; 2596 2597 switch (model) { 2598 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 2599 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 2600 return 1; 2601 default: 2602 return 0; 2603 } 2604 } 2605 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 2606 { 2607 if (!genuine_intel) 2608 return 0; 2609 2610 if (family != 6) 2611 return 0; 2612 2613 switch (model) { 2614 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 2615 return 1; 2616 default: 2617 return 0; 2618 } 2619 } 2620 2621 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 2622 { 2623 if (!genuine_intel) 2624 return 0; 2625 2626 if (family != 6) 2627 return 0; 2628 2629 switch (model) { 2630 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 2631 case INTEL_FAM6_XEON_PHI_KNM: 2632 return 1; 2633 default: 2634 return 0; 2635 } 2636 } 2637 int has_config_tdp(unsigned int family, unsigned int model) 2638 { 2639 if (!genuine_intel) 2640 return 0; 2641 2642 if (family != 6) 2643 return 0; 2644 2645 switch (model) { 2646 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 2647 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 2648 case INTEL_FAM6_HASWELL_X: /* HSX */ 2649 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 2650 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 2651 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 2652 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 2653 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2654 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2655 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 2656 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 2657 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 2658 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 2659 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 2660 2661 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 2662 case INTEL_FAM6_XEON_PHI_KNM: 2663 return 1; 2664 default: 2665 return 0; 2666 } 2667 } 2668 2669 static void 2670 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 2671 { 2672 if (!do_nhm_platform_info) 2673 return; 2674 2675 dump_nhm_platform_info(); 2676 2677 if (has_hsw_turbo_ratio_limit(family, model)) 2678 dump_hsw_turbo_ratio_limits(); 2679 2680 if (has_ivt_turbo_ratio_limit(family, model)) 2681 dump_ivt_turbo_ratio_limits(); 2682 2683 if (has_nhm_turbo_ratio_limit(family, model)) 2684 dump_nhm_turbo_ratio_limits(); 2685 2686 if (has_atom_turbo_ratio_limit(family, model)) 2687 dump_atom_turbo_ratio_limits(); 2688 2689 if (has_knl_turbo_ratio_limit(family, model)) 2690 dump_knl_turbo_ratio_limits(); 2691 2692 if (has_config_tdp(family, model)) 2693 dump_config_tdp(); 2694 2695 dump_nhm_cst_cfg(); 2696 } 2697 2698 2699 /* 2700 * print_epb() 2701 * Decode the ENERGY_PERF_BIAS MSR 2702 */ 2703 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2704 { 2705 unsigned long long msr; 2706 char *epb_string; 2707 int cpu; 2708 2709 if (!has_epb) 2710 return 0; 2711 2712 cpu = t->cpu_id; 2713 2714 /* EPB is per-package */ 2715 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2716 return 0; 2717 2718 if (cpu_migrate(cpu)) { 2719 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2720 return -1; 2721 } 2722 2723 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) 2724 return 0; 2725 2726 switch (msr & 0xF) { 2727 case ENERGY_PERF_BIAS_PERFORMANCE: 2728 epb_string = "performance"; 2729 break; 2730 case ENERGY_PERF_BIAS_NORMAL: 2731 epb_string = "balanced"; 2732 break; 2733 case ENERGY_PERF_BIAS_POWERSAVE: 2734 epb_string = "powersave"; 2735 break; 2736 default: 2737 epb_string = "custom"; 2738 break; 2739 } 2740 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); 2741 2742 return 0; 2743 } 2744 /* 2745 * print_hwp() 2746 * Decode the MSR_HWP_CAPABILITIES 2747 */ 2748 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2749 { 2750 unsigned long long msr; 2751 int cpu; 2752 2753 if (!has_hwp) 2754 return 0; 2755 2756 cpu = t->cpu_id; 2757 2758 /* MSR_HWP_CAPABILITIES is per-package */ 2759 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2760 return 0; 2761 2762 if (cpu_migrate(cpu)) { 2763 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2764 return -1; 2765 } 2766 2767 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 2768 return 0; 2769 2770 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 2771 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 2772 2773 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 2774 if ((msr & (1 << 0)) == 0) 2775 return 0; 2776 2777 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 2778 return 0; 2779 2780 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 2781 "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n", 2782 cpu, msr, 2783 (unsigned int)HWP_HIGHEST_PERF(msr), 2784 (unsigned int)HWP_GUARANTEED_PERF(msr), 2785 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 2786 (unsigned int)HWP_LOWEST_PERF(msr)); 2787 2788 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 2789 return 0; 2790 2791 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 2792 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n", 2793 cpu, msr, 2794 (unsigned int)(((msr) >> 0) & 0xff), 2795 (unsigned int)(((msr) >> 8) & 0xff), 2796 (unsigned int)(((msr) >> 16) & 0xff), 2797 (unsigned int)(((msr) >> 24) & 0xff), 2798 (unsigned int)(((msr) >> 32) & 0xff3), 2799 (unsigned int)(((msr) >> 42) & 0x1)); 2800 2801 if (has_hwp_pkg) { 2802 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 2803 return 0; 2804 2805 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 2806 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n", 2807 cpu, msr, 2808 (unsigned int)(((msr) >> 0) & 0xff), 2809 (unsigned int)(((msr) >> 8) & 0xff), 2810 (unsigned int)(((msr) >> 16) & 0xff), 2811 (unsigned int)(((msr) >> 24) & 0xff), 2812 (unsigned int)(((msr) >> 32) & 0xff3)); 2813 } 2814 if (has_hwp_notify) { 2815 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 2816 return 0; 2817 2818 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 2819 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 2820 cpu, msr, 2821 ((msr) & 0x1) ? "EN" : "Dis", 2822 ((msr) & 0x2) ? "EN" : "Dis"); 2823 } 2824 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 2825 return 0; 2826 2827 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 2828 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 2829 cpu, msr, 2830 ((msr) & 0x1) ? "" : "No-", 2831 ((msr) & 0x2) ? "" : "No-"); 2832 2833 return 0; 2834 } 2835 2836 /* 2837 * print_perf_limit() 2838 */ 2839 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2840 { 2841 unsigned long long msr; 2842 int cpu; 2843 2844 cpu = t->cpu_id; 2845 2846 /* per-package */ 2847 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2848 return 0; 2849 2850 if (cpu_migrate(cpu)) { 2851 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2852 return -1; 2853 } 2854 2855 if (do_core_perf_limit_reasons) { 2856 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 2857 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2858 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 2859 (msr & 1 << 15) ? "bit15, " : "", 2860 (msr & 1 << 14) ? "bit14, " : "", 2861 (msr & 1 << 13) ? "Transitions, " : "", 2862 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 2863 (msr & 1 << 11) ? "PkgPwrL2, " : "", 2864 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2865 (msr & 1 << 9) ? "CorePwr, " : "", 2866 (msr & 1 << 8) ? "Amps, " : "", 2867 (msr & 1 << 6) ? "VR-Therm, " : "", 2868 (msr & 1 << 5) ? "Auto-HWP, " : "", 2869 (msr & 1 << 4) ? "Graphics, " : "", 2870 (msr & 1 << 2) ? "bit2, " : "", 2871 (msr & 1 << 1) ? "ThermStatus, " : "", 2872 (msr & 1 << 0) ? "PROCHOT, " : ""); 2873 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 2874 (msr & 1 << 31) ? "bit31, " : "", 2875 (msr & 1 << 30) ? "bit30, " : "", 2876 (msr & 1 << 29) ? "Transitions, " : "", 2877 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 2878 (msr & 1 << 27) ? "PkgPwrL2, " : "", 2879 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2880 (msr & 1 << 25) ? "CorePwr, " : "", 2881 (msr & 1 << 24) ? "Amps, " : "", 2882 (msr & 1 << 22) ? "VR-Therm, " : "", 2883 (msr & 1 << 21) ? "Auto-HWP, " : "", 2884 (msr & 1 << 20) ? "Graphics, " : "", 2885 (msr & 1 << 18) ? "bit18, " : "", 2886 (msr & 1 << 17) ? "ThermStatus, " : "", 2887 (msr & 1 << 16) ? "PROCHOT, " : ""); 2888 2889 } 2890 if (do_gfx_perf_limit_reasons) { 2891 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 2892 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2893 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 2894 (msr & 1 << 0) ? "PROCHOT, " : "", 2895 (msr & 1 << 1) ? "ThermStatus, " : "", 2896 (msr & 1 << 4) ? "Graphics, " : "", 2897 (msr & 1 << 6) ? "VR-Therm, " : "", 2898 (msr & 1 << 8) ? "Amps, " : "", 2899 (msr & 1 << 9) ? "GFXPwr, " : "", 2900 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2901 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 2902 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 2903 (msr & 1 << 16) ? "PROCHOT, " : "", 2904 (msr & 1 << 17) ? "ThermStatus, " : "", 2905 (msr & 1 << 20) ? "Graphics, " : "", 2906 (msr & 1 << 22) ? "VR-Therm, " : "", 2907 (msr & 1 << 24) ? "Amps, " : "", 2908 (msr & 1 << 25) ? "GFXPwr, " : "", 2909 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2910 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 2911 } 2912 if (do_ring_perf_limit_reasons) { 2913 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 2914 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2915 fprintf(outf, " (Active: %s%s%s%s%s%s)", 2916 (msr & 1 << 0) ? "PROCHOT, " : "", 2917 (msr & 1 << 1) ? "ThermStatus, " : "", 2918 (msr & 1 << 6) ? "VR-Therm, " : "", 2919 (msr & 1 << 8) ? "Amps, " : "", 2920 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2921 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 2922 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 2923 (msr & 1 << 16) ? "PROCHOT, " : "", 2924 (msr & 1 << 17) ? "ThermStatus, " : "", 2925 (msr & 1 << 22) ? "VR-Therm, " : "", 2926 (msr & 1 << 24) ? "Amps, " : "", 2927 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2928 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 2929 } 2930 return 0; 2931 } 2932 2933 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 2934 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 2935 2936 double get_tdp(unsigned int model) 2937 { 2938 unsigned long long msr; 2939 2940 if (do_rapl & RAPL_PKG_POWER_INFO) 2941 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 2942 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 2943 2944 switch (model) { 2945 case INTEL_FAM6_ATOM_SILVERMONT1: 2946 case INTEL_FAM6_ATOM_SILVERMONT2: 2947 return 30.0; 2948 default: 2949 return 135.0; 2950 } 2951 } 2952 2953 /* 2954 * rapl_dram_energy_units_probe() 2955 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 2956 */ 2957 static double 2958 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 2959 { 2960 /* only called for genuine_intel, family 6 */ 2961 2962 switch (model) { 2963 case INTEL_FAM6_HASWELL_X: /* HSX */ 2964 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2965 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2966 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 2967 case INTEL_FAM6_XEON_PHI_KNM: 2968 return (rapl_dram_energy_units = 15.3 / 1000000); 2969 default: 2970 return (rapl_energy_units); 2971 } 2972 } 2973 2974 2975 /* 2976 * rapl_probe() 2977 * 2978 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 2979 */ 2980 void rapl_probe(unsigned int family, unsigned int model) 2981 { 2982 unsigned long long msr; 2983 unsigned int time_unit; 2984 double tdp; 2985 2986 if (!genuine_intel) 2987 return; 2988 2989 if (family != 6) 2990 return; 2991 2992 switch (model) { 2993 case INTEL_FAM6_SANDYBRIDGE: 2994 case INTEL_FAM6_IVYBRIDGE: 2995 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 2996 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 2997 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 2998 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 2999 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3000 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 3001 if (rapl_joules) { 3002 BIC_PRESENT(BIC_Pkg_J); 3003 BIC_PRESENT(BIC_Cor_J); 3004 BIC_PRESENT(BIC_GFX_J); 3005 } else { 3006 BIC_PRESENT(BIC_PkgWatt); 3007 BIC_PRESENT(BIC_CorWatt); 3008 BIC_PRESENT(BIC_GFXWatt); 3009 } 3010 break; 3011 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3012 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 3013 if (rapl_joules) 3014 BIC_PRESENT(BIC_Pkg_J); 3015 else 3016 BIC_PRESENT(BIC_PkgWatt); 3017 break; 3018 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3019 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3020 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3021 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3022 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 3023 BIC_PRESENT(BIC_PKG__); 3024 BIC_PRESENT(BIC_RAM__); 3025 if (rapl_joules) { 3026 BIC_PRESENT(BIC_Pkg_J); 3027 BIC_PRESENT(BIC_Cor_J); 3028 BIC_PRESENT(BIC_RAM_J); 3029 } else { 3030 BIC_PRESENT(BIC_PkgWatt); 3031 BIC_PRESENT(BIC_CorWatt); 3032 BIC_PRESENT(BIC_RAMWatt); 3033 } 3034 break; 3035 case INTEL_FAM6_HASWELL_X: /* HSX */ 3036 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3037 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3038 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3039 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3040 case INTEL_FAM6_XEON_PHI_KNM: 3041 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 3042 BIC_PRESENT(BIC_PKG__); 3043 BIC_PRESENT(BIC_RAM__); 3044 if (rapl_joules) { 3045 BIC_PRESENT(BIC_Pkg_J); 3046 BIC_PRESENT(BIC_RAM_J); 3047 } else { 3048 BIC_PRESENT(BIC_PkgWatt); 3049 BIC_PRESENT(BIC_RAMWatt); 3050 } 3051 break; 3052 case INTEL_FAM6_SANDYBRIDGE_X: 3053 case INTEL_FAM6_IVYBRIDGE_X: 3054 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 3055 BIC_PRESENT(BIC_PKG__); 3056 BIC_PRESENT(BIC_RAM__); 3057 if (rapl_joules) { 3058 BIC_PRESENT(BIC_Pkg_J); 3059 BIC_PRESENT(BIC_Cor_J); 3060 BIC_PRESENT(BIC_RAM_J); 3061 } else { 3062 BIC_PRESENT(BIC_PkgWatt); 3063 BIC_PRESENT(BIC_CorWatt); 3064 BIC_PRESENT(BIC_RAMWatt); 3065 } 3066 break; 3067 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 3068 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 3069 do_rapl = RAPL_PKG | RAPL_CORES; 3070 if (rapl_joules) { 3071 BIC_PRESENT(BIC_Pkg_J); 3072 BIC_PRESENT(BIC_Cor_J); 3073 } else { 3074 BIC_PRESENT(BIC_PkgWatt); 3075 BIC_PRESENT(BIC_CorWatt); 3076 } 3077 break; 3078 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3079 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 3080 BIC_PRESENT(BIC_PKG__); 3081 BIC_PRESENT(BIC_RAM__); 3082 if (rapl_joules) { 3083 BIC_PRESENT(BIC_Pkg_J); 3084 BIC_PRESENT(BIC_Cor_J); 3085 BIC_PRESENT(BIC_RAM_J); 3086 } else { 3087 BIC_PRESENT(BIC_PkgWatt); 3088 BIC_PRESENT(BIC_CorWatt); 3089 BIC_PRESENT(BIC_RAMWatt); 3090 } 3091 break; 3092 default: 3093 return; 3094 } 3095 3096 /* units on package 0, verify later other packages match */ 3097 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 3098 return; 3099 3100 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 3101 if (model == INTEL_FAM6_ATOM_SILVERMONT1) 3102 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 3103 else 3104 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 3105 3106 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 3107 3108 time_unit = msr >> 16 & 0xF; 3109 if (time_unit == 0) 3110 time_unit = 0xA; 3111 3112 rapl_time_units = 1.0 / (1 << (time_unit)); 3113 3114 tdp = get_tdp(model); 3115 3116 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 3117 if (debug) 3118 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 3119 3120 return; 3121 } 3122 3123 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 3124 { 3125 if (!genuine_intel) 3126 return; 3127 3128 if (family != 6) 3129 return; 3130 3131 switch (model) { 3132 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3133 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3134 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3135 do_gfx_perf_limit_reasons = 1; 3136 case INTEL_FAM6_HASWELL_X: /* HSX */ 3137 do_core_perf_limit_reasons = 1; 3138 do_ring_perf_limit_reasons = 1; 3139 default: 3140 return; 3141 } 3142 } 3143 3144 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3145 { 3146 unsigned long long msr; 3147 unsigned int dts; 3148 int cpu; 3149 3150 if (!(do_dts || do_ptm)) 3151 return 0; 3152 3153 cpu = t->cpu_id; 3154 3155 /* DTS is per-core, no need to print for each thread */ 3156 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 3157 return 0; 3158 3159 if (cpu_migrate(cpu)) { 3160 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3161 return -1; 3162 } 3163 3164 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 3165 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 3166 return 0; 3167 3168 dts = (msr >> 16) & 0x7F; 3169 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 3170 cpu, msr, tcc_activation_temp - dts); 3171 3172 #ifdef THERM_DEBUG 3173 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 3174 return 0; 3175 3176 dts = (msr >> 16) & 0x7F; 3177 dts2 = (msr >> 8) & 0x7F; 3178 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 3179 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 3180 #endif 3181 } 3182 3183 3184 if (do_dts) { 3185 unsigned int resolution; 3186 3187 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 3188 return 0; 3189 3190 dts = (msr >> 16) & 0x7F; 3191 resolution = (msr >> 27) & 0xF; 3192 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 3193 cpu, msr, tcc_activation_temp - dts, resolution); 3194 3195 #ifdef THERM_DEBUG 3196 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 3197 return 0; 3198 3199 dts = (msr >> 16) & 0x7F; 3200 dts2 = (msr >> 8) & 0x7F; 3201 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 3202 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 3203 #endif 3204 } 3205 3206 return 0; 3207 } 3208 3209 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 3210 { 3211 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 3212 cpu, label, 3213 ((msr >> 15) & 1) ? "EN" : "DIS", 3214 ((msr >> 0) & 0x7FFF) * rapl_power_units, 3215 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 3216 (((msr >> 16) & 1) ? "EN" : "DIS")); 3217 3218 return; 3219 } 3220 3221 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3222 { 3223 unsigned long long msr; 3224 int cpu; 3225 3226 if (!do_rapl) 3227 return 0; 3228 3229 /* RAPL counters are per package, so print only for 1st thread/package */ 3230 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3231 return 0; 3232 3233 cpu = t->cpu_id; 3234 if (cpu_migrate(cpu)) { 3235 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3236 return -1; 3237 } 3238 3239 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 3240 return -1; 3241 3242 if (debug) { 3243 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx " 3244 "(%f Watts, %f Joules, %f sec.)\n", cpu, msr, 3245 rapl_power_units, rapl_energy_units, rapl_time_units); 3246 } 3247 if (do_rapl & RAPL_PKG_POWER_INFO) { 3248 3249 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 3250 return -5; 3251 3252 3253 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 3254 cpu, msr, 3255 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3256 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3257 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3258 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 3259 3260 } 3261 if (do_rapl & RAPL_PKG) { 3262 3263 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 3264 return -9; 3265 3266 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 3267 cpu, msr, (msr >> 63) & 1 ? "": "UN"); 3268 3269 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 3270 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 3271 cpu, 3272 ((msr >> 47) & 1) ? "EN" : "DIS", 3273 ((msr >> 32) & 0x7FFF) * rapl_power_units, 3274 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 3275 ((msr >> 48) & 1) ? "EN" : "DIS"); 3276 } 3277 3278 if (do_rapl & RAPL_DRAM_POWER_INFO) { 3279 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 3280 return -6; 3281 3282 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 3283 cpu, msr, 3284 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3285 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3286 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3287 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 3288 } 3289 if (do_rapl & RAPL_DRAM) { 3290 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 3291 return -9; 3292 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 3293 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 3294 3295 print_power_limit_msr(cpu, msr, "DRAM Limit"); 3296 } 3297 if (do_rapl & RAPL_CORE_POLICY) { 3298 if (debug) { 3299 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 3300 return -7; 3301 3302 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 3303 } 3304 } 3305 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 3306 if (debug) { 3307 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 3308 return -9; 3309 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 3310 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 3311 print_power_limit_msr(cpu, msr, "Cores Limit"); 3312 } 3313 } 3314 if (do_rapl & RAPL_GFX) { 3315 if (debug) { 3316 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 3317 return -8; 3318 3319 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 3320 3321 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 3322 return -9; 3323 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 3324 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 3325 print_power_limit_msr(cpu, msr, "GFX Limit"); 3326 } 3327 } 3328 return 0; 3329 } 3330 3331 /* 3332 * SNB adds support for additional MSRs: 3333 * 3334 * MSR_PKG_C7_RESIDENCY 0x000003fa 3335 * MSR_CORE_C7_RESIDENCY 0x000003fe 3336 * MSR_PKG_C2_RESIDENCY 0x0000060d 3337 */ 3338 3339 int has_snb_msrs(unsigned int family, unsigned int model) 3340 { 3341 if (!genuine_intel) 3342 return 0; 3343 3344 switch (model) { 3345 case INTEL_FAM6_SANDYBRIDGE: 3346 case INTEL_FAM6_SANDYBRIDGE_X: 3347 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3348 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3349 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3350 case INTEL_FAM6_HASWELL_X: /* HSW */ 3351 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3352 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3353 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3354 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3355 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3356 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3357 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3358 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3359 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3360 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3361 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3362 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3363 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3364 return 1; 3365 } 3366 return 0; 3367 } 3368 3369 /* 3370 * HSW adds support for additional MSRs: 3371 * 3372 * MSR_PKG_C8_RESIDENCY 0x00000630 3373 * MSR_PKG_C9_RESIDENCY 0x00000631 3374 * MSR_PKG_C10_RESIDENCY 0x00000632 3375 * 3376 * MSR_PKGC8_IRTL 0x00000633 3377 * MSR_PKGC9_IRTL 0x00000634 3378 * MSR_PKGC10_IRTL 0x00000635 3379 * 3380 */ 3381 int has_hsw_msrs(unsigned int family, unsigned int model) 3382 { 3383 if (!genuine_intel) 3384 return 0; 3385 3386 switch (model) { 3387 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3388 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3389 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3390 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3391 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3392 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3393 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3394 return 1; 3395 } 3396 return 0; 3397 } 3398 3399 /* 3400 * SKL adds support for additional MSRS: 3401 * 3402 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 3403 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 3404 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 3405 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 3406 */ 3407 int has_skl_msrs(unsigned int family, unsigned int model) 3408 { 3409 if (!genuine_intel) 3410 return 0; 3411 3412 switch (model) { 3413 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3414 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3415 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3416 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3417 return 1; 3418 } 3419 return 0; 3420 } 3421 3422 int is_slm(unsigned int family, unsigned int model) 3423 { 3424 if (!genuine_intel) 3425 return 0; 3426 switch (model) { 3427 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 3428 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 3429 return 1; 3430 } 3431 return 0; 3432 } 3433 3434 int is_knl(unsigned int family, unsigned int model) 3435 { 3436 if (!genuine_intel) 3437 return 0; 3438 switch (model) { 3439 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3440 case INTEL_FAM6_XEON_PHI_KNM: 3441 return 1; 3442 } 3443 return 0; 3444 } 3445 3446 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 3447 { 3448 if (is_knl(family, model)) 3449 return 1024; 3450 return 1; 3451 } 3452 3453 #define SLM_BCLK_FREQS 5 3454 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 3455 3456 double slm_bclk(void) 3457 { 3458 unsigned long long msr = 3; 3459 unsigned int i; 3460 double freq; 3461 3462 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 3463 fprintf(outf, "SLM BCLK: unknown\n"); 3464 3465 i = msr & 0xf; 3466 if (i >= SLM_BCLK_FREQS) { 3467 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 3468 i = 3; 3469 } 3470 freq = slm_freq_table[i]; 3471 3472 if (debug) 3473 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 3474 3475 return freq; 3476 } 3477 3478 double discover_bclk(unsigned int family, unsigned int model) 3479 { 3480 if (has_snb_msrs(family, model) || is_knl(family, model)) 3481 return 100.00; 3482 else if (is_slm(family, model)) 3483 return slm_bclk(); 3484 else 3485 return 133.33; 3486 } 3487 3488 /* 3489 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 3490 * the Thermal Control Circuit (TCC) activates. 3491 * This is usually equal to tjMax. 3492 * 3493 * Older processors do not have this MSR, so there we guess, 3494 * but also allow cmdline over-ride with -T. 3495 * 3496 * Several MSR temperature values are in units of degrees-C 3497 * below this value, including the Digital Thermal Sensor (DTS), 3498 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 3499 */ 3500 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3501 { 3502 unsigned long long msr; 3503 unsigned int target_c_local; 3504 int cpu; 3505 3506 /* tcc_activation_temp is used only for dts or ptm */ 3507 if (!(do_dts || do_ptm)) 3508 return 0; 3509 3510 /* this is a per-package concept */ 3511 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3512 return 0; 3513 3514 cpu = t->cpu_id; 3515 if (cpu_migrate(cpu)) { 3516 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3517 return -1; 3518 } 3519 3520 if (tcc_activation_temp_override != 0) { 3521 tcc_activation_temp = tcc_activation_temp_override; 3522 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 3523 cpu, tcc_activation_temp); 3524 return 0; 3525 } 3526 3527 /* Temperature Target MSR is Nehalem and newer only */ 3528 if (!do_nhm_platform_info) 3529 goto guess; 3530 3531 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 3532 goto guess; 3533 3534 target_c_local = (msr >> 16) & 0xFF; 3535 3536 if (debug) 3537 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 3538 cpu, msr, target_c_local); 3539 3540 if (!target_c_local) 3541 goto guess; 3542 3543 tcc_activation_temp = target_c_local; 3544 3545 return 0; 3546 3547 guess: 3548 tcc_activation_temp = TJMAX_DEFAULT; 3549 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 3550 cpu, tcc_activation_temp); 3551 3552 return 0; 3553 } 3554 3555 void decode_feature_control_msr(void) 3556 { 3557 unsigned long long msr; 3558 3559 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) 3560 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 3561 base_cpu, msr, 3562 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", 3563 msr & (1 << 18) ? "SGX" : ""); 3564 } 3565 3566 void decode_misc_enable_msr(void) 3567 { 3568 unsigned long long msr; 3569 3570 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 3571 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 3572 base_cpu, msr, 3573 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 3574 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 3575 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "No-" : "", 3576 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 3577 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 3578 } 3579 3580 void decode_misc_feature_control(void) 3581 { 3582 unsigned long long msr; 3583 3584 if (!has_misc_feature_control) 3585 return; 3586 3587 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 3588 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 3589 base_cpu, msr, 3590 msr & (0 << 0) ? "No-" : "", 3591 msr & (1 << 0) ? "No-" : "", 3592 msr & (2 << 0) ? "No-" : "", 3593 msr & (3 << 0) ? "No-" : ""); 3594 } 3595 /* 3596 * Decode MSR_MISC_PWR_MGMT 3597 * 3598 * Decode the bits according to the Nehalem documentation 3599 * bit[0] seems to continue to have same meaning going forward 3600 * bit[1] less so... 3601 */ 3602 void decode_misc_pwr_mgmt_msr(void) 3603 { 3604 unsigned long long msr; 3605 3606 if (!do_nhm_platform_info) 3607 return; 3608 3609 if (no_MSR_MISC_PWR_MGMT) 3610 return; 3611 3612 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 3613 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 3614 base_cpu, msr, 3615 msr & (1 << 0) ? "DIS" : "EN", 3616 msr & (1 << 1) ? "EN" : "DIS", 3617 msr & (1 << 8) ? "EN" : "DIS"); 3618 } 3619 /* 3620 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 3621 * 3622 * This MSRs are present on Silvermont processors, 3623 * Intel Atom processor E3000 series (Baytrail), and friends. 3624 */ 3625 void decode_c6_demotion_policy_msr(void) 3626 { 3627 unsigned long long msr; 3628 3629 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 3630 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 3631 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 3632 3633 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 3634 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 3635 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 3636 } 3637 3638 void process_cpuid() 3639 { 3640 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level; 3641 unsigned int fms, family, model, stepping; 3642 unsigned int has_turbo; 3643 3644 eax = ebx = ecx = edx = 0; 3645 3646 __cpuid(0, max_level, ebx, ecx, edx); 3647 3648 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) 3649 genuine_intel = 1; 3650 3651 if (debug) 3652 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 3653 (char *)&ebx, (char *)&edx, (char *)&ecx); 3654 3655 __cpuid(1, fms, ebx, ecx, edx); 3656 family = (fms >> 8) & 0xf; 3657 model = (fms >> 4) & 0xf; 3658 stepping = fms & 0xf; 3659 if (family == 6 || family == 0xf) 3660 model += ((fms >> 16) & 0xf) << 4; 3661 3662 if (debug) { 3663 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 3664 max_level, family, model, stepping, family, model, stepping); 3665 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n", 3666 ecx & (1 << 0) ? "SSE3" : "-", 3667 ecx & (1 << 3) ? "MONITOR" : "-", 3668 ecx & (1 << 6) ? "SMX" : "-", 3669 ecx & (1 << 7) ? "EIST" : "-", 3670 ecx & (1 << 8) ? "TM2" : "-", 3671 edx & (1 << 4) ? "TSC" : "-", 3672 edx & (1 << 5) ? "MSR" : "-", 3673 edx & (1 << 22) ? "ACPI-TM" : "-", 3674 edx & (1 << 29) ? "TM" : "-"); 3675 } 3676 3677 if (!(edx & (1 << 5))) 3678 errx(1, "CPUID: no MSR"); 3679 3680 /* 3681 * check max extended function levels of CPUID. 3682 * This is needed to check for invariant TSC. 3683 * This check is valid for both Intel and AMD. 3684 */ 3685 ebx = ecx = edx = 0; 3686 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 3687 3688 if (max_extended_level >= 0x80000007) { 3689 3690 /* 3691 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 3692 * this check is valid for both Intel and AMD 3693 */ 3694 __cpuid(0x80000007, eax, ebx, ecx, edx); 3695 has_invariant_tsc = edx & (1 << 8); 3696 } 3697 3698 /* 3699 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 3700 * this check is valid for both Intel and AMD 3701 */ 3702 3703 __cpuid(0x6, eax, ebx, ecx, edx); 3704 has_aperf = ecx & (1 << 0); 3705 if (has_aperf) { 3706 BIC_PRESENT(BIC_Avg_MHz); 3707 BIC_PRESENT(BIC_Busy); 3708 BIC_PRESENT(BIC_Bzy_MHz); 3709 } 3710 do_dts = eax & (1 << 0); 3711 if (do_dts) 3712 BIC_PRESENT(BIC_CoreTmp); 3713 has_turbo = eax & (1 << 1); 3714 do_ptm = eax & (1 << 6); 3715 if (do_ptm) 3716 BIC_PRESENT(BIC_PkgTmp); 3717 has_hwp = eax & (1 << 7); 3718 has_hwp_notify = eax & (1 << 8); 3719 has_hwp_activity_window = eax & (1 << 9); 3720 has_hwp_epp = eax & (1 << 10); 3721 has_hwp_pkg = eax & (1 << 11); 3722 has_epb = ecx & (1 << 3); 3723 3724 if (debug) 3725 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 3726 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 3727 has_aperf ? "" : "No-", 3728 has_turbo ? "" : "No-", 3729 do_dts ? "" : "No-", 3730 do_ptm ? "" : "No-", 3731 has_hwp ? "" : "No-", 3732 has_hwp_notify ? "" : "No-", 3733 has_hwp_activity_window ? "" : "No-", 3734 has_hwp_epp ? "" : "No-", 3735 has_hwp_pkg ? "" : "No-", 3736 has_epb ? "" : "No-"); 3737 3738 if (debug) 3739 decode_misc_enable_msr(); 3740 3741 3742 if (max_level >= 0x7 && debug) { 3743 int has_sgx; 3744 3745 ecx = 0; 3746 3747 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 3748 3749 has_sgx = ebx & (1 << 2); 3750 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 3751 3752 if (has_sgx) 3753 decode_feature_control_msr(); 3754 } 3755 3756 if (max_level >= 0x15) { 3757 unsigned int eax_crystal; 3758 unsigned int ebx_tsc; 3759 3760 /* 3761 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 3762 */ 3763 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 3764 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 3765 3766 if (ebx_tsc != 0) { 3767 3768 if (debug && (ebx != 0)) 3769 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 3770 eax_crystal, ebx_tsc, crystal_hz); 3771 3772 if (crystal_hz == 0) 3773 switch(model) { 3774 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3775 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3776 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3777 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3778 crystal_hz = 24000000; /* 24.0 MHz */ 3779 break; 3780 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3781 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3782 crystal_hz = 25000000; /* 25.0 MHz */ 3783 break; 3784 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3785 crystal_hz = 19200000; /* 19.2 MHz */ 3786 break; 3787 default: 3788 crystal_hz = 0; 3789 } 3790 3791 if (crystal_hz) { 3792 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 3793 if (debug) 3794 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 3795 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 3796 } 3797 } 3798 } 3799 if (max_level >= 0x16) { 3800 unsigned int base_mhz, max_mhz, bus_mhz, edx; 3801 3802 /* 3803 * CPUID 16H Base MHz, Max MHz, Bus MHz 3804 */ 3805 base_mhz = max_mhz = bus_mhz = edx = 0; 3806 3807 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 3808 if (debug) 3809 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 3810 base_mhz, max_mhz, bus_mhz); 3811 } 3812 3813 if (has_aperf) 3814 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 3815 3816 BIC_PRESENT(BIC_IRQ); 3817 BIC_PRESENT(BIC_TSC_MHz); 3818 3819 if (probe_nhm_msrs(family, model)) { 3820 do_nhm_platform_info = 1; 3821 BIC_PRESENT(BIC_CPU_c1); 3822 BIC_PRESENT(BIC_CPU_c3); 3823 BIC_PRESENT(BIC_CPU_c6); 3824 BIC_PRESENT(BIC_SMI); 3825 } 3826 do_snb_cstates = has_snb_msrs(family, model); 3827 3828 if (do_snb_cstates) 3829 BIC_PRESENT(BIC_CPU_c7); 3830 3831 do_irtl_snb = has_snb_msrs(family, model); 3832 do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2); 3833 do_pc3 = (pkg_cstate_limit >= PCL__3); 3834 do_pc6 = (pkg_cstate_limit >= PCL__6); 3835 do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7); 3836 if (has_slv_msrs(family, model)) { 3837 do_pc2 = do_pc3 = do_pc7 = 0; 3838 do_pc6 = 1; 3839 BIC_PRESENT(BIC_Mod_c6); 3840 use_c1_residency_msr = 1; 3841 } 3842 do_c8_c9_c10 = has_hsw_msrs(family, model); 3843 do_irtl_hsw = has_hsw_msrs(family, model); 3844 do_skl_residency = has_skl_msrs(family, model); 3845 do_slm_cstates = is_slm(family, model); 3846 do_knl_cstates = is_knl(family, model); 3847 3848 if (debug) 3849 decode_misc_pwr_mgmt_msr(); 3850 3851 if (debug && has_slv_msrs(family, model)) 3852 decode_c6_demotion_policy_msr(); 3853 3854 rapl_probe(family, model); 3855 perf_limit_reasons_probe(family, model); 3856 3857 if (debug) 3858 dump_cstate_pstate_config_info(family, model); 3859 3860 if (has_skl_msrs(family, model)) 3861 calculate_tsc_tweak(); 3862 3863 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 3864 BIC_PRESENT(BIC_GFX_rc6); 3865 3866 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 3867 BIC_PRESENT(BIC_GFXMHz); 3868 3869 if (debug) 3870 decode_misc_feature_control(); 3871 3872 return; 3873 } 3874 3875 void help() 3876 { 3877 fprintf(outf, 3878 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 3879 "\n" 3880 "Turbostat forks the specified COMMAND and prints statistics\n" 3881 "when COMMAND completes.\n" 3882 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 3883 "to print statistics, until interrupted.\n" 3884 "--add add a counter\n" 3885 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 3886 "--debug run in \"debug\" mode\n" 3887 "--interval sec Override default 5-second measurement interval\n" 3888 "--help print this help message\n" 3889 "--out file create or truncate \"file\" for all output\n" 3890 "--version print version information\n" 3891 "\n" 3892 "For more help, run \"man turbostat\"\n"); 3893 } 3894 3895 3896 /* 3897 * in /dev/cpu/ return success for names that are numbers 3898 * ie. filter out ".", "..", "microcode". 3899 */ 3900 int dir_filter(const struct dirent *dirp) 3901 { 3902 if (isdigit(dirp->d_name[0])) 3903 return 1; 3904 else 3905 return 0; 3906 } 3907 3908 int open_dev_cpu_msr(int dummy1) 3909 { 3910 return 0; 3911 } 3912 3913 void topology_probe() 3914 { 3915 int i; 3916 int max_core_id = 0; 3917 int max_package_id = 0; 3918 int max_siblings = 0; 3919 struct cpu_topology { 3920 int core_id; 3921 int physical_package_id; 3922 } *cpus; 3923 3924 /* Initialize num_cpus, max_cpu_num */ 3925 topo.num_cpus = 0; 3926 topo.max_cpu_num = 0; 3927 for_all_proc_cpus(count_cpus); 3928 if (!summary_only && topo.num_cpus > 1) 3929 BIC_PRESENT(BIC_CPU); 3930 3931 if (debug > 1) 3932 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 3933 3934 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 3935 if (cpus == NULL) 3936 err(1, "calloc cpus"); 3937 3938 /* 3939 * Allocate and initialize cpu_present_set 3940 */ 3941 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 3942 if (cpu_present_set == NULL) 3943 err(3, "CPU_ALLOC"); 3944 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3945 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 3946 for_all_proc_cpus(mark_cpu_present); 3947 3948 /* 3949 * Allocate and initialize cpu_affinity_set 3950 */ 3951 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 3952 if (cpu_affinity_set == NULL) 3953 err(3, "CPU_ALLOC"); 3954 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3955 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 3956 3957 3958 /* 3959 * For online cpus 3960 * find max_core_id, max_package_id 3961 */ 3962 for (i = 0; i <= topo.max_cpu_num; ++i) { 3963 int siblings; 3964 3965 if (cpu_is_not_present(i)) { 3966 if (debug > 1) 3967 fprintf(outf, "cpu%d NOT PRESENT\n", i); 3968 continue; 3969 } 3970 cpus[i].core_id = get_core_id(i); 3971 if (cpus[i].core_id > max_core_id) 3972 max_core_id = cpus[i].core_id; 3973 3974 cpus[i].physical_package_id = get_physical_package_id(i); 3975 if (cpus[i].physical_package_id > max_package_id) 3976 max_package_id = cpus[i].physical_package_id; 3977 3978 siblings = get_num_ht_siblings(i); 3979 if (siblings > max_siblings) 3980 max_siblings = siblings; 3981 if (debug > 1) 3982 fprintf(outf, "cpu %d pkg %d core %d\n", 3983 i, cpus[i].physical_package_id, cpus[i].core_id); 3984 } 3985 topo.num_cores_per_pkg = max_core_id + 1; 3986 if (debug > 1) 3987 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 3988 max_core_id, topo.num_cores_per_pkg); 3989 if (debug && !summary_only && topo.num_cores_per_pkg > 1) 3990 BIC_PRESENT(BIC_Core); 3991 3992 topo.num_packages = max_package_id + 1; 3993 if (debug > 1) 3994 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 3995 max_package_id, topo.num_packages); 3996 if (debug && !summary_only && topo.num_packages > 1) 3997 BIC_PRESENT(BIC_Package); 3998 3999 topo.num_threads_per_core = max_siblings; 4000 if (debug > 1) 4001 fprintf(outf, "max_siblings %d\n", max_siblings); 4002 4003 free(cpus); 4004 } 4005 4006 void 4007 allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) 4008 { 4009 int i; 4010 4011 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg * 4012 topo.num_packages, sizeof(struct thread_data)); 4013 if (*t == NULL) 4014 goto error; 4015 4016 for (i = 0; i < topo.num_threads_per_core * 4017 topo.num_cores_per_pkg * topo.num_packages; i++) 4018 (*t)[i].cpu_id = -1; 4019 4020 *c = calloc(topo.num_cores_per_pkg * topo.num_packages, 4021 sizeof(struct core_data)); 4022 if (*c == NULL) 4023 goto error; 4024 4025 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++) 4026 (*c)[i].core_id = -1; 4027 4028 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 4029 if (*p == NULL) 4030 goto error; 4031 4032 for (i = 0; i < topo.num_packages; i++) 4033 (*p)[i].package_id = i; 4034 4035 return; 4036 error: 4037 err(1, "calloc counters"); 4038 } 4039 /* 4040 * init_counter() 4041 * 4042 * set cpu_id, core_num, pkg_num 4043 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 4044 * 4045 * increment topo.num_cores when 1st core in pkg seen 4046 */ 4047 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 4048 struct pkg_data *pkg_base, int thread_num, int core_num, 4049 int pkg_num, int cpu_id) 4050 { 4051 struct thread_data *t; 4052 struct core_data *c; 4053 struct pkg_data *p; 4054 4055 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num); 4056 c = GET_CORE(core_base, core_num, pkg_num); 4057 p = GET_PKG(pkg_base, pkg_num); 4058 4059 t->cpu_id = cpu_id; 4060 if (thread_num == 0) { 4061 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 4062 if (cpu_is_first_core_in_package(cpu_id)) 4063 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 4064 } 4065 4066 c->core_id = core_num; 4067 p->package_id = pkg_num; 4068 } 4069 4070 4071 int initialize_counters(int cpu_id) 4072 { 4073 int my_thread_id, my_core_id, my_package_id; 4074 4075 my_package_id = get_physical_package_id(cpu_id); 4076 my_core_id = get_core_id(cpu_id); 4077 my_thread_id = get_cpu_position_in_core(cpu_id); 4078 if (!my_thread_id) 4079 topo.num_cores++; 4080 4081 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); 4082 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); 4083 return 0; 4084 } 4085 4086 void allocate_output_buffer() 4087 { 4088 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); 4089 outp = output_buffer; 4090 if (outp == NULL) 4091 err(-1, "calloc output buffer"); 4092 } 4093 void allocate_fd_percpu(void) 4094 { 4095 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 4096 if (fd_percpu == NULL) 4097 err(-1, "calloc fd_percpu"); 4098 } 4099 void allocate_irq_buffers(void) 4100 { 4101 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 4102 if (irq_column_2_cpu == NULL) 4103 err(-1, "calloc %d", topo.num_cpus); 4104 4105 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 4106 if (irqs_per_cpu == NULL) 4107 err(-1, "calloc %d", topo.max_cpu_num + 1); 4108 } 4109 void setup_all_buffers(void) 4110 { 4111 topology_probe(); 4112 allocate_irq_buffers(); 4113 allocate_fd_percpu(); 4114 allocate_counters(&thread_even, &core_even, &package_even); 4115 allocate_counters(&thread_odd, &core_odd, &package_odd); 4116 allocate_output_buffer(); 4117 for_all_proc_cpus(initialize_counters); 4118 } 4119 4120 void set_base_cpu(void) 4121 { 4122 base_cpu = sched_getcpu(); 4123 if (base_cpu < 0) 4124 err(-ENODEV, "No valid cpus found"); 4125 4126 if (debug > 1) 4127 fprintf(outf, "base_cpu = %d\n", base_cpu); 4128 } 4129 4130 void turbostat_init() 4131 { 4132 setup_all_buffers(); 4133 set_base_cpu(); 4134 check_dev_msr(); 4135 check_permissions(); 4136 process_cpuid(); 4137 4138 4139 if (debug) 4140 for_all_cpus(print_hwp, ODD_COUNTERS); 4141 4142 if (debug) 4143 for_all_cpus(print_epb, ODD_COUNTERS); 4144 4145 if (debug) 4146 for_all_cpus(print_perf_limit, ODD_COUNTERS); 4147 4148 if (debug) 4149 for_all_cpus(print_rapl, ODD_COUNTERS); 4150 4151 for_all_cpus(set_temperature_target, ODD_COUNTERS); 4152 4153 if (debug) 4154 for_all_cpus(print_thermal, ODD_COUNTERS); 4155 4156 if (debug && do_irtl_snb) 4157 print_irtl(); 4158 } 4159 4160 int fork_it(char **argv) 4161 { 4162 pid_t child_pid; 4163 int status; 4164 4165 status = for_all_cpus(get_counters, EVEN_COUNTERS); 4166 if (status) 4167 exit(status); 4168 /* clear affinity side-effect of get_counters() */ 4169 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 4170 gettimeofday(&tv_even, (struct timezone *)NULL); 4171 4172 child_pid = fork(); 4173 if (!child_pid) { 4174 /* child */ 4175 execvp(argv[0], argv); 4176 } else { 4177 4178 /* parent */ 4179 if (child_pid == -1) 4180 err(1, "fork"); 4181 4182 signal(SIGINT, SIG_IGN); 4183 signal(SIGQUIT, SIG_IGN); 4184 if (waitpid(child_pid, &status, 0) == -1) 4185 err(status, "waitpid"); 4186 } 4187 /* 4188 * n.b. fork_it() does not check for errors from for_all_cpus() 4189 * because re-starting is problematic when forking 4190 */ 4191 for_all_cpus(get_counters, ODD_COUNTERS); 4192 gettimeofday(&tv_odd, (struct timezone *)NULL); 4193 timersub(&tv_odd, &tv_even, &tv_delta); 4194 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 4195 fprintf(outf, "%s: Counter reset detected\n", progname); 4196 else { 4197 compute_average(EVEN_COUNTERS); 4198 format_all_counters(EVEN_COUNTERS); 4199 } 4200 4201 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 4202 4203 flush_output_stderr(); 4204 4205 return status; 4206 } 4207 4208 int get_and_dump_counters(void) 4209 { 4210 int status; 4211 4212 status = for_all_cpus(get_counters, ODD_COUNTERS); 4213 if (status) 4214 return status; 4215 4216 status = for_all_cpus(dump_counters, ODD_COUNTERS); 4217 if (status) 4218 return status; 4219 4220 flush_output_stdout(); 4221 4222 return status; 4223 } 4224 4225 void print_version() { 4226 fprintf(outf, "turbostat version 4.17 10 Jan 2017" 4227 " - Len Brown <lenb@kernel.org>\n"); 4228 } 4229 4230 int add_counter(unsigned int msr_num, char *name, unsigned int width, 4231 enum counter_scope scope, enum counter_type type, 4232 enum counter_format format) 4233 { 4234 struct msr_counter *msrp; 4235 4236 msrp = calloc(1, sizeof(struct msr_counter)); 4237 if (msrp == NULL) { 4238 perror("calloc"); 4239 exit(1); 4240 } 4241 4242 msrp->msr_num = msr_num; 4243 strncpy(msrp->name, name, NAME_BYTES); 4244 msrp->width = width; 4245 msrp->type = type; 4246 msrp->format = format; 4247 4248 switch (scope) { 4249 4250 case SCOPE_CPU: 4251 msrp->next = sys.tp; 4252 sys.tp = msrp; 4253 sys.added_thread_counters++; 4254 if (sys.added_thread_counters > MAX_ADDED_COUNTERS) { 4255 fprintf(stderr, "exceeded max %d added thread counters\n", 4256 MAX_ADDED_COUNTERS); 4257 exit(-1); 4258 } 4259 break; 4260 4261 case SCOPE_CORE: 4262 msrp->next = sys.cp; 4263 sys.cp = msrp; 4264 sys.added_core_counters++; 4265 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 4266 fprintf(stderr, "exceeded max %d added core counters\n", 4267 MAX_ADDED_COUNTERS); 4268 exit(-1); 4269 } 4270 break; 4271 4272 case SCOPE_PACKAGE: 4273 msrp->next = sys.pp; 4274 sys.pp = msrp; 4275 sys.added_package_counters++; 4276 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 4277 fprintf(stderr, "exceeded max %d added package counters\n", 4278 MAX_ADDED_COUNTERS); 4279 exit(-1); 4280 } 4281 break; 4282 } 4283 4284 return 0; 4285 } 4286 4287 void parse_add_command(char *add_command) 4288 { 4289 int msr_num = 0; 4290 char name_buffer[NAME_BYTES]; 4291 int width = 64; 4292 int fail = 0; 4293 enum counter_scope scope = SCOPE_CPU; 4294 enum counter_type type = COUNTER_CYCLES; 4295 enum counter_format format = FORMAT_DELTA; 4296 4297 while (add_command) { 4298 4299 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 4300 goto next; 4301 4302 if (sscanf(add_command, "msr%d", &msr_num) == 1) 4303 goto next; 4304 4305 if (sscanf(add_command, "u%d", &width) == 1) { 4306 if ((width == 32) || (width == 64)) 4307 goto next; 4308 width = 64; 4309 } 4310 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 4311 scope = SCOPE_CPU; 4312 goto next; 4313 } 4314 if (!strncmp(add_command, "core", strlen("core"))) { 4315 scope = SCOPE_CORE; 4316 goto next; 4317 } 4318 if (!strncmp(add_command, "package", strlen("package"))) { 4319 scope = SCOPE_PACKAGE; 4320 goto next; 4321 } 4322 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 4323 type = COUNTER_CYCLES; 4324 goto next; 4325 } 4326 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 4327 type = COUNTER_SECONDS; 4328 goto next; 4329 } 4330 if (!strncmp(add_command, "raw", strlen("raw"))) { 4331 format = FORMAT_RAW; 4332 goto next; 4333 } 4334 if (!strncmp(add_command, "delta", strlen("delta"))) { 4335 format = FORMAT_DELTA; 4336 goto next; 4337 } 4338 if (!strncmp(add_command, "percent", strlen("percent"))) { 4339 format = FORMAT_PERCENT; 4340 goto next; 4341 } 4342 4343 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 4344 char *eos; 4345 4346 eos = strchr(name_buffer, ','); 4347 if (eos) 4348 *eos = '\0'; 4349 goto next; 4350 } 4351 4352 next: 4353 add_command = strchr(add_command, ','); 4354 if (add_command) 4355 add_command++; 4356 4357 } 4358 if (msr_num == 0) { 4359 fprintf(stderr, "--add: (msrDDD | msr0xXXX) required\n"); 4360 fail++; 4361 } 4362 4363 /* generate default column header */ 4364 if (*name_buffer == '\0') { 4365 if (format == FORMAT_RAW) { 4366 if (width == 32) 4367 sprintf(name_buffer, "msr%d", msr_num); 4368 else 4369 sprintf(name_buffer, "MSR%d", msr_num); 4370 } else if (format == FORMAT_DELTA) { 4371 if (width == 32) 4372 sprintf(name_buffer, "cnt%d", msr_num); 4373 else 4374 sprintf(name_buffer, "CNT%d", msr_num); 4375 } else if (format == FORMAT_PERCENT) { 4376 if (width == 32) 4377 sprintf(name_buffer, "msr%d%%", msr_num); 4378 else 4379 sprintf(name_buffer, "MSR%d%%", msr_num); 4380 } 4381 } 4382 4383 if (add_counter(msr_num, name_buffer, width, scope, type, format)) 4384 fail++; 4385 4386 if (fail) { 4387 help(); 4388 exit(1); 4389 } 4390 } 4391 /* 4392 * HIDE_LIST - hide this list of counters, show the rest [default] 4393 * SHOW_LIST - show this list of counters, hide the rest 4394 */ 4395 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 4396 4397 int shown; 4398 /* 4399 * parse_show_hide() - process cmdline to set default counter action 4400 */ 4401 void parse_show_hide(char *optarg, enum show_hide_mode new_mode) 4402 { 4403 /* 4404 * --show: show only those specified 4405 * The 1st invocation will clear and replace the enabled mask 4406 * subsequent invocations can add to it. 4407 */ 4408 if (new_mode == SHOW_LIST) { 4409 if (shown == 0) 4410 bic_enabled = bic_lookup(optarg); 4411 else 4412 bic_enabled |= bic_lookup(optarg); 4413 shown = 1; 4414 4415 return; 4416 } 4417 4418 /* 4419 * --hide: do not show those specified 4420 * multiple invocations simply clear more bits in enabled mask 4421 */ 4422 bic_enabled &= ~bic_lookup(optarg); 4423 } 4424 4425 void cmdline(int argc, char **argv) 4426 { 4427 int opt; 4428 int option_index = 0; 4429 static struct option long_options[] = { 4430 {"add", required_argument, 0, 'a'}, 4431 {"Dump", no_argument, 0, 'D'}, 4432 {"debug", no_argument, 0, 'd'}, 4433 {"interval", required_argument, 0, 'i'}, 4434 {"help", no_argument, 0, 'h'}, 4435 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help 4436 {"Joules", no_argument, 0, 'J'}, 4437 {"out", required_argument, 0, 'o'}, 4438 {"Package", no_argument, 0, 'p'}, 4439 {"processor", no_argument, 0, 'p'}, 4440 {"show", required_argument, 0, 's'}, 4441 {"Summary", no_argument, 0, 'S'}, 4442 {"TCC", required_argument, 0, 'T'}, 4443 {"version", no_argument, 0, 'v' }, 4444 {0, 0, 0, 0 } 4445 }; 4446 4447 progname = argv[0]; 4448 4449 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpST:v", 4450 long_options, &option_index)) != -1) { 4451 switch (opt) { 4452 case 'a': 4453 parse_add_command(optarg); 4454 break; 4455 case 'D': 4456 dump_only++; 4457 break; 4458 case 'd': 4459 debug++; 4460 break; 4461 case 'H': 4462 parse_show_hide(optarg, HIDE_LIST); 4463 break; 4464 case 'h': 4465 default: 4466 help(); 4467 exit(1); 4468 case 'i': 4469 { 4470 double interval = strtod(optarg, NULL); 4471 4472 if (interval < 0.001) { 4473 fprintf(outf, "interval %f seconds is too small\n", 4474 interval); 4475 exit(2); 4476 } 4477 4478 interval_ts.tv_sec = interval; 4479 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 4480 } 4481 break; 4482 case 'J': 4483 rapl_joules++; 4484 break; 4485 case 'o': 4486 outf = fopen_or_die(optarg, "w"); 4487 break; 4488 case 'P': 4489 show_pkg_only++; 4490 break; 4491 case 'p': 4492 show_core_only++; 4493 break; 4494 case 's': 4495 parse_show_hide(optarg, SHOW_LIST); 4496 break; 4497 case 'S': 4498 summary_only++; 4499 break; 4500 case 'T': 4501 tcc_activation_temp_override = atoi(optarg); 4502 break; 4503 case 'v': 4504 print_version(); 4505 exit(0); 4506 break; 4507 } 4508 } 4509 } 4510 4511 int main(int argc, char **argv) 4512 { 4513 outf = stderr; 4514 4515 cmdline(argc, argv); 4516 4517 if (debug) 4518 print_version(); 4519 4520 turbostat_init(); 4521 4522 /* dump counters and exit */ 4523 if (dump_only) 4524 return get_and_dump_counters(); 4525 4526 /* 4527 * if any params left, it must be a command to fork 4528 */ 4529 if (argc - optind) 4530 return fork_it(argv + optind); 4531 else 4532 turbostat_loop(); 4533 4534 return 0; 4535 } 4536