1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * turbostat -- show CPU frequency and C-state residency
4 * on modern Intel and AMD processors.
5 *
6 * Copyright (c) 2023 Intel Corporation.
7 * Len Brown <len.brown@intel.com>
8 */
9
10 #define _GNU_SOURCE
11 #include MSRHEADER
12 #include INTEL_FAMILY_HEADER
13 #include <stdarg.h>
14 #include <stdio.h>
15 #include <err.h>
16 #include <unistd.h>
17 #include <sys/types.h>
18 #include <sys/wait.h>
19 #include <sys/stat.h>
20 #include <sys/select.h>
21 #include <sys/resource.h>
22 #include <fcntl.h>
23 #include <signal.h>
24 #include <sys/time.h>
25 #include <stdlib.h>
26 #include <getopt.h>
27 #include <dirent.h>
28 #include <string.h>
29 #include <ctype.h>
30 #include <sched.h>
31 #include <time.h>
32 #include <cpuid.h>
33 #include <sys/capability.h>
34 #include <errno.h>
35 #include <math.h>
36 #include <linux/perf_event.h>
37 #include <asm/unistd.h>
38 #include <stdbool.h>
39
40 #define UNUSED(x) (void)(x)
41
42 /*
43 * This list matches the column headers, except
44 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time
45 * 2. Core and CPU are moved to the end, we can't have strings that contain them
46 * matching on them for --show and --hide.
47 */
48
49 /*
50 * buffer size used by sscanf() for added column names
51 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
52 */
53 #define NAME_BYTES 20
54 #define PATH_BYTES 128
55
56 #define MAX_NOFILE 0x8000
57
58 enum counter_scope { SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE };
59 enum counter_type { COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC };
60 enum counter_format { FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT };
61
62 struct msr_counter {
63 unsigned int msr_num;
64 char name[NAME_BYTES];
65 char path[PATH_BYTES];
66 unsigned int width;
67 enum counter_type type;
68 enum counter_format format;
69 struct msr_counter *next;
70 unsigned int flags;
71 #define FLAGS_HIDE (1 << 0)
72 #define FLAGS_SHOW (1 << 1)
73 #define SYSFS_PERCPU (1 << 1)
74 };
75
76 struct msr_counter bic[] = {
77 { 0x0, "usec", "", 0, 0, 0, NULL, 0 },
78 { 0x0, "Time_Of_Day_Seconds", "", 0, 0, 0, NULL, 0 },
79 { 0x0, "Package", "", 0, 0, 0, NULL, 0 },
80 { 0x0, "Node", "", 0, 0, 0, NULL, 0 },
81 { 0x0, "Avg_MHz", "", 0, 0, 0, NULL, 0 },
82 { 0x0, "Busy%", "", 0, 0, 0, NULL, 0 },
83 { 0x0, "Bzy_MHz", "", 0, 0, 0, NULL, 0 },
84 { 0x0, "TSC_MHz", "", 0, 0, 0, NULL, 0 },
85 { 0x0, "IRQ", "", 0, 0, 0, NULL, 0 },
86 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL, 0 },
87 { 0x0, "sysfs", "", 0, 0, 0, NULL, 0 },
88 { 0x0, "CPU%c1", "", 0, 0, 0, NULL, 0 },
89 { 0x0, "CPU%c3", "", 0, 0, 0, NULL, 0 },
90 { 0x0, "CPU%c6", "", 0, 0, 0, NULL, 0 },
91 { 0x0, "CPU%c7", "", 0, 0, 0, NULL, 0 },
92 { 0x0, "ThreadC", "", 0, 0, 0, NULL, 0 },
93 { 0x0, "CoreTmp", "", 0, 0, 0, NULL, 0 },
94 { 0x0, "CoreCnt", "", 0, 0, 0, NULL, 0 },
95 { 0x0, "PkgTmp", "", 0, 0, 0, NULL, 0 },
96 { 0x0, "GFX%rc6", "", 0, 0, 0, NULL, 0 },
97 { 0x0, "GFXMHz", "", 0, 0, 0, NULL, 0 },
98 { 0x0, "Pkg%pc2", "", 0, 0, 0, NULL, 0 },
99 { 0x0, "Pkg%pc3", "", 0, 0, 0, NULL, 0 },
100 { 0x0, "Pkg%pc6", "", 0, 0, 0, NULL, 0 },
101 { 0x0, "Pkg%pc7", "", 0, 0, 0, NULL, 0 },
102 { 0x0, "Pkg%pc8", "", 0, 0, 0, NULL, 0 },
103 { 0x0, "Pkg%pc9", "", 0, 0, 0, NULL, 0 },
104 { 0x0, "Pk%pc10", "", 0, 0, 0, NULL, 0 },
105 { 0x0, "CPU%LPI", "", 0, 0, 0, NULL, 0 },
106 { 0x0, "SYS%LPI", "", 0, 0, 0, NULL, 0 },
107 { 0x0, "PkgWatt", "", 0, 0, 0, NULL, 0 },
108 { 0x0, "CorWatt", "", 0, 0, 0, NULL, 0 },
109 { 0x0, "GFXWatt", "", 0, 0, 0, NULL, 0 },
110 { 0x0, "PkgCnt", "", 0, 0, 0, NULL, 0 },
111 { 0x0, "RAMWatt", "", 0, 0, 0, NULL, 0 },
112 { 0x0, "PKG_%", "", 0, 0, 0, NULL, 0 },
113 { 0x0, "RAM_%", "", 0, 0, 0, NULL, 0 },
114 { 0x0, "Pkg_J", "", 0, 0, 0, NULL, 0 },
115 { 0x0, "Cor_J", "", 0, 0, 0, NULL, 0 },
116 { 0x0, "GFX_J", "", 0, 0, 0, NULL, 0 },
117 { 0x0, "RAM_J", "", 0, 0, 0, NULL, 0 },
118 { 0x0, "Mod%c6", "", 0, 0, 0, NULL, 0 },
119 { 0x0, "Totl%C0", "", 0, 0, 0, NULL, 0 },
120 { 0x0, "Any%C0", "", 0, 0, 0, NULL, 0 },
121 { 0x0, "GFX%C0", "", 0, 0, 0, NULL, 0 },
122 { 0x0, "CPUGFX%", "", 0, 0, 0, NULL, 0 },
123 { 0x0, "Core", "", 0, 0, 0, NULL, 0 },
124 { 0x0, "CPU", "", 0, 0, 0, NULL, 0 },
125 { 0x0, "APIC", "", 0, 0, 0, NULL, 0 },
126 { 0x0, "X2APIC", "", 0, 0, 0, NULL, 0 },
127 { 0x0, "Die", "", 0, 0, 0, NULL, 0 },
128 { 0x0, "GFXAMHz", "", 0, 0, 0, NULL, 0 },
129 { 0x0, "IPC", "", 0, 0, 0, NULL, 0 },
130 { 0x0, "CoreThr", "", 0, 0, 0, NULL, 0 },
131 { 0x0, "UncMHz", "", 0, 0, 0, NULL, 0 },
132 };
133
134 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
135 #define BIC_USEC (1ULL << 0)
136 #define BIC_TOD (1ULL << 1)
137 #define BIC_Package (1ULL << 2)
138 #define BIC_Node (1ULL << 3)
139 #define BIC_Avg_MHz (1ULL << 4)
140 #define BIC_Busy (1ULL << 5)
141 #define BIC_Bzy_MHz (1ULL << 6)
142 #define BIC_TSC_MHz (1ULL << 7)
143 #define BIC_IRQ (1ULL << 8)
144 #define BIC_SMI (1ULL << 9)
145 #define BIC_sysfs (1ULL << 10)
146 #define BIC_CPU_c1 (1ULL << 11)
147 #define BIC_CPU_c3 (1ULL << 12)
148 #define BIC_CPU_c6 (1ULL << 13)
149 #define BIC_CPU_c7 (1ULL << 14)
150 #define BIC_ThreadC (1ULL << 15)
151 #define BIC_CoreTmp (1ULL << 16)
152 #define BIC_CoreCnt (1ULL << 17)
153 #define BIC_PkgTmp (1ULL << 18)
154 #define BIC_GFX_rc6 (1ULL << 19)
155 #define BIC_GFXMHz (1ULL << 20)
156 #define BIC_Pkgpc2 (1ULL << 21)
157 #define BIC_Pkgpc3 (1ULL << 22)
158 #define BIC_Pkgpc6 (1ULL << 23)
159 #define BIC_Pkgpc7 (1ULL << 24)
160 #define BIC_Pkgpc8 (1ULL << 25)
161 #define BIC_Pkgpc9 (1ULL << 26)
162 #define BIC_Pkgpc10 (1ULL << 27)
163 #define BIC_CPU_LPI (1ULL << 28)
164 #define BIC_SYS_LPI (1ULL << 29)
165 #define BIC_PkgWatt (1ULL << 30)
166 #define BIC_CorWatt (1ULL << 31)
167 #define BIC_GFXWatt (1ULL << 32)
168 #define BIC_PkgCnt (1ULL << 33)
169 #define BIC_RAMWatt (1ULL << 34)
170 #define BIC_PKG__ (1ULL << 35)
171 #define BIC_RAM__ (1ULL << 36)
172 #define BIC_Pkg_J (1ULL << 37)
173 #define BIC_Cor_J (1ULL << 38)
174 #define BIC_GFX_J (1ULL << 39)
175 #define BIC_RAM_J (1ULL << 40)
176 #define BIC_Mod_c6 (1ULL << 41)
177 #define BIC_Totl_c0 (1ULL << 42)
178 #define BIC_Any_c0 (1ULL << 43)
179 #define BIC_GFX_c0 (1ULL << 44)
180 #define BIC_CPUGFX (1ULL << 45)
181 #define BIC_Core (1ULL << 46)
182 #define BIC_CPU (1ULL << 47)
183 #define BIC_APIC (1ULL << 48)
184 #define BIC_X2APIC (1ULL << 49)
185 #define BIC_Die (1ULL << 50)
186 #define BIC_GFXACTMHz (1ULL << 51)
187 #define BIC_IPC (1ULL << 52)
188 #define BIC_CORE_THROT_CNT (1ULL << 53)
189 #define BIC_UNCORE_MHZ (1ULL << 54)
190
191 #define BIC_TOPOLOGY (BIC_Package | BIC_Node | BIC_CoreCnt | BIC_PkgCnt | BIC_Core | BIC_CPU | BIC_Die )
192 #define BIC_THERMAL_PWR ( BIC_CoreTmp | BIC_PkgTmp | BIC_PkgWatt | BIC_CorWatt | BIC_GFXWatt | BIC_RAMWatt | BIC_PKG__ | BIC_RAM__)
193 #define BIC_FREQUENCY ( BIC_Avg_MHz | BIC_Busy | BIC_Bzy_MHz | BIC_TSC_MHz | BIC_GFXMHz | BIC_GFXACTMHz | BIC_UNCORE_MHZ)
194 #define BIC_IDLE ( BIC_sysfs | BIC_CPU_c1 | BIC_CPU_c3 | BIC_CPU_c6 | BIC_CPU_c7 | BIC_GFX_rc6 | BIC_Pkgpc2 | BIC_Pkgpc3 | BIC_Pkgpc6 | BIC_Pkgpc7 | BIC_Pkgpc8 | BIC_Pkgpc9 | BIC_Pkgpc10 | BIC_CPU_LPI | BIC_SYS_LPI | BIC_Mod_c6 | BIC_Totl_c0 | BIC_Any_c0 | BIC_GFX_c0 | BIC_CPUGFX)
195 #define BIC_OTHER ( BIC_IRQ | BIC_SMI | BIC_ThreadC | BIC_CoreTmp | BIC_IPC)
196
197 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC)
198
199 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT);
200 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC;
201
202 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
203 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME)
204 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME)
205 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
206 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT)
207 #define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT)
208
209 char *proc_stat = "/proc/stat";
210 FILE *outf;
211 int *fd_percpu;
212 int *fd_instr_count_percpu;
213 struct timeval interval_tv = { 5, 0 };
214 struct timespec interval_ts = { 5, 0 };
215
216 /* Save original CPU model */
217 unsigned int model_orig;
218
219 unsigned int num_iterations;
220 unsigned int header_iterations;
221 unsigned int debug;
222 unsigned int quiet;
223 unsigned int shown;
224 unsigned int sums_need_wide_columns;
225 unsigned int rapl_joules;
226 unsigned int summary_only;
227 unsigned int list_header_only;
228 unsigned int dump_only;
229 unsigned int do_snb_cstates;
230 unsigned int do_knl_cstates;
231 unsigned int do_slm_cstates;
232 unsigned int use_c1_residency_msr;
233 unsigned int has_aperf;
234 unsigned int has_epb;
235 unsigned int has_turbo;
236 unsigned int is_hybrid;
237 unsigned int do_irtl_snb;
238 unsigned int do_irtl_hsw;
239 unsigned int units = 1000000; /* MHz etc */
240 unsigned int genuine_intel;
241 unsigned int authentic_amd;
242 unsigned int hygon_genuine;
243 unsigned int max_level, max_extended_level;
244 unsigned int has_invariant_tsc;
245 unsigned int do_nhm_platform_info;
246 unsigned int no_MSR_MISC_PWR_MGMT;
247 unsigned int aperf_mperf_multiplier = 1;
248 double bclk;
249 double base_hz;
250 unsigned int has_base_hz;
251 double tsc_tweak = 1.0;
252 unsigned int show_pkg_only;
253 unsigned int show_core_only;
254 char *output_buffer, *outp;
255 unsigned int do_rapl;
256 unsigned int do_dts;
257 unsigned int do_ptm;
258 unsigned int do_ipc;
259 unsigned long long gfx_cur_rc6_ms;
260 unsigned long long cpuidle_cur_cpu_lpi_us;
261 unsigned long long cpuidle_cur_sys_lpi_us;
262 unsigned int gfx_cur_mhz;
263 unsigned int gfx_act_mhz;
264 unsigned int tj_max;
265 unsigned int tj_max_override;
266 int tcc_offset_bits;
267 double rapl_power_units, rapl_time_units;
268 double rapl_dram_energy_units, rapl_energy_units;
269 double rapl_joule_counter_range;
270 unsigned int do_core_perf_limit_reasons;
271 unsigned int has_automatic_cstate_conversion;
272 unsigned int dis_cstate_prewake;
273 unsigned int do_gfx_perf_limit_reasons;
274 unsigned int do_ring_perf_limit_reasons;
275 unsigned int crystal_hz;
276 unsigned long long tsc_hz;
277 int base_cpu;
278 double discover_bclk(unsigned int family, unsigned int model);
279 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
280 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
281 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
282 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
283 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
284 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
285 unsigned int has_misc_feature_control;
286 unsigned int first_counter_read = 1;
287 int ignore_stdin;
288
289 #define RAPL_PKG (1 << 0)
290 /* 0x610 MSR_PKG_POWER_LIMIT */
291 /* 0x611 MSR_PKG_ENERGY_STATUS */
292 #define RAPL_PKG_PERF_STATUS (1 << 1)
293 /* 0x613 MSR_PKG_PERF_STATUS */
294 #define RAPL_PKG_POWER_INFO (1 << 2)
295 /* 0x614 MSR_PKG_POWER_INFO */
296
297 #define RAPL_DRAM (1 << 3)
298 /* 0x618 MSR_DRAM_POWER_LIMIT */
299 /* 0x619 MSR_DRAM_ENERGY_STATUS */
300 #define RAPL_DRAM_PERF_STATUS (1 << 4)
301 /* 0x61b MSR_DRAM_PERF_STATUS */
302 #define RAPL_DRAM_POWER_INFO (1 << 5)
303 /* 0x61c MSR_DRAM_POWER_INFO */
304
305 #define RAPL_CORES_POWER_LIMIT (1 << 6)
306 /* 0x638 MSR_PP0_POWER_LIMIT */
307 #define RAPL_CORE_POLICY (1 << 7)
308 /* 0x63a MSR_PP0_POLICY */
309
310 #define RAPL_GFX (1 << 8)
311 /* 0x640 MSR_PP1_POWER_LIMIT */
312 /* 0x641 MSR_PP1_ENERGY_STATUS */
313 /* 0x642 MSR_PP1_POLICY */
314
315 #define RAPL_CORES_ENERGY_STATUS (1 << 9)
316 /* 0x639 MSR_PP0_ENERGY_STATUS */
317 #define RAPL_PER_CORE_ENERGY (1 << 10)
318 /* Indicates cores energy collection is per-core,
319 * not per-package. */
320 #define RAPL_AMD_F17H (1 << 11)
321 /* 0xc0010299 MSR_RAPL_PWR_UNIT */
322 /* 0xc001029a MSR_CORE_ENERGY_STAT */
323 /* 0xc001029b MSR_PKG_ENERGY_STAT */
324 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
325 #define TJMAX_DEFAULT 100
326
327 /* MSRs that are not yet in the kernel-provided header. */
328 #define MSR_RAPL_PWR_UNIT 0xc0010299
329 #define MSR_CORE_ENERGY_STAT 0xc001029a
330 #define MSR_PKG_ENERGY_STAT 0xc001029b
331
332 #define MAX(a, b) ((a) > (b) ? (a) : (b))
333
334 int backwards_count;
335 char *progname;
336
337 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */
338 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset;
339 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size;
340 #define MAX_ADDED_COUNTERS 8
341 #define MAX_ADDED_THREAD_COUNTERS 24
342 #define BITMASK_SIZE 32
343
344 struct thread_data {
345 struct timeval tv_begin;
346 struct timeval tv_end;
347 struct timeval tv_delta;
348 unsigned long long tsc;
349 unsigned long long aperf;
350 unsigned long long mperf;
351 unsigned long long c1;
352 unsigned long long instr_count;
353 unsigned long long irq_count;
354 unsigned int smi_count;
355 unsigned int cpu_id;
356 unsigned int apic_id;
357 unsigned int x2apic_id;
358 unsigned int flags;
359 bool is_atom;
360 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2
361 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
362 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS];
363 } *thread_even, *thread_odd;
364
365 struct core_data {
366 unsigned long long c3;
367 unsigned long long c6;
368 unsigned long long c7;
369 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
370 unsigned int core_temp_c;
371 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */
372 unsigned int core_id;
373 unsigned long long core_throt_cnt;
374 unsigned long long counter[MAX_ADDED_COUNTERS];
375 } *core_even, *core_odd;
376
377 struct pkg_data {
378 unsigned long long pc2;
379 unsigned long long pc3;
380 unsigned long long pc6;
381 unsigned long long pc7;
382 unsigned long long pc8;
383 unsigned long long pc9;
384 unsigned long long pc10;
385 unsigned long long cpu_lpi;
386 unsigned long long sys_lpi;
387 unsigned long long pkg_wtd_core_c0;
388 unsigned long long pkg_any_core_c0;
389 unsigned long long pkg_any_gfxe_c0;
390 unsigned long long pkg_both_core_gfxe_c0;
391 long long gfx_rc6_ms;
392 unsigned int gfx_mhz;
393 unsigned int gfx_act_mhz;
394 unsigned int package_id;
395 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */
396 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */
397 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */
398 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */
399 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
400 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
401 unsigned int pkg_temp_c;
402 unsigned int uncore_mhz;
403 unsigned long long counter[MAX_ADDED_COUNTERS];
404 } *package_even, *package_odd;
405
406 #define ODD_COUNTERS thread_odd, core_odd, package_odd
407 #define EVEN_COUNTERS thread_even, core_even, package_even
408
409 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \
410 ((thread_base) + \
411 ((pkg_no) * \
412 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \
413 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \
414 ((core_no) * topo.threads_per_core) + \
415 (thread_no))
416
417 #define GET_CORE(core_base, core_no, node_no, pkg_no) \
418 ((core_base) + \
419 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \
420 ((node_no) * topo.cores_per_node) + \
421 (core_no))
422
423 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
424
425 /*
426 * The accumulated sum of MSR is defined as a monotonic
427 * increasing MSR, it will be accumulated periodically,
428 * despite its register's bit width.
429 */
430 enum {
431 IDX_PKG_ENERGY,
432 IDX_DRAM_ENERGY,
433 IDX_PP0_ENERGY,
434 IDX_PP1_ENERGY,
435 IDX_PKG_PERF,
436 IDX_DRAM_PERF,
437 IDX_COUNT,
438 };
439
440 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr);
441
442 struct msr_sum_array {
443 /* get_msr_sum() = sum + (get_msr() - last) */
444 struct {
445 /*The accumulated MSR value is updated by the timer */
446 unsigned long long sum;
447 /*The MSR footprint recorded in last timer */
448 unsigned long long last;
449 } entries[IDX_COUNT];
450 };
451
452 /* The percpu MSR sum array.*/
453 struct msr_sum_array *per_cpu_msr_sum;
454
idx_to_offset(int idx)455 off_t idx_to_offset(int idx)
456 {
457 off_t offset;
458
459 switch (idx) {
460 case IDX_PKG_ENERGY:
461 if (do_rapl & RAPL_AMD_F17H)
462 offset = MSR_PKG_ENERGY_STAT;
463 else
464 offset = MSR_PKG_ENERGY_STATUS;
465 break;
466 case IDX_DRAM_ENERGY:
467 offset = MSR_DRAM_ENERGY_STATUS;
468 break;
469 case IDX_PP0_ENERGY:
470 offset = MSR_PP0_ENERGY_STATUS;
471 break;
472 case IDX_PP1_ENERGY:
473 offset = MSR_PP1_ENERGY_STATUS;
474 break;
475 case IDX_PKG_PERF:
476 offset = MSR_PKG_PERF_STATUS;
477 break;
478 case IDX_DRAM_PERF:
479 offset = MSR_DRAM_PERF_STATUS;
480 break;
481 default:
482 offset = -1;
483 }
484 return offset;
485 }
486
offset_to_idx(off_t offset)487 int offset_to_idx(off_t offset)
488 {
489 int idx;
490
491 switch (offset) {
492 case MSR_PKG_ENERGY_STATUS:
493 case MSR_PKG_ENERGY_STAT:
494 idx = IDX_PKG_ENERGY;
495 break;
496 case MSR_DRAM_ENERGY_STATUS:
497 idx = IDX_DRAM_ENERGY;
498 break;
499 case MSR_PP0_ENERGY_STATUS:
500 idx = IDX_PP0_ENERGY;
501 break;
502 case MSR_PP1_ENERGY_STATUS:
503 idx = IDX_PP1_ENERGY;
504 break;
505 case MSR_PKG_PERF_STATUS:
506 idx = IDX_PKG_PERF;
507 break;
508 case MSR_DRAM_PERF_STATUS:
509 idx = IDX_DRAM_PERF;
510 break;
511 default:
512 idx = -1;
513 }
514 return idx;
515 }
516
idx_valid(int idx)517 int idx_valid(int idx)
518 {
519 switch (idx) {
520 case IDX_PKG_ENERGY:
521 return do_rapl & (RAPL_PKG | RAPL_AMD_F17H);
522 case IDX_DRAM_ENERGY:
523 return do_rapl & RAPL_DRAM;
524 case IDX_PP0_ENERGY:
525 return do_rapl & RAPL_CORES_ENERGY_STATUS;
526 case IDX_PP1_ENERGY:
527 return do_rapl & RAPL_GFX;
528 case IDX_PKG_PERF:
529 return do_rapl & RAPL_PKG_PERF_STATUS;
530 case IDX_DRAM_PERF:
531 return do_rapl & RAPL_DRAM_PERF_STATUS;
532 default:
533 return 0;
534 }
535 }
536
537 struct sys_counters {
538 unsigned int added_thread_counters;
539 unsigned int added_core_counters;
540 unsigned int added_package_counters;
541 struct msr_counter *tp;
542 struct msr_counter *cp;
543 struct msr_counter *pp;
544 } sys;
545
546 struct system_summary {
547 struct thread_data threads;
548 struct core_data cores;
549 struct pkg_data packages;
550 } average;
551
552 struct cpu_topology {
553 int physical_package_id;
554 int die_id;
555 int logical_cpu_id;
556 int physical_node_id;
557 int logical_node_id; /* 0-based count within the package */
558 int physical_core_id;
559 int thread_id;
560 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */
561 } *cpus;
562
563 struct topo_params {
564 int num_packages;
565 int num_die;
566 int num_cpus;
567 int num_cores;
568 int max_cpu_num;
569 int max_node_num;
570 int nodes_per_pkg;
571 int cores_per_node;
572 int threads_per_core;
573 } topo;
574
575 struct timeval tv_even, tv_odd, tv_delta;
576
577 int *irq_column_2_cpu; /* /proc/interrupts column numbers */
578 int *irqs_per_cpu; /* indexed by cpu_num */
579
580 void setup_all_buffers(void);
581
582 char *sys_lpi_file;
583 char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us";
584 char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec";
585
cpu_is_not_present(int cpu)586 int cpu_is_not_present(int cpu)
587 {
588 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
589 }
590
591 /*
592 * run func(thread, core, package) in topology order
593 * skip non-present cpus
594 */
595
for_all_cpus(int (func)(struct thread_data *,struct core_data *,struct pkg_data *),struct thread_data * thread_base,struct core_data * core_base,struct pkg_data * pkg_base)596 int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *),
597 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
598 {
599 int retval, pkg_no, core_no, thread_no, node_no;
600
601 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
602 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) {
603 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
604 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
605 struct thread_data *t;
606 struct core_data *c;
607 struct pkg_data *p;
608
609 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
610
611 if (cpu_is_not_present(t->cpu_id))
612 continue;
613
614 c = GET_CORE(core_base, core_no, node_no, pkg_no);
615 p = GET_PKG(pkg_base, pkg_no);
616
617 retval = func(t, c, p);
618 if (retval)
619 return retval;
620 }
621 }
622 }
623 }
624 return 0;
625 }
626
cpu_migrate(int cpu)627 int cpu_migrate(int cpu)
628 {
629 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
630 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
631 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
632 return -1;
633 else
634 return 0;
635 }
636
get_msr_fd(int cpu)637 int get_msr_fd(int cpu)
638 {
639 char pathname[32];
640 int fd;
641
642 fd = fd_percpu[cpu];
643
644 if (fd)
645 return fd;
646
647 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
648 fd = open(pathname, O_RDONLY);
649 if (fd < 0)
650 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
651
652 fd_percpu[cpu] = fd;
653
654 return fd;
655 }
656
perf_event_open(struct perf_event_attr * hw_event,pid_t pid,int cpu,int group_fd,unsigned long flags)657 static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags)
658 {
659 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags);
660 }
661
perf_instr_count_open(int cpu_num)662 static int perf_instr_count_open(int cpu_num)
663 {
664 struct perf_event_attr pea;
665 int fd;
666
667 memset(&pea, 0, sizeof(struct perf_event_attr));
668 pea.type = PERF_TYPE_HARDWARE;
669 pea.size = sizeof(struct perf_event_attr);
670 pea.config = PERF_COUNT_HW_INSTRUCTIONS;
671
672 /* counter for cpu_num, including user + kernel and all processes */
673 fd = perf_event_open(&pea, -1, cpu_num, -1, 0);
674 if (fd == -1) {
675 warnx("capget(CAP_PERFMON) failed, try \"# setcap cap_sys_admin=ep %s\"", progname);
676 BIC_NOT_PRESENT(BIC_IPC);
677 }
678
679 return fd;
680 }
681
get_instr_count_fd(int cpu)682 int get_instr_count_fd(int cpu)
683 {
684 if (fd_instr_count_percpu[cpu])
685 return fd_instr_count_percpu[cpu];
686
687 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu);
688
689 return fd_instr_count_percpu[cpu];
690 }
691
get_msr(int cpu,off_t offset,unsigned long long * msr)692 int get_msr(int cpu, off_t offset, unsigned long long *msr)
693 {
694 ssize_t retval;
695
696 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
697
698 if (retval != sizeof *msr)
699 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
700
701 return 0;
702 }
703
704 #define MAX_DEFERRED 16
705 char *deferred_add_names[MAX_DEFERRED];
706 char *deferred_skip_names[MAX_DEFERRED];
707 int deferred_add_index;
708 int deferred_skip_index;
709
710 /*
711 * HIDE_LIST - hide this list of counters, show the rest [default]
712 * SHOW_LIST - show this list of counters, hide the rest
713 */
714 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
715
help(void)716 void help(void)
717 {
718 fprintf(outf,
719 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
720 "\n"
721 "Turbostat forks the specified COMMAND and prints statistics\n"
722 "when COMMAND completes.\n"
723 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
724 "to print statistics, until interrupted.\n"
725 " -a, --add add a counter\n"
726 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
727 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n"
728 " {core | package | j,k,l..m,n-p }\n"
729 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n"
730 " -D, --Dump displays the raw counter values\n"
731 " -e, --enable [all | column]\n"
732 " shows all or the specified disabled column\n"
733 " -H, --hide [column|column,column,...]\n"
734 " hide the specified column(s)\n"
735 " -i, --interval sec.subsec\n"
736 " Override default 5-second measurement interval\n"
737 " -J, --Joules displays energy in Joules instead of Watts\n"
738 " -l, --list list column headers only\n"
739 " -n, --num_iterations num\n"
740 " number of the measurement iterations\n"
741 " -N, --header_iterations num\n"
742 " print header every num iterations\n"
743 " -o, --out file\n"
744 " create or truncate \"file\" for all output\n"
745 " -q, --quiet skip decoding system configuration header\n"
746 " -s, --show [column|column,column,...]\n"
747 " show only the specified column(s)\n"
748 " -S, --Summary\n"
749 " limits output to 1-line system summary per interval\n"
750 " -T, --TCC temperature\n"
751 " sets the Thermal Control Circuit temperature in\n"
752 " degrees Celsius\n"
753 " -h, --help print this help message\n"
754 " -v, --version print version information\n" "\n" "For more help, run \"man turbostat\"\n");
755 }
756
757 /*
758 * bic_lookup
759 * for all the strings in comma separate name_list,
760 * set the approprate bit in return value.
761 */
bic_lookup(char * name_list,enum show_hide_mode mode)762 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode)
763 {
764 unsigned int i;
765 unsigned long long retval = 0;
766
767 while (name_list) {
768 char *comma;
769
770 comma = strchr(name_list, ',');
771
772 if (comma)
773 *comma = '\0';
774
775 for (i = 0; i < MAX_BIC; ++i) {
776 if (!strcmp(name_list, bic[i].name)) {
777 retval |= (1ULL << i);
778 break;
779 }
780 if (!strcmp(name_list, "all")) {
781 retval |= ~0;
782 break;
783 } else if (!strcmp(name_list, "topology")) {
784 retval |= BIC_TOPOLOGY;
785 break;
786 } else if (!strcmp(name_list, "power")) {
787 retval |= BIC_THERMAL_PWR;
788 break;
789 } else if (!strcmp(name_list, "idle")) {
790 retval |= BIC_IDLE;
791 break;
792 } else if (!strcmp(name_list, "frequency")) {
793 retval |= BIC_FREQUENCY;
794 break;
795 } else if (!strcmp(name_list, "other")) {
796 retval |= BIC_OTHER;
797 break;
798 }
799
800 }
801 if (i == MAX_BIC) {
802 if (mode == SHOW_LIST) {
803 deferred_add_names[deferred_add_index++] = name_list;
804 if (deferred_add_index >= MAX_DEFERRED) {
805 fprintf(stderr, "More than max %d un-recognized --add options '%s'\n",
806 MAX_DEFERRED, name_list);
807 help();
808 exit(1);
809 }
810 } else {
811 deferred_skip_names[deferred_skip_index++] = name_list;
812 if (debug)
813 fprintf(stderr, "deferred \"%s\"\n", name_list);
814 if (deferred_skip_index >= MAX_DEFERRED) {
815 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n",
816 MAX_DEFERRED, name_list);
817 help();
818 exit(1);
819 }
820 }
821 }
822
823 name_list = comma;
824 if (name_list)
825 name_list++;
826
827 }
828 return retval;
829 }
830
print_header(char * delim)831 void print_header(char *delim)
832 {
833 struct msr_counter *mp;
834 int printed = 0;
835
836 if (DO_BIC(BIC_USEC))
837 outp += sprintf(outp, "%susec", (printed++ ? delim : ""));
838 if (DO_BIC(BIC_TOD))
839 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : ""));
840 if (DO_BIC(BIC_Package))
841 outp += sprintf(outp, "%sPackage", (printed++ ? delim : ""));
842 if (DO_BIC(BIC_Die))
843 outp += sprintf(outp, "%sDie", (printed++ ? delim : ""));
844 if (DO_BIC(BIC_Node))
845 outp += sprintf(outp, "%sNode", (printed++ ? delim : ""));
846 if (DO_BIC(BIC_Core))
847 outp += sprintf(outp, "%sCore", (printed++ ? delim : ""));
848 if (DO_BIC(BIC_CPU))
849 outp += sprintf(outp, "%sCPU", (printed++ ? delim : ""));
850 if (DO_BIC(BIC_APIC))
851 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : ""));
852 if (DO_BIC(BIC_X2APIC))
853 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : ""));
854 if (DO_BIC(BIC_Avg_MHz))
855 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : ""));
856 if (DO_BIC(BIC_Busy))
857 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : ""));
858 if (DO_BIC(BIC_Bzy_MHz))
859 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : ""));
860 if (DO_BIC(BIC_TSC_MHz))
861 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : ""));
862
863 if (DO_BIC(BIC_IPC))
864 outp += sprintf(outp, "%sIPC", (printed++ ? delim : ""));
865
866 if (DO_BIC(BIC_IRQ)) {
867 if (sums_need_wide_columns)
868 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : ""));
869 else
870 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : ""));
871 }
872
873 if (DO_BIC(BIC_SMI))
874 outp += sprintf(outp, "%sSMI", (printed++ ? delim : ""));
875
876 for (mp = sys.tp; mp; mp = mp->next) {
877
878 if (mp->format == FORMAT_RAW) {
879 if (mp->width == 64)
880 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name);
881 else
882 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name);
883 } else {
884 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
885 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name);
886 else
887 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name);
888 }
889 }
890
891 if (DO_BIC(BIC_CPU_c1))
892 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : ""));
893 if (DO_BIC(BIC_CPU_c3))
894 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : ""));
895 if (DO_BIC(BIC_CPU_c6))
896 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : ""));
897 if (DO_BIC(BIC_CPU_c7))
898 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : ""));
899
900 if (DO_BIC(BIC_Mod_c6))
901 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : ""));
902
903 if (DO_BIC(BIC_CoreTmp))
904 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : ""));
905
906 if (DO_BIC(BIC_CORE_THROT_CNT))
907 outp += sprintf(outp, "%sCoreThr", (printed++ ? delim : ""));
908
909 if (do_rapl && !rapl_joules) {
910 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
911 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
912 } else if (do_rapl && rapl_joules) {
913 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
914 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
915 }
916
917 for (mp = sys.cp; mp; mp = mp->next) {
918 if (mp->format == FORMAT_RAW) {
919 if (mp->width == 64)
920 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
921 else
922 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
923 } else {
924 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
925 outp += sprintf(outp, "%s%8s", delim, mp->name);
926 else
927 outp += sprintf(outp, "%s%s", delim, mp->name);
928 }
929 }
930
931 if (DO_BIC(BIC_PkgTmp))
932 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : ""));
933
934 if (DO_BIC(BIC_GFX_rc6))
935 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : ""));
936
937 if (DO_BIC(BIC_GFXMHz))
938 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : ""));
939
940 if (DO_BIC(BIC_GFXACTMHz))
941 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : ""));
942
943 if (DO_BIC(BIC_Totl_c0))
944 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : ""));
945 if (DO_BIC(BIC_Any_c0))
946 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : ""));
947 if (DO_BIC(BIC_GFX_c0))
948 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : ""));
949 if (DO_BIC(BIC_CPUGFX))
950 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : ""));
951
952 if (DO_BIC(BIC_Pkgpc2))
953 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : ""));
954 if (DO_BIC(BIC_Pkgpc3))
955 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : ""));
956 if (DO_BIC(BIC_Pkgpc6))
957 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : ""));
958 if (DO_BIC(BIC_Pkgpc7))
959 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : ""));
960 if (DO_BIC(BIC_Pkgpc8))
961 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : ""));
962 if (DO_BIC(BIC_Pkgpc9))
963 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : ""));
964 if (DO_BIC(BIC_Pkgpc10))
965 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : ""));
966 if (DO_BIC(BIC_CPU_LPI))
967 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : ""));
968 if (DO_BIC(BIC_SYS_LPI))
969 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : ""));
970
971 if (do_rapl && !rapl_joules) {
972 if (DO_BIC(BIC_PkgWatt))
973 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : ""));
974 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
975 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
976 if (DO_BIC(BIC_GFXWatt))
977 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : ""));
978 if (DO_BIC(BIC_RAMWatt))
979 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : ""));
980 if (DO_BIC(BIC_PKG__))
981 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
982 if (DO_BIC(BIC_RAM__))
983 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
984 } else if (do_rapl && rapl_joules) {
985 if (DO_BIC(BIC_Pkg_J))
986 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : ""));
987 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
988 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
989 if (DO_BIC(BIC_GFX_J))
990 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : ""));
991 if (DO_BIC(BIC_RAM_J))
992 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : ""));
993 if (DO_BIC(BIC_PKG__))
994 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
995 if (DO_BIC(BIC_RAM__))
996 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
997 }
998 if (DO_BIC(BIC_UNCORE_MHZ))
999 outp += sprintf(outp, "%sUncMHz", (printed++ ? delim : ""));
1000
1001 for (mp = sys.pp; mp; mp = mp->next) {
1002 if (mp->format == FORMAT_RAW) {
1003 if (mp->width == 64)
1004 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
1005 else
1006 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
1007 } else {
1008 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1009 outp += sprintf(outp, "%s%8s", delim, mp->name);
1010 else
1011 outp += sprintf(outp, "%s%s", delim, mp->name);
1012 }
1013 }
1014
1015 outp += sprintf(outp, "\n");
1016 }
1017
dump_counters(struct thread_data * t,struct core_data * c,struct pkg_data * p)1018 int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1019 {
1020 int i;
1021 struct msr_counter *mp;
1022
1023 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
1024
1025 if (t) {
1026 outp += sprintf(outp, "CPU: %d flags 0x%x\n", t->cpu_id, t->flags);
1027 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
1028 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
1029 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
1030 outp += sprintf(outp, "c1: %016llX\n", t->c1);
1031
1032 if (DO_BIC(BIC_IPC))
1033 outp += sprintf(outp, "IPC: %lld\n", t->instr_count);
1034
1035 if (DO_BIC(BIC_IRQ))
1036 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count);
1037 if (DO_BIC(BIC_SMI))
1038 outp += sprintf(outp, "SMI: %d\n", t->smi_count);
1039
1040 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1041 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, t->counter[i]);
1042 }
1043 }
1044
1045 if (c) {
1046 outp += sprintf(outp, "core: %d\n", c->core_id);
1047 outp += sprintf(outp, "c3: %016llX\n", c->c3);
1048 outp += sprintf(outp, "c6: %016llX\n", c->c6);
1049 outp += sprintf(outp, "c7: %016llX\n", c->c7);
1050 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
1051 outp += sprintf(outp, "cpu_throt_count: %016llX\n", c->core_throt_cnt);
1052 outp += sprintf(outp, "Joules: %0X\n", c->core_energy);
1053
1054 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1055 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, c->counter[i]);
1056 }
1057 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
1058 }
1059
1060 if (p) {
1061 outp += sprintf(outp, "package: %d\n", p->package_id);
1062
1063 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
1064 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
1065 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
1066 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
1067
1068 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
1069 if (DO_BIC(BIC_Pkgpc3))
1070 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
1071 if (DO_BIC(BIC_Pkgpc6))
1072 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
1073 if (DO_BIC(BIC_Pkgpc7))
1074 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
1075 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
1076 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
1077 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
1078 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi);
1079 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi);
1080 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg);
1081 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores);
1082 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx);
1083 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram);
1084 outp += sprintf(outp, "Throttle PKG: %0llX\n", p->rapl_pkg_perf_status);
1085 outp += sprintf(outp, "Throttle RAM: %0llX\n", p->rapl_dram_perf_status);
1086 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
1087
1088 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1089 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, p->counter[i]);
1090 }
1091 }
1092
1093 outp += sprintf(outp, "\n");
1094
1095 return 0;
1096 }
1097
1098 /*
1099 * column formatting convention & formats
1100 */
format_counters(struct thread_data * t,struct core_data * c,struct pkg_data * p)1101 int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1102 {
1103 double interval_float, tsc;
1104 char *fmt8;
1105 int i;
1106 struct msr_counter *mp;
1107 char *delim = "\t";
1108 int printed = 0;
1109
1110 /* if showing only 1st thread in core and this isn't one, bail out */
1111 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1112 return 0;
1113
1114 /* if showing only 1st thread in pkg and this isn't one, bail out */
1115 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1116 return 0;
1117
1118 /*if not summary line and --cpu is used */
1119 if ((t != &average.threads) && (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset)))
1120 return 0;
1121
1122 if (DO_BIC(BIC_USEC)) {
1123 /* on each row, print how many usec each timestamp took to gather */
1124 struct timeval tv;
1125
1126 timersub(&t->tv_end, &t->tv_begin, &tv);
1127 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec);
1128 }
1129
1130 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */
1131 if (DO_BIC(BIC_TOD))
1132 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec);
1133
1134 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec / 1000000.0;
1135
1136 tsc = t->tsc * tsc_tweak;
1137
1138 /* topo columns, print blanks on 1st (average) line */
1139 if (t == &average.threads) {
1140 if (DO_BIC(BIC_Package))
1141 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1142 if (DO_BIC(BIC_Die))
1143 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1144 if (DO_BIC(BIC_Node))
1145 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1146 if (DO_BIC(BIC_Core))
1147 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1148 if (DO_BIC(BIC_CPU))
1149 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1150 if (DO_BIC(BIC_APIC))
1151 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1152 if (DO_BIC(BIC_X2APIC))
1153 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1154 } else {
1155 if (DO_BIC(BIC_Package)) {
1156 if (p)
1157 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id);
1158 else
1159 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1160 }
1161 if (DO_BIC(BIC_Die)) {
1162 if (c)
1163 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id);
1164 else
1165 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1166 }
1167 if (DO_BIC(BIC_Node)) {
1168 if (t)
1169 outp += sprintf(outp, "%s%d",
1170 (printed++ ? delim : ""), cpus[t->cpu_id].physical_node_id);
1171 else
1172 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1173 }
1174 if (DO_BIC(BIC_Core)) {
1175 if (c)
1176 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id);
1177 else
1178 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1179 }
1180 if (DO_BIC(BIC_CPU))
1181 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id);
1182 if (DO_BIC(BIC_APIC))
1183 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id);
1184 if (DO_BIC(BIC_X2APIC))
1185 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id);
1186 }
1187
1188 if (DO_BIC(BIC_Avg_MHz))
1189 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 / units * t->aperf / interval_float);
1190
1191 if (DO_BIC(BIC_Busy))
1192 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf / tsc);
1193
1194 if (DO_BIC(BIC_Bzy_MHz)) {
1195 if (has_base_hz)
1196 outp +=
1197 sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf);
1198 else
1199 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""),
1200 tsc / units * t->aperf / t->mperf / interval_float);
1201 }
1202
1203 if (DO_BIC(BIC_TSC_MHz))
1204 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc / units / interval_float);
1205
1206 if (DO_BIC(BIC_IPC))
1207 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf);
1208
1209 /* IRQ */
1210 if (DO_BIC(BIC_IRQ)) {
1211 if (sums_need_wide_columns)
1212 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count);
1213 else
1214 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count);
1215 }
1216
1217 /* SMI */
1218 if (DO_BIC(BIC_SMI))
1219 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count);
1220
1221 /* Added counters */
1222 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1223 if (mp->format == FORMAT_RAW) {
1224 if (mp->width == 32)
1225 outp +=
1226 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]);
1227 else
1228 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]);
1229 } else if (mp->format == FORMAT_DELTA) {
1230 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1231 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]);
1232 else
1233 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]);
1234 } else if (mp->format == FORMAT_PERCENT) {
1235 if (mp->type == COUNTER_USEC)
1236 outp +=
1237 sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1238 t->counter[i] / interval_float / 10000);
1239 else
1240 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i] / tsc);
1241 }
1242 }
1243
1244 /* C1 */
1245 if (DO_BIC(BIC_CPU_c1))
1246 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1 / tsc);
1247
1248 /* print per-core data only for 1st thread in core */
1249 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1250 goto done;
1251
1252 if (DO_BIC(BIC_CPU_c3))
1253 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3 / tsc);
1254 if (DO_BIC(BIC_CPU_c6))
1255 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6 / tsc);
1256 if (DO_BIC(BIC_CPU_c7))
1257 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7 / tsc);
1258
1259 /* Mod%c6 */
1260 if (DO_BIC(BIC_Mod_c6))
1261 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc);
1262
1263 if (DO_BIC(BIC_CoreTmp))
1264 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c);
1265
1266 /* Core throttle count */
1267 if (DO_BIC(BIC_CORE_THROT_CNT))
1268 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->core_throt_cnt);
1269
1270 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1271 if (mp->format == FORMAT_RAW) {
1272 if (mp->width == 32)
1273 outp +=
1274 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]);
1275 else
1276 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]);
1277 } else if (mp->format == FORMAT_DELTA) {
1278 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1279 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]);
1280 else
1281 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]);
1282 } else if (mp->format == FORMAT_PERCENT) {
1283 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i] / tsc);
1284 }
1285 }
1286
1287 fmt8 = "%s%.2f";
1288
1289 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
1290 outp +=
1291 sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float);
1292 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
1293 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units);
1294
1295 /* print per-package data only for 1st core in package */
1296 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1297 goto done;
1298
1299 /* PkgTmp */
1300 if (DO_BIC(BIC_PkgTmp))
1301 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c);
1302
1303 /* GFXrc6 */
1304 if (DO_BIC(BIC_GFX_rc6)) {
1305 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
1306 outp += sprintf(outp, "%s**.**", (printed++ ? delim : ""));
1307 } else {
1308 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1309 p->gfx_rc6_ms / 10.0 / interval_float);
1310 }
1311 }
1312
1313 /* GFXMHz */
1314 if (DO_BIC(BIC_GFXMHz))
1315 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz);
1316
1317 /* GFXACTMHz */
1318 if (DO_BIC(BIC_GFXACTMHz))
1319 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz);
1320
1321 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
1322 if (DO_BIC(BIC_Totl_c0))
1323 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0 / tsc);
1324 if (DO_BIC(BIC_Any_c0))
1325 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0 / tsc);
1326 if (DO_BIC(BIC_GFX_c0))
1327 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0 / tsc);
1328 if (DO_BIC(BIC_CPUGFX))
1329 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0 / tsc);
1330
1331 if (DO_BIC(BIC_Pkgpc2))
1332 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2 / tsc);
1333 if (DO_BIC(BIC_Pkgpc3))
1334 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3 / tsc);
1335 if (DO_BIC(BIC_Pkgpc6))
1336 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6 / tsc);
1337 if (DO_BIC(BIC_Pkgpc7))
1338 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7 / tsc);
1339 if (DO_BIC(BIC_Pkgpc8))
1340 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8 / tsc);
1341 if (DO_BIC(BIC_Pkgpc9))
1342 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9 / tsc);
1343 if (DO_BIC(BIC_Pkgpc10))
1344 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10 / tsc);
1345
1346 if (DO_BIC(BIC_CPU_LPI))
1347 outp +=
1348 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float);
1349 if (DO_BIC(BIC_SYS_LPI))
1350 outp +=
1351 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float);
1352
1353 if (DO_BIC(BIC_PkgWatt))
1354 outp +=
1355 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float);
1356
1357 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
1358 outp +=
1359 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float);
1360 if (DO_BIC(BIC_GFXWatt))
1361 outp +=
1362 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float);
1363 if (DO_BIC(BIC_RAMWatt))
1364 outp +=
1365 sprintf(outp, fmt8, (printed++ ? delim : ""),
1366 p->energy_dram * rapl_dram_energy_units / interval_float);
1367 if (DO_BIC(BIC_Pkg_J))
1368 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units);
1369 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
1370 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units);
1371 if (DO_BIC(BIC_GFX_J))
1372 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units);
1373 if (DO_BIC(BIC_RAM_J))
1374 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units);
1375 if (DO_BIC(BIC_PKG__))
1376 outp +=
1377 sprintf(outp, fmt8, (printed++ ? delim : ""),
1378 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
1379 if (DO_BIC(BIC_RAM__))
1380 outp +=
1381 sprintf(outp, fmt8, (printed++ ? delim : ""),
1382 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
1383 /* UncMHz */
1384 if (DO_BIC(BIC_UNCORE_MHZ))
1385 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->uncore_mhz);
1386
1387 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1388 if (mp->format == FORMAT_RAW) {
1389 if (mp->width == 32)
1390 outp +=
1391 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]);
1392 else
1393 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]);
1394 } else if (mp->format == FORMAT_DELTA) {
1395 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1396 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]);
1397 else
1398 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]);
1399 } else if (mp->format == FORMAT_PERCENT) {
1400 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i] / tsc);
1401 }
1402 }
1403
1404 done:
1405 if (*(outp - 1) != '\n')
1406 outp += sprintf(outp, "\n");
1407
1408 return 0;
1409 }
1410
flush_output_stdout(void)1411 void flush_output_stdout(void)
1412 {
1413 FILE *filep;
1414
1415 if (outf == stderr)
1416 filep = stdout;
1417 else
1418 filep = outf;
1419
1420 fputs(output_buffer, filep);
1421 fflush(filep);
1422
1423 outp = output_buffer;
1424 }
1425
flush_output_stderr(void)1426 void flush_output_stderr(void)
1427 {
1428 fputs(output_buffer, outf);
1429 fflush(outf);
1430 outp = output_buffer;
1431 }
1432
format_all_counters(struct thread_data * t,struct core_data * c,struct pkg_data * p)1433 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1434 {
1435 static int count;
1436
1437 if ((!count || (header_iterations && !(count % header_iterations))) || !summary_only)
1438 print_header("\t");
1439
1440 format_counters(&average.threads, &average.cores, &average.packages);
1441
1442 count++;
1443
1444 if (summary_only)
1445 return;
1446
1447 for_all_cpus(format_counters, t, c, p);
1448 }
1449
1450 #define DELTA_WRAP32(new, old) \
1451 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32);
1452
delta_package(struct pkg_data * new,struct pkg_data * old)1453 int delta_package(struct pkg_data *new, struct pkg_data *old)
1454 {
1455 int i;
1456 struct msr_counter *mp;
1457
1458 if (DO_BIC(BIC_Totl_c0))
1459 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
1460 if (DO_BIC(BIC_Any_c0))
1461 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
1462 if (DO_BIC(BIC_GFX_c0))
1463 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
1464 if (DO_BIC(BIC_CPUGFX))
1465 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
1466
1467 old->pc2 = new->pc2 - old->pc2;
1468 if (DO_BIC(BIC_Pkgpc3))
1469 old->pc3 = new->pc3 - old->pc3;
1470 if (DO_BIC(BIC_Pkgpc6))
1471 old->pc6 = new->pc6 - old->pc6;
1472 if (DO_BIC(BIC_Pkgpc7))
1473 old->pc7 = new->pc7 - old->pc7;
1474 old->pc8 = new->pc8 - old->pc8;
1475 old->pc9 = new->pc9 - old->pc9;
1476 old->pc10 = new->pc10 - old->pc10;
1477 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi;
1478 old->sys_lpi = new->sys_lpi - old->sys_lpi;
1479 old->pkg_temp_c = new->pkg_temp_c;
1480
1481 /* flag an error when rc6 counter resets/wraps */
1482 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
1483 old->gfx_rc6_ms = -1;
1484 else
1485 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
1486
1487 old->uncore_mhz = new->uncore_mhz;
1488 old->gfx_mhz = new->gfx_mhz;
1489 old->gfx_act_mhz = new->gfx_act_mhz;
1490
1491 old->energy_pkg = new->energy_pkg - old->energy_pkg;
1492 old->energy_cores = new->energy_cores - old->energy_cores;
1493 old->energy_gfx = new->energy_gfx - old->energy_gfx;
1494 old->energy_dram = new->energy_dram - old->energy_dram;
1495 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status;
1496 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status;
1497
1498 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1499 if (mp->format == FORMAT_RAW)
1500 old->counter[i] = new->counter[i];
1501 else
1502 old->counter[i] = new->counter[i] - old->counter[i];
1503 }
1504
1505 return 0;
1506 }
1507
delta_core(struct core_data * new,struct core_data * old)1508 void delta_core(struct core_data *new, struct core_data *old)
1509 {
1510 int i;
1511 struct msr_counter *mp;
1512
1513 old->c3 = new->c3 - old->c3;
1514 old->c6 = new->c6 - old->c6;
1515 old->c7 = new->c7 - old->c7;
1516 old->core_temp_c = new->core_temp_c;
1517 old->core_throt_cnt = new->core_throt_cnt;
1518 old->mc6_us = new->mc6_us - old->mc6_us;
1519
1520 DELTA_WRAP32(new->core_energy, old->core_energy);
1521
1522 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1523 if (mp->format == FORMAT_RAW)
1524 old->counter[i] = new->counter[i];
1525 else
1526 old->counter[i] = new->counter[i] - old->counter[i];
1527 }
1528 }
1529
soft_c1_residency_display(int bic)1530 int soft_c1_residency_display(int bic)
1531 {
1532 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr)
1533 return 0;
1534
1535 return DO_BIC_READ(bic);
1536 }
1537
1538 /*
1539 * old = new - old
1540 */
delta_thread(struct thread_data * new,struct thread_data * old,struct core_data * core_delta)1541 int delta_thread(struct thread_data *new, struct thread_data *old, struct core_data *core_delta)
1542 {
1543 int i;
1544 struct msr_counter *mp;
1545
1546 /* we run cpuid just the 1st time, copy the results */
1547 if (DO_BIC(BIC_APIC))
1548 new->apic_id = old->apic_id;
1549 if (DO_BIC(BIC_X2APIC))
1550 new->x2apic_id = old->x2apic_id;
1551
1552 /*
1553 * the timestamps from start of measurement interval are in "old"
1554 * the timestamp from end of measurement interval are in "new"
1555 * over-write old w/ new so we can print end of interval values
1556 */
1557
1558 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta);
1559 old->tv_begin = new->tv_begin;
1560 old->tv_end = new->tv_end;
1561
1562 old->tsc = new->tsc - old->tsc;
1563
1564 /* check for TSC < 1 Mcycles over interval */
1565 if (old->tsc < (1000 * 1000))
1566 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1567 "You can disable all c-states by booting with \"idle=poll\"\n"
1568 "or just the deep ones with \"processor.max_cstate=1\"");
1569
1570 old->c1 = new->c1 - old->c1;
1571
1572 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) {
1573 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
1574 old->aperf = new->aperf - old->aperf;
1575 old->mperf = new->mperf - old->mperf;
1576 } else {
1577 return -1;
1578 }
1579 }
1580
1581 if (use_c1_residency_msr) {
1582 /*
1583 * Some models have a dedicated C1 residency MSR,
1584 * which should be more accurate than the derivation below.
1585 */
1586 } else {
1587 /*
1588 * As counter collection is not atomic,
1589 * it is possible for mperf's non-halted cycles + idle states
1590 * to exceed TSC's all cycles: show c1 = 0% in that case.
1591 */
1592 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak))
1593 old->c1 = 0;
1594 else {
1595 /* normal case, derive c1 */
1596 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3
1597 - core_delta->c6 - core_delta->c7;
1598 }
1599 }
1600
1601 if (old->mperf == 0) {
1602 if (debug > 1)
1603 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
1604 old->mperf = 1; /* divide by 0 protection */
1605 }
1606
1607 if (DO_BIC(BIC_IPC))
1608 old->instr_count = new->instr_count - old->instr_count;
1609
1610 if (DO_BIC(BIC_IRQ))
1611 old->irq_count = new->irq_count - old->irq_count;
1612
1613 if (DO_BIC(BIC_SMI))
1614 old->smi_count = new->smi_count - old->smi_count;
1615
1616 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1617 if (mp->format == FORMAT_RAW)
1618 old->counter[i] = new->counter[i];
1619 else
1620 old->counter[i] = new->counter[i] - old->counter[i];
1621 }
1622 return 0;
1623 }
1624
delta_cpu(struct thread_data * t,struct core_data * c,struct pkg_data * p,struct thread_data * t2,struct core_data * c2,struct pkg_data * p2)1625 int delta_cpu(struct thread_data *t, struct core_data *c,
1626 struct pkg_data *p, struct thread_data *t2, struct core_data *c2, struct pkg_data *p2)
1627 {
1628 int retval = 0;
1629
1630 /* calculate core delta only for 1st thread in core */
1631 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
1632 delta_core(c, c2);
1633
1634 /* always calculate thread delta */
1635 retval = delta_thread(t, t2, c2); /* c2 is core delta */
1636 if (retval)
1637 return retval;
1638
1639 /* calculate package delta only for 1st core in package */
1640 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
1641 retval = delta_package(p, p2);
1642
1643 return retval;
1644 }
1645
clear_counters(struct thread_data * t,struct core_data * c,struct pkg_data * p)1646 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1647 {
1648 int i;
1649 struct msr_counter *mp;
1650
1651 t->tv_begin.tv_sec = 0;
1652 t->tv_begin.tv_usec = 0;
1653 t->tv_end.tv_sec = 0;
1654 t->tv_end.tv_usec = 0;
1655 t->tv_delta.tv_sec = 0;
1656 t->tv_delta.tv_usec = 0;
1657
1658 t->tsc = 0;
1659 t->aperf = 0;
1660 t->mperf = 0;
1661 t->c1 = 0;
1662
1663 t->instr_count = 0;
1664
1665 t->irq_count = 0;
1666 t->smi_count = 0;
1667
1668 /* tells format_counters to dump all fields from this set */
1669 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
1670
1671 c->c3 = 0;
1672 c->c6 = 0;
1673 c->c7 = 0;
1674 c->mc6_us = 0;
1675 c->core_temp_c = 0;
1676 c->core_energy = 0;
1677 c->core_throt_cnt = 0;
1678
1679 p->pkg_wtd_core_c0 = 0;
1680 p->pkg_any_core_c0 = 0;
1681 p->pkg_any_gfxe_c0 = 0;
1682 p->pkg_both_core_gfxe_c0 = 0;
1683
1684 p->pc2 = 0;
1685 if (DO_BIC(BIC_Pkgpc3))
1686 p->pc3 = 0;
1687 if (DO_BIC(BIC_Pkgpc6))
1688 p->pc6 = 0;
1689 if (DO_BIC(BIC_Pkgpc7))
1690 p->pc7 = 0;
1691 p->pc8 = 0;
1692 p->pc9 = 0;
1693 p->pc10 = 0;
1694 p->cpu_lpi = 0;
1695 p->sys_lpi = 0;
1696
1697 p->energy_pkg = 0;
1698 p->energy_dram = 0;
1699 p->energy_cores = 0;
1700 p->energy_gfx = 0;
1701 p->rapl_pkg_perf_status = 0;
1702 p->rapl_dram_perf_status = 0;
1703 p->pkg_temp_c = 0;
1704
1705 p->gfx_rc6_ms = 0;
1706 p->uncore_mhz = 0;
1707 p->gfx_mhz = 0;
1708 p->gfx_act_mhz = 0;
1709 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
1710 t->counter[i] = 0;
1711
1712 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
1713 c->counter[i] = 0;
1714
1715 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
1716 p->counter[i] = 0;
1717 }
1718
sum_counters(struct thread_data * t,struct core_data * c,struct pkg_data * p)1719 int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1720 {
1721 int i;
1722 struct msr_counter *mp;
1723
1724 /* copy un-changing apic_id's */
1725 if (DO_BIC(BIC_APIC))
1726 average.threads.apic_id = t->apic_id;
1727 if (DO_BIC(BIC_X2APIC))
1728 average.threads.x2apic_id = t->x2apic_id;
1729
1730 /* remember first tv_begin */
1731 if (average.threads.tv_begin.tv_sec == 0)
1732 average.threads.tv_begin = t->tv_begin;
1733
1734 /* remember last tv_end */
1735 average.threads.tv_end = t->tv_end;
1736
1737 average.threads.tsc += t->tsc;
1738 average.threads.aperf += t->aperf;
1739 average.threads.mperf += t->mperf;
1740 average.threads.c1 += t->c1;
1741
1742 average.threads.instr_count += t->instr_count;
1743
1744 average.threads.irq_count += t->irq_count;
1745 average.threads.smi_count += t->smi_count;
1746
1747 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1748 if (mp->format == FORMAT_RAW)
1749 continue;
1750 average.threads.counter[i] += t->counter[i];
1751 }
1752
1753 /* sum per-core values only for 1st thread in core */
1754 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1755 return 0;
1756
1757 average.cores.c3 += c->c3;
1758 average.cores.c6 += c->c6;
1759 average.cores.c7 += c->c7;
1760 average.cores.mc6_us += c->mc6_us;
1761
1762 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
1763 average.cores.core_throt_cnt = MAX(average.cores.core_throt_cnt, c->core_throt_cnt);
1764
1765 average.cores.core_energy += c->core_energy;
1766
1767 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1768 if (mp->format == FORMAT_RAW)
1769 continue;
1770 average.cores.counter[i] += c->counter[i];
1771 }
1772
1773 /* sum per-pkg values only for 1st core in pkg */
1774 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1775 return 0;
1776
1777 if (DO_BIC(BIC_Totl_c0))
1778 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
1779 if (DO_BIC(BIC_Any_c0))
1780 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
1781 if (DO_BIC(BIC_GFX_c0))
1782 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
1783 if (DO_BIC(BIC_CPUGFX))
1784 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
1785
1786 average.packages.pc2 += p->pc2;
1787 if (DO_BIC(BIC_Pkgpc3))
1788 average.packages.pc3 += p->pc3;
1789 if (DO_BIC(BIC_Pkgpc6))
1790 average.packages.pc6 += p->pc6;
1791 if (DO_BIC(BIC_Pkgpc7))
1792 average.packages.pc7 += p->pc7;
1793 average.packages.pc8 += p->pc8;
1794 average.packages.pc9 += p->pc9;
1795 average.packages.pc10 += p->pc10;
1796
1797 average.packages.cpu_lpi = p->cpu_lpi;
1798 average.packages.sys_lpi = p->sys_lpi;
1799
1800 average.packages.energy_pkg += p->energy_pkg;
1801 average.packages.energy_dram += p->energy_dram;
1802 average.packages.energy_cores += p->energy_cores;
1803 average.packages.energy_gfx += p->energy_gfx;
1804
1805 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
1806 average.packages.uncore_mhz = p->uncore_mhz;
1807 average.packages.gfx_mhz = p->gfx_mhz;
1808 average.packages.gfx_act_mhz = p->gfx_act_mhz;
1809
1810 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
1811
1812 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
1813 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
1814
1815 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1816 if ((mp->format == FORMAT_RAW) && (topo.num_packages == 0))
1817 average.packages.counter[i] = p->counter[i];
1818 else
1819 average.packages.counter[i] += p->counter[i];
1820 }
1821 return 0;
1822 }
1823
1824 /*
1825 * sum the counters for all cpus in the system
1826 * compute the weighted average
1827 */
compute_average(struct thread_data * t,struct core_data * c,struct pkg_data * p)1828 void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1829 {
1830 int i;
1831 struct msr_counter *mp;
1832
1833 clear_counters(&average.threads, &average.cores, &average.packages);
1834
1835 for_all_cpus(sum_counters, t, c, p);
1836
1837 /* Use the global time delta for the average. */
1838 average.threads.tv_delta = tv_delta;
1839
1840 average.threads.tsc /= topo.num_cpus;
1841 average.threads.aperf /= topo.num_cpus;
1842 average.threads.mperf /= topo.num_cpus;
1843 average.threads.instr_count /= topo.num_cpus;
1844 average.threads.c1 /= topo.num_cpus;
1845
1846 if (average.threads.irq_count > 9999999)
1847 sums_need_wide_columns = 1;
1848
1849 average.cores.c3 /= topo.num_cores;
1850 average.cores.c6 /= topo.num_cores;
1851 average.cores.c7 /= topo.num_cores;
1852 average.cores.mc6_us /= topo.num_cores;
1853
1854 if (DO_BIC(BIC_Totl_c0))
1855 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
1856 if (DO_BIC(BIC_Any_c0))
1857 average.packages.pkg_any_core_c0 /= topo.num_packages;
1858 if (DO_BIC(BIC_GFX_c0))
1859 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
1860 if (DO_BIC(BIC_CPUGFX))
1861 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
1862
1863 average.packages.pc2 /= topo.num_packages;
1864 if (DO_BIC(BIC_Pkgpc3))
1865 average.packages.pc3 /= topo.num_packages;
1866 if (DO_BIC(BIC_Pkgpc6))
1867 average.packages.pc6 /= topo.num_packages;
1868 if (DO_BIC(BIC_Pkgpc7))
1869 average.packages.pc7 /= topo.num_packages;
1870
1871 average.packages.pc8 /= topo.num_packages;
1872 average.packages.pc9 /= topo.num_packages;
1873 average.packages.pc10 /= topo.num_packages;
1874
1875 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1876 if (mp->format == FORMAT_RAW)
1877 continue;
1878 if (mp->type == COUNTER_ITEMS) {
1879 if (average.threads.counter[i] > 9999999)
1880 sums_need_wide_columns = 1;
1881 continue;
1882 }
1883 average.threads.counter[i] /= topo.num_cpus;
1884 }
1885 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1886 if (mp->format == FORMAT_RAW)
1887 continue;
1888 if (mp->type == COUNTER_ITEMS) {
1889 if (average.cores.counter[i] > 9999999)
1890 sums_need_wide_columns = 1;
1891 }
1892 average.cores.counter[i] /= topo.num_cores;
1893 }
1894 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1895 if (mp->format == FORMAT_RAW)
1896 continue;
1897 if (mp->type == COUNTER_ITEMS) {
1898 if (average.packages.counter[i] > 9999999)
1899 sums_need_wide_columns = 1;
1900 }
1901 average.packages.counter[i] /= topo.num_packages;
1902 }
1903 }
1904
rdtsc(void)1905 static unsigned long long rdtsc(void)
1906 {
1907 unsigned int low, high;
1908
1909 asm volatile ("rdtsc":"=a" (low), "=d"(high));
1910
1911 return low | ((unsigned long long)high) << 32;
1912 }
1913
1914 /*
1915 * Open a file, and exit on failure
1916 */
fopen_or_die(const char * path,const char * mode)1917 FILE *fopen_or_die(const char *path, const char *mode)
1918 {
1919 FILE *filep = fopen(path, mode);
1920
1921 if (!filep)
1922 err(1, "%s: open failed", path);
1923 return filep;
1924 }
1925
1926 /*
1927 * snapshot_sysfs_counter()
1928 *
1929 * return snapshot of given counter
1930 */
snapshot_sysfs_counter(char * path)1931 unsigned long long snapshot_sysfs_counter(char *path)
1932 {
1933 FILE *fp;
1934 int retval;
1935 unsigned long long counter;
1936
1937 fp = fopen_or_die(path, "r");
1938
1939 retval = fscanf(fp, "%lld", &counter);
1940 if (retval != 1)
1941 err(1, "snapshot_sysfs_counter(%s)", path);
1942
1943 fclose(fp);
1944
1945 return counter;
1946 }
1947
get_mp(int cpu,struct msr_counter * mp,unsigned long long * counterp)1948 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp)
1949 {
1950 if (mp->msr_num != 0) {
1951 if (get_msr(cpu, mp->msr_num, counterp))
1952 return -1;
1953 } else {
1954 char path[128 + PATH_BYTES];
1955
1956 if (mp->flags & SYSFS_PERCPU) {
1957 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", cpu, mp->path);
1958
1959 *counterp = snapshot_sysfs_counter(path);
1960 } else {
1961 *counterp = snapshot_sysfs_counter(mp->path);
1962 }
1963 }
1964
1965 return 0;
1966 }
1967
get_uncore_mhz(int package,int die)1968 unsigned long long get_uncore_mhz(int package, int die)
1969 {
1970 char path[128];
1971
1972 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_%02d_die_%02d/current_freq_khz", package,
1973 die);
1974
1975 return (snapshot_sysfs_counter(path) / 1000);
1976 }
1977
get_epb(int cpu)1978 int get_epb(int cpu)
1979 {
1980 char path[128 + PATH_BYTES];
1981 unsigned long long msr;
1982 int ret, epb = -1;
1983 FILE *fp;
1984
1985 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu);
1986
1987 fp = fopen(path, "r");
1988 if (!fp)
1989 goto msr_fallback;
1990
1991 ret = fscanf(fp, "%d", &epb);
1992 if (ret != 1)
1993 err(1, "%s(%s)", __func__, path);
1994
1995 fclose(fp);
1996
1997 return epb;
1998
1999 msr_fallback:
2000 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr);
2001
2002 return msr & 0xf;
2003 }
2004
get_apic_id(struct thread_data * t)2005 void get_apic_id(struct thread_data *t)
2006 {
2007 unsigned int eax, ebx, ecx, edx;
2008
2009 if (DO_BIC(BIC_APIC)) {
2010 eax = ebx = ecx = edx = 0;
2011 __cpuid(1, eax, ebx, ecx, edx);
2012
2013 t->apic_id = (ebx >> 24) & 0xff;
2014 }
2015
2016 if (!DO_BIC(BIC_X2APIC))
2017 return;
2018
2019 if (authentic_amd || hygon_genuine) {
2020 unsigned int topology_extensions;
2021
2022 if (max_extended_level < 0x8000001e)
2023 return;
2024
2025 eax = ebx = ecx = edx = 0;
2026 __cpuid(0x80000001, eax, ebx, ecx, edx);
2027 topology_extensions = ecx & (1 << 22);
2028
2029 if (topology_extensions == 0)
2030 return;
2031
2032 eax = ebx = ecx = edx = 0;
2033 __cpuid(0x8000001e, eax, ebx, ecx, edx);
2034
2035 t->x2apic_id = eax;
2036 return;
2037 }
2038
2039 if (!genuine_intel)
2040 return;
2041
2042 if (max_level < 0xb)
2043 return;
2044
2045 ecx = 0;
2046 __cpuid(0xb, eax, ebx, ecx, edx);
2047 t->x2apic_id = edx;
2048
2049 if (debug && (t->apic_id != (t->x2apic_id & 0xff)))
2050 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id);
2051 }
2052
get_core_throt_cnt(int cpu,unsigned long long * cnt)2053 int get_core_throt_cnt(int cpu, unsigned long long *cnt)
2054 {
2055 char path[128 + PATH_BYTES];
2056 unsigned long long tmp;
2057 FILE *fp;
2058 int ret;
2059
2060 sprintf(path, "/sys/devices/system/cpu/cpu%d/thermal_throttle/core_throttle_count", cpu);
2061 fp = fopen(path, "r");
2062 if (!fp)
2063 return -1;
2064 ret = fscanf(fp, "%lld", &tmp);
2065 fclose(fp);
2066 if (ret != 1)
2067 return -1;
2068 *cnt = tmp;
2069
2070 return 0;
2071 }
2072
2073 /*
2074 * get_counters(...)
2075 * migrate to cpu
2076 * acquire and record local counters for that cpu
2077 */
get_counters(struct thread_data * t,struct core_data * c,struct pkg_data * p)2078 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2079 {
2080 int cpu = t->cpu_id;
2081 unsigned long long msr;
2082 int aperf_mperf_retry_count = 0;
2083 struct msr_counter *mp;
2084 int i;
2085
2086 if (cpu_migrate(cpu)) {
2087 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu);
2088 return -1;
2089 }
2090
2091 gettimeofday(&t->tv_begin, (struct timezone *)NULL);
2092
2093 if (first_counter_read)
2094 get_apic_id(t);
2095 retry:
2096 t->tsc = rdtsc(); /* we are running on local CPU of interest */
2097
2098 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) {
2099 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
2100
2101 /*
2102 * The TSC, APERF and MPERF must be read together for
2103 * APERF/MPERF and MPERF/TSC to give accurate results.
2104 *
2105 * Unfortunately, APERF and MPERF are read by
2106 * individual system call, so delays may occur
2107 * between them. If the time to read them
2108 * varies by a large amount, we re-read them.
2109 */
2110
2111 /*
2112 * This initial dummy APERF read has been seen to
2113 * reduce jitter in the subsequent reads.
2114 */
2115
2116 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
2117 return -3;
2118
2119 t->tsc = rdtsc(); /* re-read close to APERF */
2120
2121 tsc_before = t->tsc;
2122
2123 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
2124 return -3;
2125
2126 tsc_between = rdtsc();
2127
2128 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
2129 return -4;
2130
2131 tsc_after = rdtsc();
2132
2133 aperf_time = tsc_between - tsc_before;
2134 mperf_time = tsc_after - tsc_between;
2135
2136 /*
2137 * If the system call latency to read APERF and MPERF
2138 * differ by more than 2x, then try again.
2139 */
2140 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
2141 aperf_mperf_retry_count++;
2142 if (aperf_mperf_retry_count < 5)
2143 goto retry;
2144 else
2145 warnx("cpu%d jitter %lld %lld", cpu, aperf_time, mperf_time);
2146 }
2147 aperf_mperf_retry_count = 0;
2148
2149 t->aperf = t->aperf * aperf_mperf_multiplier;
2150 t->mperf = t->mperf * aperf_mperf_multiplier;
2151 }
2152
2153 if (DO_BIC(BIC_IPC))
2154 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long))
2155 return -4;
2156
2157 if (DO_BIC(BIC_IRQ))
2158 t->irq_count = irqs_per_cpu[cpu];
2159 if (DO_BIC(BIC_SMI)) {
2160 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
2161 return -5;
2162 t->smi_count = msr & 0xFFFFFFFF;
2163 }
2164 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
2165 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
2166 return -6;
2167 }
2168
2169 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
2170 if (get_mp(cpu, mp, &t->counter[i]))
2171 return -10;
2172 }
2173
2174 /* collect core counters only for 1st thread in core */
2175 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
2176 goto done;
2177
2178 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) {
2179 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
2180 return -6;
2181 }
2182
2183 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) {
2184 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
2185 return -7;
2186 } else if (do_knl_cstates && soft_c1_residency_display(BIC_CPU_c6)) {
2187 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
2188 return -7;
2189 }
2190
2191 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) {
2192 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
2193 return -8;
2194 else if (t->is_atom) {
2195 /*
2196 * For Atom CPUs that has core cstate deeper than c6,
2197 * MSR_CORE_C6_RESIDENCY returns residency of cc6 and deeper.
2198 * Minus CC7 (and deeper cstates) residency to get
2199 * accturate cc6 residency.
2200 */
2201 c->c6 -= c->c7;
2202 }
2203 }
2204
2205 if (DO_BIC(BIC_Mod_c6))
2206 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
2207 return -8;
2208
2209 if (DO_BIC(BIC_CoreTmp)) {
2210 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
2211 return -9;
2212 c->core_temp_c = tj_max - ((msr >> 16) & 0x7F);
2213 }
2214
2215 if (DO_BIC(BIC_CORE_THROT_CNT))
2216 get_core_throt_cnt(cpu, &c->core_throt_cnt);
2217
2218 if (do_rapl & RAPL_AMD_F17H) {
2219 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr))
2220 return -14;
2221 c->core_energy = msr & 0xFFFFFFFF;
2222 }
2223
2224 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
2225 if (get_mp(cpu, mp, &c->counter[i]))
2226 return -10;
2227 }
2228
2229 /* collect package counters only for 1st core in package */
2230 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2231 goto done;
2232
2233 if (DO_BIC(BIC_Totl_c0)) {
2234 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
2235 return -10;
2236 }
2237 if (DO_BIC(BIC_Any_c0)) {
2238 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
2239 return -11;
2240 }
2241 if (DO_BIC(BIC_GFX_c0)) {
2242 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
2243 return -12;
2244 }
2245 if (DO_BIC(BIC_CPUGFX)) {
2246 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
2247 return -13;
2248 }
2249 if (DO_BIC(BIC_Pkgpc3))
2250 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
2251 return -9;
2252 if (DO_BIC(BIC_Pkgpc6)) {
2253 if (do_slm_cstates) {
2254 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
2255 return -10;
2256 } else {
2257 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
2258 return -10;
2259 }
2260 }
2261
2262 if (DO_BIC(BIC_Pkgpc2))
2263 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
2264 return -11;
2265 if (DO_BIC(BIC_Pkgpc7))
2266 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
2267 return -12;
2268 if (DO_BIC(BIC_Pkgpc8))
2269 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
2270 return -13;
2271 if (DO_BIC(BIC_Pkgpc9))
2272 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
2273 return -13;
2274 if (DO_BIC(BIC_Pkgpc10))
2275 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
2276 return -13;
2277
2278 if (DO_BIC(BIC_CPU_LPI))
2279 p->cpu_lpi = cpuidle_cur_cpu_lpi_us;
2280 if (DO_BIC(BIC_SYS_LPI))
2281 p->sys_lpi = cpuidle_cur_sys_lpi_us;
2282
2283 if (do_rapl & RAPL_PKG) {
2284 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr))
2285 return -13;
2286 p->energy_pkg = msr;
2287 }
2288 if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
2289 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr))
2290 return -14;
2291 p->energy_cores = msr;
2292 }
2293 if (do_rapl & RAPL_DRAM) {
2294 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
2295 return -15;
2296 p->energy_dram = msr;
2297 }
2298 if (do_rapl & RAPL_GFX) {
2299 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr))
2300 return -16;
2301 p->energy_gfx = msr;
2302 }
2303 if (do_rapl & RAPL_PKG_PERF_STATUS) {
2304 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr))
2305 return -16;
2306 p->rapl_pkg_perf_status = msr;
2307 }
2308 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
2309 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr))
2310 return -16;
2311 p->rapl_dram_perf_status = msr;
2312 }
2313 if (do_rapl & RAPL_AMD_F17H) {
2314 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr))
2315 return -13;
2316 p->energy_pkg = msr;
2317 }
2318 if (DO_BIC(BIC_PkgTmp)) {
2319 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
2320 return -17;
2321 p->pkg_temp_c = tj_max - ((msr >> 16) & 0x7F);
2322 }
2323
2324 if (DO_BIC(BIC_GFX_rc6))
2325 p->gfx_rc6_ms = gfx_cur_rc6_ms;
2326
2327 /* n.b. assume die0 uncore frequency applies to whole package */
2328 if (DO_BIC(BIC_UNCORE_MHZ))
2329 p->uncore_mhz = get_uncore_mhz(p->package_id, 0);
2330
2331 if (DO_BIC(BIC_GFXMHz))
2332 p->gfx_mhz = gfx_cur_mhz;
2333
2334 if (DO_BIC(BIC_GFXACTMHz))
2335 p->gfx_act_mhz = gfx_act_mhz;
2336
2337 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2338 if (get_mp(cpu, mp, &p->counter[i]))
2339 return -10;
2340 }
2341 done:
2342 gettimeofday(&t->tv_end, (struct timezone *)NULL);
2343
2344 return 0;
2345 }
2346
2347 /*
2348 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
2349 * If you change the values, note they are used both in comparisons
2350 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
2351 */
2352
2353 #define PCLUKN 0 /* Unknown */
2354 #define PCLRSV 1 /* Reserved */
2355 #define PCL__0 2 /* PC0 */
2356 #define PCL__1 3 /* PC1 */
2357 #define PCL__2 4 /* PC2 */
2358 #define PCL__3 5 /* PC3 */
2359 #define PCL__4 6 /* PC4 */
2360 #define PCL__6 7 /* PC6 */
2361 #define PCL_6N 8 /* PC6 No Retention */
2362 #define PCL_6R 9 /* PC6 Retention */
2363 #define PCL__7 10 /* PC7 */
2364 #define PCL_7S 11 /* PC7 Shrink */
2365 #define PCL__8 12 /* PC8 */
2366 #define PCL__9 13 /* PC9 */
2367 #define PCL_10 14 /* PC10 */
2368 #define PCLUNL 15 /* Unlimited */
2369
2370 int pkg_cstate_limit = PCLUKN;
2371 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
2372 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"
2373 };
2374
2375 int nhm_pkg_cstate_limits[16] =
2376 { PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2377 PCLRSV, PCLRSV
2378 };
2379
2380 int snb_pkg_cstate_limits[16] =
2381 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2382 PCLRSV, PCLRSV
2383 };
2384
2385 int hsw_pkg_cstate_limits[16] =
2386 { PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2387 PCLRSV, PCLRSV
2388 };
2389
2390 int slv_pkg_cstate_limits[16] =
2391 { PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2392 PCL__6, PCL__7
2393 };
2394
2395 int amt_pkg_cstate_limits[16] =
2396 { PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2397 PCLRSV, PCLRSV
2398 };
2399
2400 int phi_pkg_cstate_limits[16] =
2401 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2402 PCLRSV, PCLRSV
2403 };
2404
2405 int glm_pkg_cstate_limits[16] =
2406 { PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2407 PCLRSV, PCLRSV
2408 };
2409
2410 int skx_pkg_cstate_limits[16] =
2411 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2412 PCLRSV, PCLRSV
2413 };
2414
2415 int icx_pkg_cstate_limits[16] =
2416 { PCL__0, PCL__2, PCL__6, PCL__6, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2417 PCLRSV, PCLRSV
2418 };
2419
calculate_tsc_tweak()2420 static void calculate_tsc_tweak()
2421 {
2422 tsc_tweak = base_hz / tsc_hz;
2423 }
2424
2425 void prewake_cstate_probe(unsigned int family, unsigned int model);
2426
dump_nhm_platform_info(void)2427 static void dump_nhm_platform_info(void)
2428 {
2429 unsigned long long msr;
2430 unsigned int ratio;
2431
2432 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
2433
2434 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
2435
2436 ratio = (msr >> 40) & 0xFF;
2437 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk);
2438
2439 ratio = (msr >> 8) & 0xFF;
2440 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
2441
2442 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
2443 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
2444 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
2445
2446 /* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */
2447 if (dis_cstate_prewake)
2448 fprintf(outf, "C-state Pre-wake: %sabled\n", msr & 0x40000000 ? "DIS" : "EN");
2449
2450 return;
2451 }
2452
dump_hsw_turbo_ratio_limits(void)2453 static void dump_hsw_turbo_ratio_limits(void)
2454 {
2455 unsigned long long msr;
2456 unsigned int ratio;
2457
2458 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
2459
2460 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
2461
2462 ratio = (msr >> 8) & 0xFF;
2463 if (ratio)
2464 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk);
2465
2466 ratio = (msr >> 0) & 0xFF;
2467 if (ratio)
2468 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk);
2469 return;
2470 }
2471
dump_ivt_turbo_ratio_limits(void)2472 static void dump_ivt_turbo_ratio_limits(void)
2473 {
2474 unsigned long long msr;
2475 unsigned int ratio;
2476
2477 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
2478
2479 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
2480
2481 ratio = (msr >> 56) & 0xFF;
2482 if (ratio)
2483 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk);
2484
2485 ratio = (msr >> 48) & 0xFF;
2486 if (ratio)
2487 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk);
2488
2489 ratio = (msr >> 40) & 0xFF;
2490 if (ratio)
2491 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk);
2492
2493 ratio = (msr >> 32) & 0xFF;
2494 if (ratio)
2495 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk);
2496
2497 ratio = (msr >> 24) & 0xFF;
2498 if (ratio)
2499 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk);
2500
2501 ratio = (msr >> 16) & 0xFF;
2502 if (ratio)
2503 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk);
2504
2505 ratio = (msr >> 8) & 0xFF;
2506 if (ratio)
2507 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk);
2508
2509 ratio = (msr >> 0) & 0xFF;
2510 if (ratio)
2511 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk);
2512 return;
2513 }
2514
has_turbo_ratio_group_limits(int family,int model)2515 int has_turbo_ratio_group_limits(int family, int model)
2516 {
2517
2518 if (!genuine_intel)
2519 return 0;
2520
2521 if (family != 6)
2522 return 0;
2523
2524 switch (model) {
2525 case INTEL_FAM6_ATOM_GOLDMONT:
2526 case INTEL_FAM6_SKYLAKE_X:
2527 case INTEL_FAM6_ICELAKE_X:
2528 case INTEL_FAM6_SAPPHIRERAPIDS_X:
2529 case INTEL_FAM6_ATOM_GOLDMONT_D:
2530 case INTEL_FAM6_ATOM_TREMONT_D:
2531 return 1;
2532 default:
2533 return 0;
2534 }
2535 }
2536
dump_turbo_ratio_limits(int trl_msr_offset,int family,int model)2537 static void dump_turbo_ratio_limits(int trl_msr_offset, int family, int model)
2538 {
2539 unsigned long long msr, core_counts;
2540 int shift;
2541
2542 get_msr(base_cpu, trl_msr_offset, &msr);
2543 fprintf(outf, "cpu%d: MSR_%sTURBO_RATIO_LIMIT: 0x%08llx\n",
2544 base_cpu, trl_msr_offset == MSR_SECONDARY_TURBO_RATIO_LIMIT ? "SECONDARY_" : "", msr);
2545
2546 if (has_turbo_ratio_group_limits(family, model)) {
2547 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
2548 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts);
2549 } else {
2550 core_counts = 0x0807060504030201;
2551 }
2552
2553 for (shift = 56; shift >= 0; shift -= 8) {
2554 unsigned int ratio, group_size;
2555
2556 ratio = (msr >> shift) & 0xFF;
2557 group_size = (core_counts >> shift) & 0xFF;
2558 if (ratio)
2559 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2560 ratio, bclk, ratio * bclk, group_size);
2561 }
2562
2563 return;
2564 }
2565
dump_atom_turbo_ratio_limits(void)2566 static void dump_atom_turbo_ratio_limits(void)
2567 {
2568 unsigned long long msr;
2569 unsigned int ratio;
2570
2571 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
2572 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2573
2574 ratio = (msr >> 0) & 0x3F;
2575 if (ratio)
2576 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", ratio, bclk, ratio * bclk);
2577
2578 ratio = (msr >> 8) & 0x3F;
2579 if (ratio)
2580 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", ratio, bclk, ratio * bclk);
2581
2582 ratio = (msr >> 16) & 0x3F;
2583 if (ratio)
2584 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
2585
2586 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
2587 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2588
2589 ratio = (msr >> 24) & 0x3F;
2590 if (ratio)
2591 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk);
2592
2593 ratio = (msr >> 16) & 0x3F;
2594 if (ratio)
2595 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk);
2596
2597 ratio = (msr >> 8) & 0x3F;
2598 if (ratio)
2599 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk);
2600
2601 ratio = (msr >> 0) & 0x3F;
2602 if (ratio)
2603 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", ratio, bclk, ratio * bclk);
2604 }
2605
dump_knl_turbo_ratio_limits(void)2606 static void dump_knl_turbo_ratio_limits(void)
2607 {
2608 const unsigned int buckets_no = 7;
2609
2610 unsigned long long msr;
2611 int delta_cores, delta_ratio;
2612 int i, b_nr;
2613 unsigned int cores[buckets_no];
2614 unsigned int ratio[buckets_no];
2615
2616 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
2617
2618 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
2619
2620 /*
2621 * Turbo encoding in KNL is as follows:
2622 * [0] -- Reserved
2623 * [7:1] -- Base value of number of active cores of bucket 1.
2624 * [15:8] -- Base value of freq ratio of bucket 1.
2625 * [20:16] -- +ve delta of number of active cores of bucket 2.
2626 * i.e. active cores of bucket 2 =
2627 * active cores of bucket 1 + delta
2628 * [23:21] -- Negative delta of freq ratio of bucket 2.
2629 * i.e. freq ratio of bucket 2 =
2630 * freq ratio of bucket 1 - delta
2631 * [28:24]-- +ve delta of number of active cores of bucket 3.
2632 * [31:29]-- -ve delta of freq ratio of bucket 3.
2633 * [36:32]-- +ve delta of number of active cores of bucket 4.
2634 * [39:37]-- -ve delta of freq ratio of bucket 4.
2635 * [44:40]-- +ve delta of number of active cores of bucket 5.
2636 * [47:45]-- -ve delta of freq ratio of bucket 5.
2637 * [52:48]-- +ve delta of number of active cores of bucket 6.
2638 * [55:53]-- -ve delta of freq ratio of bucket 6.
2639 * [60:56]-- +ve delta of number of active cores of bucket 7.
2640 * [63:61]-- -ve delta of freq ratio of bucket 7.
2641 */
2642
2643 b_nr = 0;
2644 cores[b_nr] = (msr & 0xFF) >> 1;
2645 ratio[b_nr] = (msr >> 8) & 0xFF;
2646
2647 for (i = 16; i < 64; i += 8) {
2648 delta_cores = (msr >> i) & 0x1F;
2649 delta_ratio = (msr >> (i + 5)) & 0x7;
2650
2651 cores[b_nr + 1] = cores[b_nr] + delta_cores;
2652 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
2653 b_nr++;
2654 }
2655
2656 for (i = buckets_no - 1; i >= 0; i--)
2657 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
2658 fprintf(outf,
2659 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2660 ratio[i], bclk, ratio[i] * bclk, cores[i]);
2661 }
2662
dump_nhm_cst_cfg(void)2663 static void dump_nhm_cst_cfg(void)
2664 {
2665 unsigned long long msr;
2666
2667 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
2668
2669 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr);
2670
2671 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)",
2672 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
2673 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
2674 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
2675 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
2676 (msr & (1 << 15)) ? "" : "UN", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]);
2677
2678 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16)
2679 if (has_automatic_cstate_conversion) {
2680 fprintf(outf, ", automatic c-state conversion=%s", (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off");
2681 }
2682
2683 fprintf(outf, ")\n");
2684
2685 return;
2686 }
2687
dump_config_tdp(void)2688 static void dump_config_tdp(void)
2689 {
2690 unsigned long long msr;
2691
2692 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
2693 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
2694 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
2695
2696 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
2697 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
2698 if (msr) {
2699 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
2700 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
2701 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
2702 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
2703 }
2704 fprintf(outf, ")\n");
2705
2706 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
2707 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
2708 if (msr) {
2709 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
2710 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
2711 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
2712 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
2713 }
2714 fprintf(outf, ")\n");
2715
2716 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
2717 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
2718 if ((msr) & 0x3)
2719 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
2720 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
2721 fprintf(outf, ")\n");
2722
2723 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
2724 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
2725 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
2726 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
2727 fprintf(outf, ")\n");
2728 }
2729
2730 unsigned int irtl_time_units[] = { 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
2731
print_irtl(void)2732 void print_irtl(void)
2733 {
2734 unsigned long long msr;
2735
2736 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
2737 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
2738 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2739 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2740
2741 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
2742 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
2743 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2744 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2745
2746 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
2747 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
2748 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2749 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2750
2751 if (!do_irtl_hsw)
2752 return;
2753
2754 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
2755 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
2756 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2757 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2758
2759 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
2760 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
2761 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2762 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2763
2764 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
2765 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
2766 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2767 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2768
2769 }
2770
free_fd_percpu(void)2771 void free_fd_percpu(void)
2772 {
2773 int i;
2774
2775 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
2776 if (fd_percpu[i] != 0)
2777 close(fd_percpu[i]);
2778 }
2779
2780 free(fd_percpu);
2781 }
2782
free_all_buffers(void)2783 void free_all_buffers(void)
2784 {
2785 int i;
2786
2787 CPU_FREE(cpu_present_set);
2788 cpu_present_set = NULL;
2789 cpu_present_setsize = 0;
2790
2791 CPU_FREE(cpu_affinity_set);
2792 cpu_affinity_set = NULL;
2793 cpu_affinity_setsize = 0;
2794
2795 free(thread_even);
2796 free(core_even);
2797 free(package_even);
2798
2799 thread_even = NULL;
2800 core_even = NULL;
2801 package_even = NULL;
2802
2803 free(thread_odd);
2804 free(core_odd);
2805 free(package_odd);
2806
2807 thread_odd = NULL;
2808 core_odd = NULL;
2809 package_odd = NULL;
2810
2811 free(output_buffer);
2812 output_buffer = NULL;
2813 outp = NULL;
2814
2815 free_fd_percpu();
2816
2817 free(irq_column_2_cpu);
2818 free(irqs_per_cpu);
2819
2820 for (i = 0; i <= topo.max_cpu_num; ++i) {
2821 if (cpus[i].put_ids)
2822 CPU_FREE(cpus[i].put_ids);
2823 }
2824 free(cpus);
2825 }
2826
2827 /*
2828 * Parse a file containing a single int.
2829 * Return 0 if file can not be opened
2830 * Exit if file can be opened, but can not be parsed
2831 */
parse_int_file(const char * fmt,...)2832 int parse_int_file(const char *fmt, ...)
2833 {
2834 va_list args;
2835 char path[PATH_MAX];
2836 FILE *filep;
2837 int value;
2838
2839 va_start(args, fmt);
2840 vsnprintf(path, sizeof(path), fmt, args);
2841 va_end(args);
2842 filep = fopen(path, "r");
2843 if (!filep)
2844 return 0;
2845 if (fscanf(filep, "%d", &value) != 1)
2846 err(1, "%s: failed to parse number from file", path);
2847 fclose(filep);
2848 return value;
2849 }
2850
2851 /*
2852 * cpu_is_first_core_in_package(cpu)
2853 * return 1 if given CPU is 1st core in package
2854 */
cpu_is_first_core_in_package(int cpu)2855 int cpu_is_first_core_in_package(int cpu)
2856 {
2857 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
2858 }
2859
get_physical_package_id(int cpu)2860 int get_physical_package_id(int cpu)
2861 {
2862 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
2863 }
2864
get_die_id(int cpu)2865 int get_die_id(int cpu)
2866 {
2867 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu);
2868 }
2869
get_core_id(int cpu)2870 int get_core_id(int cpu)
2871 {
2872 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
2873 }
2874
set_node_data(void)2875 void set_node_data(void)
2876 {
2877 int pkg, node, lnode, cpu, cpux;
2878 int cpu_count;
2879
2880 /* initialize logical_node_id */
2881 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu)
2882 cpus[cpu].logical_node_id = -1;
2883
2884 cpu_count = 0;
2885 for (pkg = 0; pkg < topo.num_packages; pkg++) {
2886 lnode = 0;
2887 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) {
2888 if (cpus[cpu].physical_package_id != pkg)
2889 continue;
2890 /* find a cpu with an unset logical_node_id */
2891 if (cpus[cpu].logical_node_id != -1)
2892 continue;
2893 cpus[cpu].logical_node_id = lnode;
2894 node = cpus[cpu].physical_node_id;
2895 cpu_count++;
2896 /*
2897 * find all matching cpus on this pkg and set
2898 * the logical_node_id
2899 */
2900 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) {
2901 if ((cpus[cpux].physical_package_id == pkg) && (cpus[cpux].physical_node_id == node)) {
2902 cpus[cpux].logical_node_id = lnode;
2903 cpu_count++;
2904 }
2905 }
2906 lnode++;
2907 if (lnode > topo.nodes_per_pkg)
2908 topo.nodes_per_pkg = lnode;
2909 }
2910 if (cpu_count >= topo.max_cpu_num)
2911 break;
2912 }
2913 }
2914
get_physical_node_id(struct cpu_topology * thiscpu)2915 int get_physical_node_id(struct cpu_topology *thiscpu)
2916 {
2917 char path[80];
2918 FILE *filep;
2919 int i;
2920 int cpu = thiscpu->logical_cpu_id;
2921
2922 for (i = 0; i <= topo.max_cpu_num; i++) {
2923 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", cpu, i);
2924 filep = fopen(path, "r");
2925 if (!filep)
2926 continue;
2927 fclose(filep);
2928 return i;
2929 }
2930 return -1;
2931 }
2932
get_thread_siblings(struct cpu_topology * thiscpu)2933 int get_thread_siblings(struct cpu_topology *thiscpu)
2934 {
2935 char path[80], character;
2936 FILE *filep;
2937 unsigned long map;
2938 int so, shift, sib_core;
2939 int cpu = thiscpu->logical_cpu_id;
2940 int offset = topo.max_cpu_num + 1;
2941 size_t size;
2942 int thread_id = 0;
2943
2944 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1));
2945 if (thiscpu->thread_id < 0)
2946 thiscpu->thread_id = thread_id++;
2947 if (!thiscpu->put_ids)
2948 return -1;
2949
2950 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
2951 CPU_ZERO_S(size, thiscpu->put_ids);
2952
2953 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu);
2954 filep = fopen(path, "r");
2955
2956 if (!filep) {
2957 warnx("%s: open failed", path);
2958 return -1;
2959 }
2960 do {
2961 offset -= BITMASK_SIZE;
2962 if (fscanf(filep, "%lx%c", &map, &character) != 2)
2963 err(1, "%s: failed to parse file", path);
2964 for (shift = 0; shift < BITMASK_SIZE; shift++) {
2965 if ((map >> shift) & 0x1) {
2966 so = shift + offset;
2967 sib_core = get_core_id(so);
2968 if (sib_core == thiscpu->physical_core_id) {
2969 CPU_SET_S(so, size, thiscpu->put_ids);
2970 if ((so != cpu) && (cpus[so].thread_id < 0))
2971 cpus[so].thread_id = thread_id++;
2972 }
2973 }
2974 }
2975 } while (character == ',');
2976 fclose(filep);
2977
2978 return CPU_COUNT_S(size, thiscpu->put_ids);
2979 }
2980
2981 /*
2982 * run func(thread, core, package) in topology order
2983 * skip non-present cpus
2984 */
2985
for_all_cpus_2(int (func)(struct thread_data *,struct core_data *,struct pkg_data *,struct thread_data *,struct core_data *,struct pkg_data *),struct thread_data * thread_base,struct core_data * core_base,struct pkg_data * pkg_base,struct thread_data * thread_base2,struct core_data * core_base2,struct pkg_data * pkg_base2)2986 int for_all_cpus_2(int (func) (struct thread_data *, struct core_data *,
2987 struct pkg_data *, struct thread_data *, struct core_data *,
2988 struct pkg_data *), struct thread_data *thread_base,
2989 struct core_data *core_base, struct pkg_data *pkg_base,
2990 struct thread_data *thread_base2, struct core_data *core_base2, struct pkg_data *pkg_base2)
2991 {
2992 int retval, pkg_no, node_no, core_no, thread_no;
2993
2994 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
2995 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) {
2996 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
2997 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
2998 struct thread_data *t, *t2;
2999 struct core_data *c, *c2;
3000 struct pkg_data *p, *p2;
3001
3002 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
3003
3004 if (cpu_is_not_present(t->cpu_id))
3005 continue;
3006
3007 t2 = GET_THREAD(thread_base2, thread_no, core_no, node_no, pkg_no);
3008
3009 c = GET_CORE(core_base, core_no, node_no, pkg_no);
3010 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no);
3011
3012 p = GET_PKG(pkg_base, pkg_no);
3013 p2 = GET_PKG(pkg_base2, pkg_no);
3014
3015 retval = func(t, c, p, t2, c2, p2);
3016 if (retval)
3017 return retval;
3018 }
3019 }
3020 }
3021 }
3022 return 0;
3023 }
3024
3025 /*
3026 * run func(cpu) on every cpu in /proc/stat
3027 * return max_cpu number
3028 */
for_all_proc_cpus(int (func)(int))3029 int for_all_proc_cpus(int (func) (int))
3030 {
3031 FILE *fp;
3032 int cpu_num;
3033 int retval;
3034
3035 fp = fopen_or_die(proc_stat, "r");
3036
3037 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
3038 if (retval != 0)
3039 err(1, "%s: failed to parse format", proc_stat);
3040
3041 while (1) {
3042 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
3043 if (retval != 1)
3044 break;
3045
3046 retval = func(cpu_num);
3047 if (retval) {
3048 fclose(fp);
3049 return (retval);
3050 }
3051 }
3052 fclose(fp);
3053 return 0;
3054 }
3055
re_initialize(void)3056 void re_initialize(void)
3057 {
3058 free_all_buffers();
3059 setup_all_buffers();
3060 fprintf(outf, "turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
3061 }
3062
set_max_cpu_num(void)3063 void set_max_cpu_num(void)
3064 {
3065 FILE *filep;
3066 int base_cpu;
3067 unsigned long dummy;
3068 char pathname[64];
3069
3070 base_cpu = sched_getcpu();
3071 if (base_cpu < 0)
3072 err(1, "cannot find calling cpu ID");
3073 sprintf(pathname, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", base_cpu);
3074
3075 filep = fopen_or_die(pathname, "r");
3076 topo.max_cpu_num = 0;
3077 while (fscanf(filep, "%lx,", &dummy) == 1)
3078 topo.max_cpu_num += BITMASK_SIZE;
3079 fclose(filep);
3080 topo.max_cpu_num--; /* 0 based */
3081 }
3082
3083 /*
3084 * count_cpus()
3085 * remember the last one seen, it will be the max
3086 */
count_cpus(int cpu)3087 int count_cpus(int cpu)
3088 {
3089 UNUSED(cpu);
3090
3091 topo.num_cpus++;
3092 return 0;
3093 }
3094
mark_cpu_present(int cpu)3095 int mark_cpu_present(int cpu)
3096 {
3097 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
3098 return 0;
3099 }
3100
init_thread_id(int cpu)3101 int init_thread_id(int cpu)
3102 {
3103 cpus[cpu].thread_id = -1;
3104 return 0;
3105 }
3106
3107 /*
3108 * snapshot_proc_interrupts()
3109 *
3110 * read and record summary of /proc/interrupts
3111 *
3112 * return 1 if config change requires a restart, else return 0
3113 */
snapshot_proc_interrupts(void)3114 int snapshot_proc_interrupts(void)
3115 {
3116 static FILE *fp;
3117 int column, retval;
3118
3119 if (fp == NULL)
3120 fp = fopen_or_die("/proc/interrupts", "r");
3121 else
3122 rewind(fp);
3123
3124 /* read 1st line of /proc/interrupts to get cpu* name for each column */
3125 for (column = 0; column < topo.num_cpus; ++column) {
3126 int cpu_number;
3127
3128 retval = fscanf(fp, " CPU%d", &cpu_number);
3129 if (retval != 1)
3130 break;
3131
3132 if (cpu_number > topo.max_cpu_num) {
3133 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
3134 return 1;
3135 }
3136
3137 irq_column_2_cpu[column] = cpu_number;
3138 irqs_per_cpu[cpu_number] = 0;
3139 }
3140
3141 /* read /proc/interrupt count lines and sum up irqs per cpu */
3142 while (1) {
3143 int column;
3144 char buf[64];
3145
3146 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
3147 if (retval != 1)
3148 break;
3149
3150 /* read the count per cpu */
3151 for (column = 0; column < topo.num_cpus; ++column) {
3152
3153 int cpu_number, irq_count;
3154
3155 retval = fscanf(fp, " %d", &irq_count);
3156 if (retval != 1)
3157 break;
3158
3159 cpu_number = irq_column_2_cpu[column];
3160 irqs_per_cpu[cpu_number] += irq_count;
3161
3162 }
3163
3164 while (getc(fp) != '\n') ; /* flush interrupt description */
3165
3166 }
3167 return 0;
3168 }
3169
3170 /*
3171 * snapshot_gfx_rc6_ms()
3172 *
3173 * record snapshot of
3174 * /sys/class/drm/card0/power/rc6_residency_ms
3175 *
3176 * return 1 if config change requires a restart, else return 0
3177 */
snapshot_gfx_rc6_ms(void)3178 int snapshot_gfx_rc6_ms(void)
3179 {
3180 FILE *fp;
3181 int retval;
3182
3183 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
3184
3185 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
3186 if (retval != 1)
3187 err(1, "GFX rc6");
3188
3189 fclose(fp);
3190
3191 return 0;
3192 }
3193
3194 /*
3195 * snapshot_gfx_mhz()
3196 *
3197 * record snapshot of
3198 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
3199 *
3200 * return 1 if config change requires a restart, else return 0
3201 */
snapshot_gfx_mhz(void)3202 int snapshot_gfx_mhz(void)
3203 {
3204 static FILE *fp;
3205 int retval;
3206
3207 if (fp == NULL)
3208 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
3209 else {
3210 rewind(fp);
3211 fflush(fp);
3212 }
3213
3214 retval = fscanf(fp, "%d", &gfx_cur_mhz);
3215 if (retval != 1)
3216 err(1, "GFX MHz");
3217
3218 return 0;
3219 }
3220
3221 /*
3222 * snapshot_gfx_cur_mhz()
3223 *
3224 * record snapshot of
3225 * /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz
3226 *
3227 * return 1 if config change requires a restart, else return 0
3228 */
snapshot_gfx_act_mhz(void)3229 int snapshot_gfx_act_mhz(void)
3230 {
3231 static FILE *fp;
3232 int retval;
3233
3234 if (fp == NULL)
3235 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r");
3236 else {
3237 rewind(fp);
3238 fflush(fp);
3239 }
3240
3241 retval = fscanf(fp, "%d", &gfx_act_mhz);
3242 if (retval != 1)
3243 err(1, "GFX ACT MHz");
3244
3245 return 0;
3246 }
3247
3248 /*
3249 * snapshot_cpu_lpi()
3250 *
3251 * record snapshot of
3252 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
3253 */
snapshot_cpu_lpi_us(void)3254 int snapshot_cpu_lpi_us(void)
3255 {
3256 FILE *fp;
3257 int retval;
3258
3259 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r");
3260
3261 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us);
3262 if (retval != 1) {
3263 fprintf(stderr, "Disabling Low Power Idle CPU output\n");
3264 BIC_NOT_PRESENT(BIC_CPU_LPI);
3265 fclose(fp);
3266 return -1;
3267 }
3268
3269 fclose(fp);
3270
3271 return 0;
3272 }
3273
3274 /*
3275 * snapshot_sys_lpi()
3276 *
3277 * record snapshot of sys_lpi_file
3278 */
snapshot_sys_lpi_us(void)3279 int snapshot_sys_lpi_us(void)
3280 {
3281 FILE *fp;
3282 int retval;
3283
3284 fp = fopen_or_die(sys_lpi_file, "r");
3285
3286 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us);
3287 if (retval != 1) {
3288 fprintf(stderr, "Disabling Low Power Idle System output\n");
3289 BIC_NOT_PRESENT(BIC_SYS_LPI);
3290 fclose(fp);
3291 return -1;
3292 }
3293 fclose(fp);
3294
3295 return 0;
3296 }
3297
3298 /*
3299 * snapshot /proc and /sys files
3300 *
3301 * return 1 if configuration restart needed, else return 0
3302 */
snapshot_proc_sysfs_files(void)3303 int snapshot_proc_sysfs_files(void)
3304 {
3305 if (DO_BIC(BIC_IRQ))
3306 if (snapshot_proc_interrupts())
3307 return 1;
3308
3309 if (DO_BIC(BIC_GFX_rc6))
3310 snapshot_gfx_rc6_ms();
3311
3312 if (DO_BIC(BIC_GFXMHz))
3313 snapshot_gfx_mhz();
3314
3315 if (DO_BIC(BIC_GFXACTMHz))
3316 snapshot_gfx_act_mhz();
3317
3318 if (DO_BIC(BIC_CPU_LPI))
3319 snapshot_cpu_lpi_us();
3320
3321 if (DO_BIC(BIC_SYS_LPI))
3322 snapshot_sys_lpi_us();
3323
3324 return 0;
3325 }
3326
3327 int exit_requested;
3328
signal_handler(int signal)3329 static void signal_handler(int signal)
3330 {
3331 switch (signal) {
3332 case SIGINT:
3333 exit_requested = 1;
3334 if (debug)
3335 fprintf(stderr, " SIGINT\n");
3336 break;
3337 case SIGUSR1:
3338 if (debug > 1)
3339 fprintf(stderr, "SIGUSR1\n");
3340 break;
3341 }
3342 }
3343
setup_signal_handler(void)3344 void setup_signal_handler(void)
3345 {
3346 struct sigaction sa;
3347
3348 memset(&sa, 0, sizeof(sa));
3349
3350 sa.sa_handler = &signal_handler;
3351
3352 if (sigaction(SIGINT, &sa, NULL) < 0)
3353 err(1, "sigaction SIGINT");
3354 if (sigaction(SIGUSR1, &sa, NULL) < 0)
3355 err(1, "sigaction SIGUSR1");
3356 }
3357
do_sleep(void)3358 void do_sleep(void)
3359 {
3360 struct timeval tout;
3361 struct timespec rest;
3362 fd_set readfds;
3363 int retval;
3364
3365 FD_ZERO(&readfds);
3366 FD_SET(0, &readfds);
3367
3368 if (ignore_stdin) {
3369 nanosleep(&interval_ts, NULL);
3370 return;
3371 }
3372
3373 tout = interval_tv;
3374 retval = select(1, &readfds, NULL, NULL, &tout);
3375
3376 if (retval == 1) {
3377 switch (getc(stdin)) {
3378 case 'q':
3379 exit_requested = 1;
3380 break;
3381 case EOF:
3382 /*
3383 * 'stdin' is a pipe closed on the other end. There
3384 * won't be any further input.
3385 */
3386 ignore_stdin = 1;
3387 /* Sleep the rest of the time */
3388 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000);
3389 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000;
3390 nanosleep(&rest, NULL);
3391 }
3392 }
3393 }
3394
get_msr_sum(int cpu,off_t offset,unsigned long long * msr)3395 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr)
3396 {
3397 int ret, idx;
3398 unsigned long long msr_cur, msr_last;
3399
3400 if (!per_cpu_msr_sum)
3401 return 1;
3402
3403 idx = offset_to_idx(offset);
3404 if (idx < 0)
3405 return idx;
3406 /* get_msr_sum() = sum + (get_msr() - last) */
3407 ret = get_msr(cpu, offset, &msr_cur);
3408 if (ret)
3409 return ret;
3410 msr_last = per_cpu_msr_sum[cpu].entries[idx].last;
3411 DELTA_WRAP32(msr_cur, msr_last);
3412 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum;
3413
3414 return 0;
3415 }
3416
3417 timer_t timerid;
3418
3419 /* Timer callback, update the sum of MSRs periodically. */
update_msr_sum(struct thread_data * t,struct core_data * c,struct pkg_data * p)3420 static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3421 {
3422 int i, ret;
3423 int cpu = t->cpu_id;
3424
3425 UNUSED(c);
3426 UNUSED(p);
3427
3428 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) {
3429 unsigned long long msr_cur, msr_last;
3430 off_t offset;
3431
3432 if (!idx_valid(i))
3433 continue;
3434 offset = idx_to_offset(i);
3435 if (offset < 0)
3436 continue;
3437 ret = get_msr(cpu, offset, &msr_cur);
3438 if (ret) {
3439 fprintf(outf, "Can not update msr(0x%llx)\n", (unsigned long long)offset);
3440 continue;
3441 }
3442
3443 msr_last = per_cpu_msr_sum[cpu].entries[i].last;
3444 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff;
3445
3446 DELTA_WRAP32(msr_cur, msr_last);
3447 per_cpu_msr_sum[cpu].entries[i].sum += msr_last;
3448 }
3449 return 0;
3450 }
3451
msr_record_handler(union sigval v)3452 static void msr_record_handler(union sigval v)
3453 {
3454 UNUSED(v);
3455
3456 for_all_cpus(update_msr_sum, EVEN_COUNTERS);
3457 }
3458
msr_sum_record(void)3459 void msr_sum_record(void)
3460 {
3461 struct itimerspec its;
3462 struct sigevent sev;
3463
3464 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array));
3465 if (!per_cpu_msr_sum) {
3466 fprintf(outf, "Can not allocate memory for long time MSR.\n");
3467 return;
3468 }
3469 /*
3470 * Signal handler might be restricted, so use thread notifier instead.
3471 */
3472 memset(&sev, 0, sizeof(struct sigevent));
3473 sev.sigev_notify = SIGEV_THREAD;
3474 sev.sigev_notify_function = msr_record_handler;
3475
3476 sev.sigev_value.sival_ptr = &timerid;
3477 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) {
3478 fprintf(outf, "Can not create timer.\n");
3479 goto release_msr;
3480 }
3481
3482 its.it_value.tv_sec = 0;
3483 its.it_value.tv_nsec = 1;
3484 /*
3485 * A wraparound time has been calculated early.
3486 * Some sources state that the peak power for a
3487 * microprocessor is usually 1.5 times the TDP rating,
3488 * use 2 * TDP for safety.
3489 */
3490 its.it_interval.tv_sec = rapl_joule_counter_range / 2;
3491 its.it_interval.tv_nsec = 0;
3492
3493 if (timer_settime(timerid, 0, &its, NULL) == -1) {
3494 fprintf(outf, "Can not set timer.\n");
3495 goto release_timer;
3496 }
3497 return;
3498
3499 release_timer:
3500 timer_delete(timerid);
3501 release_msr:
3502 free(per_cpu_msr_sum);
3503 }
3504
3505 /*
3506 * set_my_sched_priority(pri)
3507 * return previous
3508 */
set_my_sched_priority(int priority)3509 int set_my_sched_priority(int priority)
3510 {
3511 int retval;
3512 int original_priority;
3513
3514 errno = 0;
3515 original_priority = getpriority(PRIO_PROCESS, 0);
3516 if (errno && (original_priority == -1))
3517 err(errno, "getpriority");
3518
3519 retval = setpriority(PRIO_PROCESS, 0, priority);
3520 if (retval)
3521 errx(retval, "capget(CAP_SYS_NICE) failed,try \"# setcap cap_sys_nice=ep %s\"", progname);
3522
3523 errno = 0;
3524 retval = getpriority(PRIO_PROCESS, 0);
3525 if (retval != priority)
3526 err(retval, "getpriority(%d) != setpriority(%d)", retval, priority);
3527
3528 return original_priority;
3529 }
3530
turbostat_loop()3531 void turbostat_loop()
3532 {
3533 int retval;
3534 int restarted = 0;
3535 unsigned int done_iters = 0;
3536
3537 setup_signal_handler();
3538
3539 /*
3540 * elevate own priority for interval mode
3541 */
3542 set_my_sched_priority(-20);
3543
3544 restart:
3545 restarted++;
3546
3547 snapshot_proc_sysfs_files();
3548 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
3549 first_counter_read = 0;
3550 if (retval < -1) {
3551 exit(retval);
3552 } else if (retval == -1) {
3553 if (restarted > 10) {
3554 exit(retval);
3555 }
3556 re_initialize();
3557 goto restart;
3558 }
3559 restarted = 0;
3560 done_iters = 0;
3561 gettimeofday(&tv_even, (struct timezone *)NULL);
3562
3563 while (1) {
3564 if (for_all_proc_cpus(cpu_is_not_present)) {
3565 re_initialize();
3566 goto restart;
3567 }
3568 do_sleep();
3569 if (snapshot_proc_sysfs_files())
3570 goto restart;
3571 retval = for_all_cpus(get_counters, ODD_COUNTERS);
3572 if (retval < -1) {
3573 exit(retval);
3574 } else if (retval == -1) {
3575 re_initialize();
3576 goto restart;
3577 }
3578 gettimeofday(&tv_odd, (struct timezone *)NULL);
3579 timersub(&tv_odd, &tv_even, &tv_delta);
3580 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
3581 re_initialize();
3582 goto restart;
3583 }
3584 compute_average(EVEN_COUNTERS);
3585 format_all_counters(EVEN_COUNTERS);
3586 flush_output_stdout();
3587 if (exit_requested)
3588 break;
3589 if (num_iterations && ++done_iters >= num_iterations)
3590 break;
3591 do_sleep();
3592 if (snapshot_proc_sysfs_files())
3593 goto restart;
3594 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
3595 if (retval < -1) {
3596 exit(retval);
3597 } else if (retval == -1) {
3598 re_initialize();
3599 goto restart;
3600 }
3601 gettimeofday(&tv_even, (struct timezone *)NULL);
3602 timersub(&tv_even, &tv_odd, &tv_delta);
3603 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
3604 re_initialize();
3605 goto restart;
3606 }
3607 compute_average(ODD_COUNTERS);
3608 format_all_counters(ODD_COUNTERS);
3609 flush_output_stdout();
3610 if (exit_requested)
3611 break;
3612 if (num_iterations && ++done_iters >= num_iterations)
3613 break;
3614 }
3615 }
3616
check_dev_msr()3617 void check_dev_msr()
3618 {
3619 struct stat sb;
3620 char pathname[32];
3621
3622 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
3623 if (stat(pathname, &sb))
3624 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
3625 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
3626 }
3627
3628 /*
3629 * check for CAP_SYS_RAWIO
3630 * return 0 on success
3631 * return 1 on fail
3632 */
check_for_cap_sys_rawio(void)3633 int check_for_cap_sys_rawio(void)
3634 {
3635 cap_t caps;
3636 cap_flag_value_t cap_flag_value;
3637
3638 caps = cap_get_proc();
3639 if (caps == NULL)
3640 err(-6, "cap_get_proc\n");
3641
3642 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value))
3643 err(-6, "cap_get\n");
3644
3645 if (cap_flag_value != CAP_SET) {
3646 warnx("capget(CAP_SYS_RAWIO) failed," " try \"# setcap cap_sys_rawio=ep %s\"", progname);
3647 return 1;
3648 }
3649
3650 if (cap_free(caps) == -1)
3651 err(-6, "cap_free\n");
3652
3653 return 0;
3654 }
3655
check_permissions(void)3656 void check_permissions(void)
3657 {
3658 int do_exit = 0;
3659 char pathname[32];
3660
3661 /* check for CAP_SYS_RAWIO */
3662 do_exit += check_for_cap_sys_rawio();
3663
3664 /* test file permissions */
3665 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
3666 if (euidaccess(pathname, R_OK)) {
3667 do_exit++;
3668 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
3669 }
3670
3671 /* if all else fails, thell them to be root */
3672 if (do_exit)
3673 if (getuid() != 0)
3674 warnx("... or simply run as root");
3675
3676 if (do_exit)
3677 exit(-6);
3678 }
3679
3680 /*
3681 * NHM adds support for additional MSRs:
3682 *
3683 * MSR_SMI_COUNT 0x00000034
3684 *
3685 * MSR_PLATFORM_INFO 0x000000ce
3686 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
3687 *
3688 * MSR_MISC_PWR_MGMT 0x000001aa
3689 *
3690 * MSR_PKG_C3_RESIDENCY 0x000003f8
3691 * MSR_PKG_C6_RESIDENCY 0x000003f9
3692 * MSR_CORE_C3_RESIDENCY 0x000003fc
3693 * MSR_CORE_C6_RESIDENCY 0x000003fd
3694 *
3695 * Side effect:
3696 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL
3697 * sets has_misc_feature_control
3698 */
probe_nhm_msrs(unsigned int family,unsigned int model)3699 int probe_nhm_msrs(unsigned int family, unsigned int model)
3700 {
3701 unsigned long long msr;
3702 unsigned int base_ratio;
3703 int *pkg_cstate_limits;
3704
3705 if (!genuine_intel)
3706 return 0;
3707
3708 if (family != 6)
3709 return 0;
3710
3711 bclk = discover_bclk(family, model);
3712
3713 switch (model) {
3714 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
3715 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
3716 pkg_cstate_limits = nhm_pkg_cstate_limits;
3717 break;
3718 case INTEL_FAM6_SANDYBRIDGE: /* SNB */
3719 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */
3720 case INTEL_FAM6_IVYBRIDGE: /* IVB */
3721 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3722 pkg_cstate_limits = snb_pkg_cstate_limits;
3723 has_misc_feature_control = 1;
3724 break;
3725 case INTEL_FAM6_HASWELL: /* HSW */
3726 case INTEL_FAM6_HASWELL_G: /* HSW */
3727 case INTEL_FAM6_HASWELL_X: /* HSX */
3728 case INTEL_FAM6_HASWELL_L: /* HSW */
3729 case INTEL_FAM6_BROADWELL: /* BDW */
3730 case INTEL_FAM6_BROADWELL_G: /* BDW */
3731 case INTEL_FAM6_BROADWELL_X: /* BDX */
3732 case INTEL_FAM6_SKYLAKE_L: /* SKL */
3733 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
3734 pkg_cstate_limits = hsw_pkg_cstate_limits;
3735 has_misc_feature_control = 1;
3736 break;
3737 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3738 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
3739 pkg_cstate_limits = skx_pkg_cstate_limits;
3740 has_misc_feature_control = 1;
3741 break;
3742 case INTEL_FAM6_ICELAKE_X: /* ICX */
3743 pkg_cstate_limits = icx_pkg_cstate_limits;
3744 has_misc_feature_control = 1;
3745 break;
3746 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
3747 no_MSR_MISC_PWR_MGMT = 1;
3748 /* FALLTHRU */
3749 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
3750 pkg_cstate_limits = slv_pkg_cstate_limits;
3751 break;
3752 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
3753 pkg_cstate_limits = amt_pkg_cstate_limits;
3754 no_MSR_MISC_PWR_MGMT = 1;
3755 break;
3756 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
3757 pkg_cstate_limits = phi_pkg_cstate_limits;
3758 break;
3759 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3760 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
3761 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
3762 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
3763 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
3764 pkg_cstate_limits = glm_pkg_cstate_limits;
3765 break;
3766 default:
3767 return 0;
3768 }
3769 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
3770 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
3771
3772 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
3773 base_ratio = (msr >> 8) & 0xFF;
3774
3775 base_hz = base_ratio * bclk * 1000000;
3776 has_base_hz = 1;
3777 return 1;
3778 }
3779
3780 /*
3781 * SLV client has support for unique MSRs:
3782 *
3783 * MSR_CC6_DEMOTION_POLICY_CONFIG
3784 * MSR_MC6_DEMOTION_POLICY_CONFIG
3785 */
3786
has_slv_msrs(unsigned int family,unsigned int model)3787 int has_slv_msrs(unsigned int family, unsigned int model)
3788 {
3789 if (!genuine_intel)
3790 return 0;
3791
3792 if (family != 6)
3793 return 0;
3794
3795 switch (model) {
3796 case INTEL_FAM6_ATOM_SILVERMONT:
3797 case INTEL_FAM6_ATOM_SILVERMONT_MID:
3798 case INTEL_FAM6_ATOM_AIRMONT_MID:
3799 return 1;
3800 }
3801 return 0;
3802 }
3803
is_dnv(unsigned int family,unsigned int model)3804 int is_dnv(unsigned int family, unsigned int model)
3805 {
3806
3807 if (!genuine_intel)
3808 return 0;
3809
3810 if (family != 6)
3811 return 0;
3812
3813 switch (model) {
3814 case INTEL_FAM6_ATOM_GOLDMONT_D:
3815 return 1;
3816 }
3817 return 0;
3818 }
3819
is_bdx(unsigned int family,unsigned int model)3820 int is_bdx(unsigned int family, unsigned int model)
3821 {
3822
3823 if (!genuine_intel)
3824 return 0;
3825
3826 if (family != 6)
3827 return 0;
3828
3829 switch (model) {
3830 case INTEL_FAM6_BROADWELL_X:
3831 return 1;
3832 }
3833 return 0;
3834 }
3835
is_skx(unsigned int family,unsigned int model)3836 int is_skx(unsigned int family, unsigned int model)
3837 {
3838
3839 if (!genuine_intel)
3840 return 0;
3841
3842 if (family != 6)
3843 return 0;
3844
3845 switch (model) {
3846 case INTEL_FAM6_SKYLAKE_X:
3847 return 1;
3848 }
3849 return 0;
3850 }
3851
is_icx(unsigned int family,unsigned int model)3852 int is_icx(unsigned int family, unsigned int model)
3853 {
3854
3855 if (!genuine_intel)
3856 return 0;
3857
3858 if (family != 6)
3859 return 0;
3860
3861 switch (model) {
3862 case INTEL_FAM6_ICELAKE_X:
3863 return 1;
3864 }
3865 return 0;
3866 }
3867
is_spr(unsigned int family,unsigned int model)3868 int is_spr(unsigned int family, unsigned int model)
3869 {
3870
3871 if (!genuine_intel)
3872 return 0;
3873
3874 if (family != 6)
3875 return 0;
3876
3877 switch (model) {
3878 case INTEL_FAM6_SAPPHIRERAPIDS_X:
3879 return 1;
3880 }
3881 return 0;
3882 }
3883
is_ehl(unsigned int family,unsigned int model)3884 int is_ehl(unsigned int family, unsigned int model)
3885 {
3886 if (!genuine_intel)
3887 return 0;
3888
3889 if (family != 6)
3890 return 0;
3891
3892 switch (model) {
3893 case INTEL_FAM6_ATOM_TREMONT:
3894 return 1;
3895 }
3896 return 0;
3897 }
3898
is_jvl(unsigned int family,unsigned int model)3899 int is_jvl(unsigned int family, unsigned int model)
3900 {
3901 if (!genuine_intel)
3902 return 0;
3903
3904 if (family != 6)
3905 return 0;
3906
3907 switch (model) {
3908 case INTEL_FAM6_ATOM_TREMONT_D:
3909 return 1;
3910 }
3911 return 0;
3912 }
3913
has_turbo_ratio_limit(unsigned int family,unsigned int model)3914 int has_turbo_ratio_limit(unsigned int family, unsigned int model)
3915 {
3916 if (has_slv_msrs(family, model))
3917 return 0;
3918
3919 if (family != 6)
3920 return 0;
3921
3922 switch (model) {
3923 /* Nehalem compatible, but do not include turbo-ratio limit support */
3924 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
3925 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
3926 return 0;
3927 default:
3928 return 1;
3929 }
3930 }
3931
has_atom_turbo_ratio_limit(unsigned int family,unsigned int model)3932 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model)
3933 {
3934 if (has_slv_msrs(family, model))
3935 return 1;
3936
3937 return 0;
3938 }
3939
has_ivt_turbo_ratio_limit(unsigned int family,unsigned int model)3940 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
3941 {
3942 if (!genuine_intel)
3943 return 0;
3944
3945 if (family != 6)
3946 return 0;
3947
3948 switch (model) {
3949 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3950 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
3951 return 1;
3952 default:
3953 return 0;
3954 }
3955 }
3956
has_hsw_turbo_ratio_limit(unsigned int family,unsigned int model)3957 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
3958 {
3959 if (!genuine_intel)
3960 return 0;
3961
3962 if (family != 6)
3963 return 0;
3964
3965 switch (model) {
3966 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
3967 return 1;
3968 default:
3969 return 0;
3970 }
3971 }
3972
has_knl_turbo_ratio_limit(unsigned int family,unsigned int model)3973 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
3974 {
3975 if (!genuine_intel)
3976 return 0;
3977
3978 if (family != 6)
3979 return 0;
3980
3981 switch (model) {
3982 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
3983 return 1;
3984 default:
3985 return 0;
3986 }
3987 }
3988
has_glm_turbo_ratio_limit(unsigned int family,unsigned int model)3989 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model)
3990 {
3991 if (!genuine_intel)
3992 return 0;
3993
3994 if (family != 6)
3995 return 0;
3996
3997 switch (model) {
3998 case INTEL_FAM6_ATOM_GOLDMONT:
3999 case INTEL_FAM6_SKYLAKE_X:
4000 case INTEL_FAM6_ICELAKE_X:
4001 case INTEL_FAM6_SAPPHIRERAPIDS_X:
4002 return 1;
4003 default:
4004 return 0;
4005 }
4006 }
4007
has_config_tdp(unsigned int family,unsigned int model)4008 int has_config_tdp(unsigned int family, unsigned int model)
4009 {
4010 if (!genuine_intel)
4011 return 0;
4012
4013 if (family != 6)
4014 return 0;
4015
4016 switch (model) {
4017 case INTEL_FAM6_IVYBRIDGE: /* IVB */
4018 case INTEL_FAM6_HASWELL: /* HSW */
4019 case INTEL_FAM6_HASWELL_X: /* HSX */
4020 case INTEL_FAM6_HASWELL_L: /* HSW */
4021 case INTEL_FAM6_HASWELL_G: /* HSW */
4022 case INTEL_FAM6_BROADWELL: /* BDW */
4023 case INTEL_FAM6_BROADWELL_G: /* BDW */
4024 case INTEL_FAM6_BROADWELL_X: /* BDX */
4025 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4026 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4027 case INTEL_FAM6_SKYLAKE_X: /* SKX */
4028 case INTEL_FAM6_ICELAKE_X: /* ICX */
4029 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
4030 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
4031 return 1;
4032 default:
4033 return 0;
4034 }
4035 }
4036
4037 /*
4038 * tcc_offset_bits:
4039 * 0: Tcc Offset not supported (Default)
4040 * 6: Bit 29:24 of MSR_PLATFORM_INFO
4041 * 4: Bit 27:24 of MSR_PLATFORM_INFO
4042 */
check_tcc_offset(int model)4043 void check_tcc_offset(int model)
4044 {
4045 unsigned long long msr;
4046
4047 if (!genuine_intel)
4048 return;
4049
4050 switch (model) {
4051 case INTEL_FAM6_SKYLAKE_L:
4052 case INTEL_FAM6_SKYLAKE:
4053 case INTEL_FAM6_KABYLAKE_L:
4054 case INTEL_FAM6_KABYLAKE:
4055 case INTEL_FAM6_ICELAKE_L:
4056 case INTEL_FAM6_ICELAKE:
4057 case INTEL_FAM6_TIGERLAKE_L:
4058 case INTEL_FAM6_TIGERLAKE:
4059 case INTEL_FAM6_COMETLAKE:
4060 if (!get_msr(base_cpu, MSR_PLATFORM_INFO, &msr)) {
4061 msr = (msr >> 30) & 1;
4062 if (msr)
4063 tcc_offset_bits = 6;
4064 }
4065 return;
4066 default:
4067 return;
4068 }
4069 }
4070
remove_underbar(char * s)4071 static void remove_underbar(char *s)
4072 {
4073 char *to = s;
4074
4075 while (*s) {
4076 if (*s != '_')
4077 *to++ = *s;
4078 s++;
4079 }
4080
4081 *to = 0;
4082 }
4083
dump_turbo_ratio_info(unsigned int family,unsigned int model)4084 static void dump_turbo_ratio_info(unsigned int family, unsigned int model)
4085 {
4086 if (!has_turbo)
4087 return;
4088
4089 if (has_hsw_turbo_ratio_limit(family, model))
4090 dump_hsw_turbo_ratio_limits();
4091
4092 if (has_ivt_turbo_ratio_limit(family, model))
4093 dump_ivt_turbo_ratio_limits();
4094
4095 if (has_turbo_ratio_limit(family, model)) {
4096 dump_turbo_ratio_limits(MSR_TURBO_RATIO_LIMIT, family, model);
4097
4098 if (is_hybrid)
4099 dump_turbo_ratio_limits(MSR_SECONDARY_TURBO_RATIO_LIMIT, family, model);
4100 }
4101
4102 if (has_atom_turbo_ratio_limit(family, model))
4103 dump_atom_turbo_ratio_limits();
4104
4105 if (has_knl_turbo_ratio_limit(family, model))
4106 dump_knl_turbo_ratio_limits();
4107
4108 if (has_config_tdp(family, model))
4109 dump_config_tdp();
4110 }
4111
dump_cstate_pstate_config_info(unsigned int family,unsigned int model)4112 static void dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
4113 {
4114 if (!do_nhm_platform_info)
4115 return;
4116
4117 dump_nhm_platform_info();
4118 dump_turbo_ratio_info(family, model);
4119 dump_nhm_cst_cfg();
4120 }
4121
read_sysfs_int(char * path)4122 static int read_sysfs_int(char *path)
4123 {
4124 FILE *input;
4125 int retval = -1;
4126
4127 input = fopen(path, "r");
4128 if (input == NULL) {
4129 if (debug)
4130 fprintf(outf, "NSFOD %s\n", path);
4131 return (-1);
4132 }
4133 if (fscanf(input, "%d", &retval) != 1)
4134 err(1, "%s: failed to read int from file", path);
4135 fclose(input);
4136
4137 return (retval);
4138 }
4139
dump_sysfs_file(char * path)4140 static void dump_sysfs_file(char *path)
4141 {
4142 FILE *input;
4143 char cpuidle_buf[64];
4144
4145 input = fopen(path, "r");
4146 if (input == NULL) {
4147 if (debug)
4148 fprintf(outf, "NSFOD %s\n", path);
4149 return;
4150 }
4151 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input))
4152 err(1, "%s: failed to read file", path);
4153 fclose(input);
4154
4155 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf);
4156 }
4157
intel_uncore_frequency_probe(void)4158 static void intel_uncore_frequency_probe(void)
4159 {
4160 int i, j;
4161 char path[128];
4162
4163 if (!genuine_intel)
4164 return;
4165
4166 if (access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00", R_OK))
4167 return;
4168
4169 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/current_freq_khz", R_OK))
4170 BIC_PRESENT(BIC_UNCORE_MHZ);
4171
4172 if (quiet)
4173 return;
4174
4175 for (i = 0; i < topo.num_packages; ++i) {
4176 for (j = 0; j < topo.num_die; ++j) {
4177 int k, l;
4178
4179 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/min_freq_khz",
4180 i, j);
4181 k = read_sysfs_int(path);
4182 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/max_freq_khz",
4183 i, j);
4184 l = read_sysfs_int(path);
4185 fprintf(outf, "Uncore Frequency pkg%d die%d: %d - %d MHz ", i, j, k / 1000, l / 1000);
4186
4187 sprintf(path,
4188 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_min_freq_khz",
4189 i, j);
4190 k = read_sysfs_int(path);
4191 sprintf(path,
4192 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_max_freq_khz",
4193 i, j);
4194 l = read_sysfs_int(path);
4195 fprintf(outf, "(%d - %d MHz)\n", k / 1000, l / 1000);
4196 }
4197 }
4198 }
4199
dump_sysfs_cstate_config(void)4200 static void dump_sysfs_cstate_config(void)
4201 {
4202 char path[64];
4203 char name_buf[16];
4204 char desc[64];
4205 FILE *input;
4206 int state;
4207 char *sp;
4208
4209 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) {
4210 fprintf(outf, "cpuidle not loaded\n");
4211 return;
4212 }
4213
4214 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver");
4215 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor");
4216 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro");
4217
4218 for (state = 0; state < 10; ++state) {
4219
4220 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
4221 input = fopen(path, "r");
4222 if (input == NULL)
4223 continue;
4224 if (!fgets(name_buf, sizeof(name_buf), input))
4225 err(1, "%s: failed to read file", path);
4226
4227 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
4228 sp = strchr(name_buf, '-');
4229 if (!sp)
4230 sp = strchrnul(name_buf, '\n');
4231 *sp = '\0';
4232 fclose(input);
4233
4234 remove_underbar(name_buf);
4235
4236 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", base_cpu, state);
4237 input = fopen(path, "r");
4238 if (input == NULL)
4239 continue;
4240 if (!fgets(desc, sizeof(desc), input))
4241 err(1, "%s: failed to read file", path);
4242
4243 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc);
4244 fclose(input);
4245 }
4246 }
4247
dump_sysfs_pstate_config(void)4248 static void dump_sysfs_pstate_config(void)
4249 {
4250 char path[64];
4251 char driver_buf[64];
4252 char governor_buf[64];
4253 FILE *input;
4254 int turbo;
4255
4256 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", base_cpu);
4257 input = fopen(path, "r");
4258 if (input == NULL) {
4259 fprintf(outf, "NSFOD %s\n", path);
4260 return;
4261 }
4262 if (!fgets(driver_buf, sizeof(driver_buf), input))
4263 err(1, "%s: failed to read file", path);
4264 fclose(input);
4265
4266 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", base_cpu);
4267 input = fopen(path, "r");
4268 if (input == NULL) {
4269 fprintf(outf, "NSFOD %s\n", path);
4270 return;
4271 }
4272 if (!fgets(governor_buf, sizeof(governor_buf), input))
4273 err(1, "%s: failed to read file", path);
4274 fclose(input);
4275
4276 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf);
4277 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf);
4278
4279 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost");
4280 input = fopen(path, "r");
4281 if (input != NULL) {
4282 if (fscanf(input, "%d", &turbo) != 1)
4283 err(1, "%s: failed to parse number from file", path);
4284 fprintf(outf, "cpufreq boost: %d\n", turbo);
4285 fclose(input);
4286 }
4287
4288 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo");
4289 input = fopen(path, "r");
4290 if (input != NULL) {
4291 if (fscanf(input, "%d", &turbo) != 1)
4292 err(1, "%s: failed to parse number from file", path);
4293 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo);
4294 fclose(input);
4295 }
4296 }
4297
4298 /*
4299 * print_epb()
4300 * Decode the ENERGY_PERF_BIAS MSR
4301 */
print_epb(struct thread_data * t,struct core_data * c,struct pkg_data * p)4302 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4303 {
4304 char *epb_string;
4305 int cpu, epb;
4306
4307 UNUSED(c);
4308 UNUSED(p);
4309
4310 if (!has_epb)
4311 return 0;
4312
4313 cpu = t->cpu_id;
4314
4315 /* EPB is per-package */
4316 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4317 return 0;
4318
4319 if (cpu_migrate(cpu)) {
4320 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu);
4321 return -1;
4322 }
4323
4324 epb = get_epb(cpu);
4325 if (epb < 0)
4326 return 0;
4327
4328 switch (epb) {
4329 case ENERGY_PERF_BIAS_PERFORMANCE:
4330 epb_string = "performance";
4331 break;
4332 case ENERGY_PERF_BIAS_NORMAL:
4333 epb_string = "balanced";
4334 break;
4335 case ENERGY_PERF_BIAS_POWERSAVE:
4336 epb_string = "powersave";
4337 break;
4338 default:
4339 epb_string = "custom";
4340 break;
4341 }
4342 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string);
4343
4344 return 0;
4345 }
4346
4347 /*
4348 * print_hwp()
4349 * Decode the MSR_HWP_CAPABILITIES
4350 */
print_hwp(struct thread_data * t,struct core_data * c,struct pkg_data * p)4351 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4352 {
4353 unsigned long long msr;
4354 int cpu;
4355
4356 UNUSED(c);
4357 UNUSED(p);
4358
4359 if (!has_hwp)
4360 return 0;
4361
4362 cpu = t->cpu_id;
4363
4364 /* MSR_HWP_CAPABILITIES is per-package */
4365 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4366 return 0;
4367
4368 if (cpu_migrate(cpu)) {
4369 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu);
4370 return -1;
4371 }
4372
4373 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
4374 return 0;
4375
4376 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", cpu, msr, (msr & (1 << 0)) ? "" : "No-");
4377
4378 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
4379 if ((msr & (1 << 0)) == 0)
4380 return 0;
4381
4382 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
4383 return 0;
4384
4385 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
4386 "(high %d guar %d eff %d low %d)\n",
4387 cpu, msr,
4388 (unsigned int)HWP_HIGHEST_PERF(msr),
4389 (unsigned int)HWP_GUARANTEED_PERF(msr),
4390 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), (unsigned int)HWP_LOWEST_PERF(msr));
4391
4392 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
4393 return 0;
4394
4395 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
4396 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n",
4397 cpu, msr,
4398 (unsigned int)(((msr) >> 0) & 0xff),
4399 (unsigned int)(((msr) >> 8) & 0xff),
4400 (unsigned int)(((msr) >> 16) & 0xff),
4401 (unsigned int)(((msr) >> 24) & 0xff),
4402 (unsigned int)(((msr) >> 32) & 0xff3), (unsigned int)(((msr) >> 42) & 0x1));
4403
4404 if (has_hwp_pkg) {
4405 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
4406 return 0;
4407
4408 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
4409 "(min %d max %d des %d epp 0x%x window 0x%x)\n",
4410 cpu, msr,
4411 (unsigned int)(((msr) >> 0) & 0xff),
4412 (unsigned int)(((msr) >> 8) & 0xff),
4413 (unsigned int)(((msr) >> 16) & 0xff),
4414 (unsigned int)(((msr) >> 24) & 0xff), (unsigned int)(((msr) >> 32) & 0xff3));
4415 }
4416 if (has_hwp_notify) {
4417 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
4418 return 0;
4419
4420 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
4421 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
4422 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis");
4423 }
4424 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
4425 return 0;
4426
4427 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
4428 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
4429 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x4) ? "" : "No-");
4430
4431 return 0;
4432 }
4433
4434 /*
4435 * print_perf_limit()
4436 */
print_perf_limit(struct thread_data * t,struct core_data * c,struct pkg_data * p)4437 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4438 {
4439 unsigned long long msr;
4440 int cpu;
4441
4442 UNUSED(c);
4443 UNUSED(p);
4444
4445 cpu = t->cpu_id;
4446
4447 /* per-package */
4448 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4449 return 0;
4450
4451 if (cpu_migrate(cpu)) {
4452 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu);
4453 return -1;
4454 }
4455
4456 if (do_core_perf_limit_reasons) {
4457 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
4458 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4459 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
4460 (msr & 1 << 15) ? "bit15, " : "",
4461 (msr & 1 << 14) ? "bit14, " : "",
4462 (msr & 1 << 13) ? "Transitions, " : "",
4463 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
4464 (msr & 1 << 11) ? "PkgPwrL2, " : "",
4465 (msr & 1 << 10) ? "PkgPwrL1, " : "",
4466 (msr & 1 << 9) ? "CorePwr, " : "",
4467 (msr & 1 << 8) ? "Amps, " : "",
4468 (msr & 1 << 6) ? "VR-Therm, " : "",
4469 (msr & 1 << 5) ? "Auto-HWP, " : "",
4470 (msr & 1 << 4) ? "Graphics, " : "",
4471 (msr & 1 << 2) ? "bit2, " : "",
4472 (msr & 1 << 1) ? "ThermStatus, " : "", (msr & 1 << 0) ? "PROCHOT, " : "");
4473 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
4474 (msr & 1 << 31) ? "bit31, " : "",
4475 (msr & 1 << 30) ? "bit30, " : "",
4476 (msr & 1 << 29) ? "Transitions, " : "",
4477 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
4478 (msr & 1 << 27) ? "PkgPwrL2, " : "",
4479 (msr & 1 << 26) ? "PkgPwrL1, " : "",
4480 (msr & 1 << 25) ? "CorePwr, " : "",
4481 (msr & 1 << 24) ? "Amps, " : "",
4482 (msr & 1 << 22) ? "VR-Therm, " : "",
4483 (msr & 1 << 21) ? "Auto-HWP, " : "",
4484 (msr & 1 << 20) ? "Graphics, " : "",
4485 (msr & 1 << 18) ? "bit18, " : "",
4486 (msr & 1 << 17) ? "ThermStatus, " : "", (msr & 1 << 16) ? "PROCHOT, " : "");
4487
4488 }
4489 if (do_gfx_perf_limit_reasons) {
4490 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
4491 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4492 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
4493 (msr & 1 << 0) ? "PROCHOT, " : "",
4494 (msr & 1 << 1) ? "ThermStatus, " : "",
4495 (msr & 1 << 4) ? "Graphics, " : "",
4496 (msr & 1 << 6) ? "VR-Therm, " : "",
4497 (msr & 1 << 8) ? "Amps, " : "",
4498 (msr & 1 << 9) ? "GFXPwr, " : "",
4499 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
4500 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
4501 (msr & 1 << 16) ? "PROCHOT, " : "",
4502 (msr & 1 << 17) ? "ThermStatus, " : "",
4503 (msr & 1 << 20) ? "Graphics, " : "",
4504 (msr & 1 << 22) ? "VR-Therm, " : "",
4505 (msr & 1 << 24) ? "Amps, " : "",
4506 (msr & 1 << 25) ? "GFXPwr, " : "",
4507 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
4508 }
4509 if (do_ring_perf_limit_reasons) {
4510 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
4511 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4512 fprintf(outf, " (Active: %s%s%s%s%s%s)",
4513 (msr & 1 << 0) ? "PROCHOT, " : "",
4514 (msr & 1 << 1) ? "ThermStatus, " : "",
4515 (msr & 1 << 6) ? "VR-Therm, " : "",
4516 (msr & 1 << 8) ? "Amps, " : "",
4517 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
4518 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
4519 (msr & 1 << 16) ? "PROCHOT, " : "",
4520 (msr & 1 << 17) ? "ThermStatus, " : "",
4521 (msr & 1 << 22) ? "VR-Therm, " : "",
4522 (msr & 1 << 24) ? "Amps, " : "",
4523 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
4524 }
4525 return 0;
4526 }
4527
4528 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
4529 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
4530
get_tdp_intel(unsigned int model)4531 double get_tdp_intel(unsigned int model)
4532 {
4533 unsigned long long msr;
4534
4535 if (do_rapl & RAPL_PKG_POWER_INFO)
4536 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
4537 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
4538
4539 switch (model) {
4540 case INTEL_FAM6_ATOM_SILVERMONT:
4541 case INTEL_FAM6_ATOM_SILVERMONT_D:
4542 return 30.0;
4543 default:
4544 return 135.0;
4545 }
4546 }
4547
get_tdp_amd(unsigned int family)4548 double get_tdp_amd(unsigned int family)
4549 {
4550 UNUSED(family);
4551
4552 /* This is the max stock TDP of HEDT/Server Fam17h+ chips */
4553 return 280.0;
4554 }
4555
4556 /*
4557 * rapl_dram_energy_units_probe()
4558 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
4559 */
rapl_dram_energy_units_probe(int model,double rapl_energy_units)4560 static double rapl_dram_energy_units_probe(int model, double rapl_energy_units)
4561 {
4562 /* only called for genuine_intel, family 6 */
4563
4564 switch (model) {
4565 case INTEL_FAM6_HASWELL_X: /* HSX */
4566 case INTEL_FAM6_BROADWELL_X: /* BDX */
4567 case INTEL_FAM6_SKYLAKE_X: /* SKX */
4568 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
4569 case INTEL_FAM6_ICELAKE_X: /* ICX */
4570 return (rapl_dram_energy_units = 15.3 / 1000000);
4571 default:
4572 return (rapl_energy_units);
4573 }
4574 }
4575
rapl_probe_intel(unsigned int family,unsigned int model)4576 void rapl_probe_intel(unsigned int family, unsigned int model)
4577 {
4578 unsigned long long msr;
4579 unsigned int time_unit;
4580 double tdp;
4581
4582 if (family != 6)
4583 return;
4584
4585 switch (model) {
4586 case INTEL_FAM6_SANDYBRIDGE:
4587 case INTEL_FAM6_IVYBRIDGE:
4588 case INTEL_FAM6_HASWELL: /* HSW */
4589 case INTEL_FAM6_HASWELL_L: /* HSW */
4590 case INTEL_FAM6_HASWELL_G: /* HSW */
4591 case INTEL_FAM6_BROADWELL: /* BDW */
4592 case INTEL_FAM6_BROADWELL_G: /* BDW */
4593 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
4594 if (rapl_joules) {
4595 BIC_PRESENT(BIC_Pkg_J);
4596 BIC_PRESENT(BIC_Cor_J);
4597 BIC_PRESENT(BIC_GFX_J);
4598 } else {
4599 BIC_PRESENT(BIC_PkgWatt);
4600 BIC_PRESENT(BIC_CorWatt);
4601 BIC_PRESENT(BIC_GFXWatt);
4602 }
4603 break;
4604 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
4605 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4606 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
4607 if (rapl_joules)
4608 BIC_PRESENT(BIC_Pkg_J);
4609 else
4610 BIC_PRESENT(BIC_PkgWatt);
4611 break;
4612 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
4613 do_rapl =
4614 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS
4615 | RAPL_GFX | RAPL_PKG_POWER_INFO;
4616 if (rapl_joules) {
4617 BIC_PRESENT(BIC_Pkg_J);
4618 BIC_PRESENT(BIC_Cor_J);
4619 BIC_PRESENT(BIC_RAM_J);
4620 BIC_PRESENT(BIC_GFX_J);
4621 } else {
4622 BIC_PRESENT(BIC_PkgWatt);
4623 BIC_PRESENT(BIC_CorWatt);
4624 BIC_PRESENT(BIC_RAMWatt);
4625 BIC_PRESENT(BIC_GFXWatt);
4626 }
4627 break;
4628 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
4629 do_rapl = RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
4630 BIC_PRESENT(BIC_PKG__);
4631 if (rapl_joules)
4632 BIC_PRESENT(BIC_Pkg_J);
4633 else
4634 BIC_PRESENT(BIC_PkgWatt);
4635 break;
4636 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4637 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4638 do_rapl =
4639 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS
4640 | RAPL_GFX | RAPL_PKG_POWER_INFO;
4641 BIC_PRESENT(BIC_PKG__);
4642 BIC_PRESENT(BIC_RAM__);
4643 if (rapl_joules) {
4644 BIC_PRESENT(BIC_Pkg_J);
4645 BIC_PRESENT(BIC_Cor_J);
4646 BIC_PRESENT(BIC_RAM_J);
4647 BIC_PRESENT(BIC_GFX_J);
4648 } else {
4649 BIC_PRESENT(BIC_PkgWatt);
4650 BIC_PRESENT(BIC_CorWatt);
4651 BIC_PRESENT(BIC_RAMWatt);
4652 BIC_PRESENT(BIC_GFXWatt);
4653 }
4654 break;
4655 case INTEL_FAM6_HASWELL_X: /* HSX */
4656 case INTEL_FAM6_BROADWELL_X: /* BDX */
4657 case INTEL_FAM6_SKYLAKE_X: /* SKX */
4658 case INTEL_FAM6_ICELAKE_X: /* ICX */
4659 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
4660 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
4661 do_rapl =
4662 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
4663 RAPL_PKG_POWER_INFO;
4664 BIC_PRESENT(BIC_PKG__);
4665 BIC_PRESENT(BIC_RAM__);
4666 if (rapl_joules) {
4667 BIC_PRESENT(BIC_Pkg_J);
4668 BIC_PRESENT(BIC_RAM_J);
4669 } else {
4670 BIC_PRESENT(BIC_PkgWatt);
4671 BIC_PRESENT(BIC_RAMWatt);
4672 }
4673 break;
4674 case INTEL_FAM6_SANDYBRIDGE_X:
4675 case INTEL_FAM6_IVYBRIDGE_X:
4676 do_rapl =
4677 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS |
4678 RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
4679 BIC_PRESENT(BIC_PKG__);
4680 BIC_PRESENT(BIC_RAM__);
4681 if (rapl_joules) {
4682 BIC_PRESENT(BIC_Pkg_J);
4683 BIC_PRESENT(BIC_Cor_J);
4684 BIC_PRESENT(BIC_RAM_J);
4685 } else {
4686 BIC_PRESENT(BIC_PkgWatt);
4687 BIC_PRESENT(BIC_CorWatt);
4688 BIC_PRESENT(BIC_RAMWatt);
4689 }
4690 break;
4691 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
4692 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
4693 do_rapl = RAPL_PKG | RAPL_CORES;
4694 if (rapl_joules) {
4695 BIC_PRESENT(BIC_Pkg_J);
4696 BIC_PRESENT(BIC_Cor_J);
4697 } else {
4698 BIC_PRESENT(BIC_PkgWatt);
4699 BIC_PRESENT(BIC_CorWatt);
4700 }
4701 break;
4702 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
4703 do_rapl =
4704 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
4705 RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
4706 BIC_PRESENT(BIC_PKG__);
4707 BIC_PRESENT(BIC_RAM__);
4708 if (rapl_joules) {
4709 BIC_PRESENT(BIC_Pkg_J);
4710 BIC_PRESENT(BIC_Cor_J);
4711 BIC_PRESENT(BIC_RAM_J);
4712 } else {
4713 BIC_PRESENT(BIC_PkgWatt);
4714 BIC_PRESENT(BIC_CorWatt);
4715 BIC_PRESENT(BIC_RAMWatt);
4716 }
4717 break;
4718 default:
4719 return;
4720 }
4721
4722 /* units on package 0, verify later other packages match */
4723 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
4724 return;
4725
4726 rapl_power_units = 1.0 / (1 << (msr & 0xF));
4727 if (model == INTEL_FAM6_ATOM_SILVERMONT)
4728 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
4729 else
4730 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
4731
4732 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
4733
4734 time_unit = msr >> 16 & 0xF;
4735 if (time_unit == 0)
4736 time_unit = 0xA;
4737
4738 rapl_time_units = 1.0 / (1 << (time_unit));
4739
4740 tdp = get_tdp_intel(model);
4741
4742 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
4743 if (!quiet)
4744 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
4745 }
4746
rapl_probe_amd(unsigned int family,unsigned int model)4747 void rapl_probe_amd(unsigned int family, unsigned int model)
4748 {
4749 unsigned long long msr;
4750 unsigned int eax, ebx, ecx, edx;
4751 unsigned int has_rapl = 0;
4752 double tdp;
4753
4754 UNUSED(model);
4755
4756 if (max_extended_level >= 0x80000007) {
4757 __cpuid(0x80000007, eax, ebx, ecx, edx);
4758 /* RAPL (Fam 17h+) */
4759 has_rapl = edx & (1 << 14);
4760 }
4761
4762 if (!has_rapl || family < 0x17)
4763 return;
4764
4765 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY;
4766 if (rapl_joules) {
4767 BIC_PRESENT(BIC_Pkg_J);
4768 BIC_PRESENT(BIC_Cor_J);
4769 } else {
4770 BIC_PRESENT(BIC_PkgWatt);
4771 BIC_PRESENT(BIC_CorWatt);
4772 }
4773
4774 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr))
4775 return;
4776
4777 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf));
4778 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f));
4779 rapl_power_units = ldexp(1.0, -(msr & 0xf));
4780
4781 tdp = get_tdp_amd(family);
4782
4783 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
4784 if (!quiet)
4785 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
4786 }
4787
4788 /*
4789 * rapl_probe()
4790 *
4791 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
4792 */
rapl_probe(unsigned int family,unsigned int model)4793 void rapl_probe(unsigned int family, unsigned int model)
4794 {
4795 if (genuine_intel)
4796 rapl_probe_intel(family, model);
4797 if (authentic_amd || hygon_genuine)
4798 rapl_probe_amd(family, model);
4799 }
4800
perf_limit_reasons_probe(unsigned int family,unsigned int model)4801 void perf_limit_reasons_probe(unsigned int family, unsigned int model)
4802 {
4803 if (!genuine_intel)
4804 return;
4805
4806 if (family != 6)
4807 return;
4808
4809 switch (model) {
4810 case INTEL_FAM6_HASWELL: /* HSW */
4811 case INTEL_FAM6_HASWELL_L: /* HSW */
4812 case INTEL_FAM6_HASWELL_G: /* HSW */
4813 do_gfx_perf_limit_reasons = 1;
4814 /* FALLTHRU */
4815 case INTEL_FAM6_HASWELL_X: /* HSX */
4816 do_core_perf_limit_reasons = 1;
4817 do_ring_perf_limit_reasons = 1;
4818 default:
4819 return;
4820 }
4821 }
4822
automatic_cstate_conversion_probe(unsigned int family,unsigned int model)4823 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model)
4824 {
4825 if (family != 6)
4826 return;
4827
4828 switch (model) {
4829 case INTEL_FAM6_BROADWELL_X:
4830 case INTEL_FAM6_SKYLAKE_X:
4831 has_automatic_cstate_conversion = 1;
4832 }
4833 }
4834
prewake_cstate_probe(unsigned int family,unsigned int model)4835 void prewake_cstate_probe(unsigned int family, unsigned int model)
4836 {
4837 if (is_icx(family, model) || is_spr(family, model))
4838 dis_cstate_prewake = 1;
4839 }
4840
print_thermal(struct thread_data * t,struct core_data * c,struct pkg_data * p)4841 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4842 {
4843 unsigned long long msr;
4844 unsigned int dts, dts2;
4845 int cpu;
4846
4847 UNUSED(c);
4848 UNUSED(p);
4849
4850 if (!(do_dts || do_ptm))
4851 return 0;
4852
4853 cpu = t->cpu_id;
4854
4855 /* DTS is per-core, no need to print for each thread */
4856 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
4857 return 0;
4858
4859 if (cpu_migrate(cpu)) {
4860 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu);
4861 return -1;
4862 }
4863
4864 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
4865 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
4866 return 0;
4867
4868 dts = (msr >> 16) & 0x7F;
4869 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", cpu, msr, tj_max - dts);
4870
4871 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
4872 return 0;
4873
4874 dts = (msr >> 16) & 0x7F;
4875 dts2 = (msr >> 8) & 0x7F;
4876 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
4877 cpu, msr, tj_max - dts, tj_max - dts2);
4878 }
4879
4880 if (do_dts && debug) {
4881 unsigned int resolution;
4882
4883 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
4884 return 0;
4885
4886 dts = (msr >> 16) & 0x7F;
4887 resolution = (msr >> 27) & 0xF;
4888 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
4889 cpu, msr, tj_max - dts, resolution);
4890
4891 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
4892 return 0;
4893
4894 dts = (msr >> 16) & 0x7F;
4895 dts2 = (msr >> 8) & 0x7F;
4896 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
4897 cpu, msr, tj_max - dts, tj_max - dts2);
4898 }
4899
4900 return 0;
4901 }
4902
print_power_limit_msr(int cpu,unsigned long long msr,char * label)4903 void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
4904 {
4905 fprintf(outf, "cpu%d: %s: %sabled (%0.3f Watts, %f sec, clamp %sabled)\n",
4906 cpu, label,
4907 ((msr >> 15) & 1) ? "EN" : "DIS",
4908 ((msr >> 0) & 0x7FFF) * rapl_power_units,
4909 (1.0 + (((msr >> 22) & 0x3) / 4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
4910 (((msr >> 16) & 1) ? "EN" : "DIS"));
4911
4912 return;
4913 }
4914
print_rapl(struct thread_data * t,struct core_data * c,struct pkg_data * p)4915 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4916 {
4917 unsigned long long msr;
4918 const char *msr_name;
4919 int cpu;
4920
4921 UNUSED(c);
4922 UNUSED(p);
4923
4924 if (!do_rapl)
4925 return 0;
4926
4927 /* RAPL counters are per package, so print only for 1st thread/package */
4928 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4929 return 0;
4930
4931 cpu = t->cpu_id;
4932 if (cpu_migrate(cpu)) {
4933 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu);
4934 return -1;
4935 }
4936
4937 if (do_rapl & RAPL_AMD_F17H) {
4938 msr_name = "MSR_RAPL_PWR_UNIT";
4939 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr))
4940 return -1;
4941 } else {
4942 msr_name = "MSR_RAPL_POWER_UNIT";
4943 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
4944 return -1;
4945 }
4946
4947 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr,
4948 rapl_power_units, rapl_energy_units, rapl_time_units);
4949
4950 if (do_rapl & RAPL_PKG_POWER_INFO) {
4951
4952 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
4953 return -5;
4954
4955 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
4956 cpu, msr,
4957 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4958 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4959 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4960 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
4961
4962 }
4963 if (do_rapl & RAPL_PKG) {
4964
4965 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
4966 return -9;
4967
4968 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
4969 cpu, msr, (msr >> 63) & 1 ? "" : "UN");
4970
4971 print_power_limit_msr(cpu, msr, "PKG Limit #1");
4972 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%0.3f Watts, %f* sec, clamp %sabled)\n",
4973 cpu,
4974 ((msr >> 47) & 1) ? "EN" : "DIS",
4975 ((msr >> 32) & 0x7FFF) * rapl_power_units,
4976 (1.0 + (((msr >> 54) & 0x3) / 4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
4977 ((msr >> 48) & 1) ? "EN" : "DIS");
4978
4979 if (get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr))
4980 return -9;
4981
4982 fprintf(outf, "cpu%d: MSR_VR_CURRENT_CONFIG: 0x%08llx\n", cpu, msr);
4983 fprintf(outf, "cpu%d: PKG Limit #4: %f Watts (%slocked)\n",
4984 cpu, ((msr >> 0) & 0x1FFF) * rapl_power_units, (msr >> 31) & 1 ? "" : "UN");
4985 }
4986
4987 if (do_rapl & RAPL_DRAM_POWER_INFO) {
4988 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
4989 return -6;
4990
4991 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
4992 cpu, msr,
4993 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4994 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4995 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4996 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
4997 }
4998 if (do_rapl & RAPL_DRAM) {
4999 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
5000 return -9;
5001 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
5002 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
5003
5004 print_power_limit_msr(cpu, msr, "DRAM Limit");
5005 }
5006 if (do_rapl & RAPL_CORE_POLICY) {
5007 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
5008 return -7;
5009
5010 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
5011 }
5012 if (do_rapl & RAPL_CORES_POWER_LIMIT) {
5013 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
5014 return -9;
5015 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
5016 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
5017 print_power_limit_msr(cpu, msr, "Cores Limit");
5018 }
5019 if (do_rapl & RAPL_GFX) {
5020 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
5021 return -8;
5022
5023 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
5024
5025 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
5026 return -9;
5027 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
5028 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
5029 print_power_limit_msr(cpu, msr, "GFX Limit");
5030 }
5031 return 0;
5032 }
5033
5034 /*
5035 * SNB adds support for additional MSRs:
5036 *
5037 * MSR_PKG_C7_RESIDENCY 0x000003fa
5038 * MSR_CORE_C7_RESIDENCY 0x000003fe
5039 * MSR_PKG_C2_RESIDENCY 0x0000060d
5040 */
5041
has_snb_msrs(unsigned int family,unsigned int model)5042 int has_snb_msrs(unsigned int family, unsigned int model)
5043 {
5044 if (!genuine_intel)
5045 return 0;
5046
5047 if (family != 6)
5048 return 0;
5049
5050 switch (model) {
5051 case INTEL_FAM6_SANDYBRIDGE:
5052 case INTEL_FAM6_SANDYBRIDGE_X:
5053 case INTEL_FAM6_IVYBRIDGE: /* IVB */
5054 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
5055 case INTEL_FAM6_HASWELL: /* HSW */
5056 case INTEL_FAM6_HASWELL_X: /* HSW */
5057 case INTEL_FAM6_HASWELL_L: /* HSW */
5058 case INTEL_FAM6_HASWELL_G: /* HSW */
5059 case INTEL_FAM6_BROADWELL: /* BDW */
5060 case INTEL_FAM6_BROADWELL_G: /* BDW */
5061 case INTEL_FAM6_BROADWELL_X: /* BDX */
5062 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5063 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
5064 case INTEL_FAM6_SKYLAKE_X: /* SKX */
5065 case INTEL_FAM6_ICELAKE_X: /* ICX */
5066 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
5067 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
5068 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5069 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
5070 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
5071 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
5072 return 1;
5073 }
5074 return 0;
5075 }
5076
5077 /*
5078 * HSW ULT added support for C8/C9/C10 MSRs:
5079 *
5080 * MSR_PKG_C8_RESIDENCY 0x00000630
5081 * MSR_PKG_C9_RESIDENCY 0x00000631
5082 * MSR_PKG_C10_RESIDENCY 0x00000632
5083 *
5084 * MSR_PKGC8_IRTL 0x00000633
5085 * MSR_PKGC9_IRTL 0x00000634
5086 * MSR_PKGC10_IRTL 0x00000635
5087 *
5088 */
has_c8910_msrs(unsigned int family,unsigned int model)5089 int has_c8910_msrs(unsigned int family, unsigned int model)
5090 {
5091 if (!genuine_intel)
5092 return 0;
5093
5094 if (family != 6)
5095 return 0;
5096
5097 switch (model) {
5098 case INTEL_FAM6_HASWELL_L: /* HSW */
5099 case INTEL_FAM6_BROADWELL: /* BDW */
5100 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5101 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
5102 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
5103 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5104 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
5105 return 1;
5106 }
5107 return 0;
5108 }
5109
5110 /*
5111 * SKL adds support for additional MSRS:
5112 *
5113 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
5114 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
5115 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
5116 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
5117 */
has_skl_msrs(unsigned int family,unsigned int model)5118 int has_skl_msrs(unsigned int family, unsigned int model)
5119 {
5120 if (!genuine_intel)
5121 return 0;
5122
5123 if (family != 6)
5124 return 0;
5125
5126 switch (model) {
5127 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5128 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
5129 return 1;
5130 }
5131 return 0;
5132 }
5133
is_slm(unsigned int family,unsigned int model)5134 int is_slm(unsigned int family, unsigned int model)
5135 {
5136 if (!genuine_intel)
5137 return 0;
5138
5139 if (family != 6)
5140 return 0;
5141
5142 switch (model) {
5143 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
5144 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
5145 return 1;
5146 }
5147 return 0;
5148 }
5149
is_knl(unsigned int family,unsigned int model)5150 int is_knl(unsigned int family, unsigned int model)
5151 {
5152 if (!genuine_intel)
5153 return 0;
5154
5155 if (family != 6)
5156 return 0;
5157
5158 switch (model) {
5159 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
5160 return 1;
5161 }
5162 return 0;
5163 }
5164
is_cnl(unsigned int family,unsigned int model)5165 int is_cnl(unsigned int family, unsigned int model)
5166 {
5167 if (!genuine_intel)
5168 return 0;
5169
5170 if (family != 6)
5171 return 0;
5172
5173 switch (model) {
5174 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
5175 return 1;
5176 }
5177
5178 return 0;
5179 }
5180
get_aperf_mperf_multiplier(unsigned int family,unsigned int model)5181 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
5182 {
5183 if (is_knl(family, model))
5184 return 1024;
5185 return 1;
5186 }
5187
5188 #define SLM_BCLK_FREQS 5
5189 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0 };
5190
slm_bclk(void)5191 double slm_bclk(void)
5192 {
5193 unsigned long long msr = 3;
5194 unsigned int i;
5195 double freq;
5196
5197 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
5198 fprintf(outf, "SLM BCLK: unknown\n");
5199
5200 i = msr & 0xf;
5201 if (i >= SLM_BCLK_FREQS) {
5202 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
5203 i = 3;
5204 }
5205 freq = slm_freq_table[i];
5206
5207 if (!quiet)
5208 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
5209
5210 return freq;
5211 }
5212
discover_bclk(unsigned int family,unsigned int model)5213 double discover_bclk(unsigned int family, unsigned int model)
5214 {
5215 if (has_snb_msrs(family, model) || is_knl(family, model))
5216 return 100.00;
5217 else if (is_slm(family, model))
5218 return slm_bclk();
5219 else
5220 return 133.33;
5221 }
5222
get_cpu_type(struct thread_data * t,struct core_data * c,struct pkg_data * p)5223 int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5224 {
5225 unsigned int eax, ebx, ecx, edx;
5226
5227 UNUSED(c);
5228 UNUSED(p);
5229
5230 if (!genuine_intel)
5231 return 0;
5232
5233 if (cpu_migrate(t->cpu_id)) {
5234 fprintf(outf, "Could not migrate to CPU %d\n", t->cpu_id);
5235 return -1;
5236 }
5237
5238 if (max_level < 0x1a)
5239 return 0;
5240
5241 __cpuid(0x1a, eax, ebx, ecx, edx);
5242 eax = (eax >> 24) & 0xFF;
5243 if (eax == 0x20)
5244 t->is_atom = true;
5245 return 0;
5246 }
5247
5248 /*
5249 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
5250 * the Thermal Control Circuit (TCC) activates.
5251 * This is usually equal to tjMax.
5252 *
5253 * Older processors do not have this MSR, so there we guess,
5254 * but also allow cmdline over-ride with -T.
5255 *
5256 * Several MSR temperature values are in units of degrees-C
5257 * below this value, including the Digital Thermal Sensor (DTS),
5258 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
5259 */
set_temperature_target(struct thread_data * t,struct core_data * c,struct pkg_data * p)5260 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5261 {
5262 unsigned long long msr;
5263 unsigned int tcc_default, tcc_offset;
5264 int cpu;
5265
5266 UNUSED(c);
5267 UNUSED(p);
5268
5269 /* tj_max is used only for dts or ptm */
5270 if (!(do_dts || do_ptm))
5271 return 0;
5272
5273 /* this is a per-package concept */
5274 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
5275 return 0;
5276
5277 cpu = t->cpu_id;
5278 if (cpu_migrate(cpu)) {
5279 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
5280 return -1;
5281 }
5282
5283 if (tj_max_override != 0) {
5284 tj_max = tj_max_override;
5285 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", cpu, tj_max);
5286 return 0;
5287 }
5288
5289 /* Temperature Target MSR is Nehalem and newer only */
5290 if (!do_nhm_platform_info)
5291 goto guess;
5292
5293 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
5294 goto guess;
5295
5296 tcc_default = (msr >> 16) & 0xFF;
5297
5298 if (!quiet) {
5299 switch (tcc_offset_bits) {
5300 case 4:
5301 tcc_offset = (msr >> 24) & 0xF;
5302 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
5303 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
5304 break;
5305 case 6:
5306 tcc_offset = (msr >> 24) & 0x3F;
5307 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
5308 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
5309 break;
5310 default:
5311 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", cpu, msr, tcc_default);
5312 break;
5313 }
5314 }
5315
5316 if (!tcc_default)
5317 goto guess;
5318
5319 tj_max = tcc_default;
5320
5321 return 0;
5322
5323 guess:
5324 tj_max = TJMAX_DEFAULT;
5325 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", cpu, tj_max);
5326
5327 return 0;
5328 }
5329
decode_feature_control_msr(void)5330 void decode_feature_control_msr(void)
5331 {
5332 unsigned long long msr;
5333
5334 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr))
5335 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
5336 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : "");
5337 }
5338
decode_misc_enable_msr(void)5339 void decode_misc_enable_msr(void)
5340 {
5341 unsigned long long msr;
5342
5343 if (!genuine_intel)
5344 return;
5345
5346 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
5347 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
5348 base_cpu, msr,
5349 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",
5350 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",
5351 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-",
5352 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",
5353 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");
5354 }
5355
decode_misc_feature_control(void)5356 void decode_misc_feature_control(void)
5357 {
5358 unsigned long long msr;
5359
5360 if (!has_misc_feature_control)
5361 return;
5362
5363 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr))
5364 fprintf(outf,
5365 "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n",
5366 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "",
5367 msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : "");
5368 }
5369
5370 /*
5371 * Decode MSR_MISC_PWR_MGMT
5372 *
5373 * Decode the bits according to the Nehalem documentation
5374 * bit[0] seems to continue to have same meaning going forward
5375 * bit[1] less so...
5376 */
decode_misc_pwr_mgmt_msr(void)5377 void decode_misc_pwr_mgmt_msr(void)
5378 {
5379 unsigned long long msr;
5380
5381 if (!do_nhm_platform_info)
5382 return;
5383
5384 if (no_MSR_MISC_PWR_MGMT)
5385 return;
5386
5387 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
5388 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
5389 base_cpu, msr,
5390 msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS");
5391 }
5392
5393 /*
5394 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
5395 *
5396 * This MSRs are present on Silvermont processors,
5397 * Intel Atom processor E3000 series (Baytrail), and friends.
5398 */
decode_c6_demotion_policy_msr(void)5399 void decode_c6_demotion_policy_msr(void)
5400 {
5401 unsigned long long msr;
5402
5403 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
5404 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
5405 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5406
5407 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
5408 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
5409 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5410 }
5411
5412 /*
5413 * When models are the same, for the purpose of turbostat, reuse
5414 */
intel_model_duplicates(unsigned int model)5415 unsigned int intel_model_duplicates(unsigned int model)
5416 {
5417
5418 switch (model) {
5419 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
5420 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
5421 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
5422 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
5423 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
5424 return INTEL_FAM6_NEHALEM;
5425
5426 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
5427 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
5428 return INTEL_FAM6_NEHALEM_EX;
5429
5430 case INTEL_FAM6_XEON_PHI_KNM:
5431 return INTEL_FAM6_XEON_PHI_KNL;
5432
5433 case INTEL_FAM6_BROADWELL_X:
5434 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */
5435 return INTEL_FAM6_BROADWELL_X;
5436
5437 case INTEL_FAM6_SKYLAKE_L:
5438 case INTEL_FAM6_SKYLAKE:
5439 case INTEL_FAM6_KABYLAKE_L:
5440 case INTEL_FAM6_KABYLAKE:
5441 case INTEL_FAM6_COMETLAKE_L:
5442 case INTEL_FAM6_COMETLAKE:
5443 return INTEL_FAM6_SKYLAKE_L;
5444
5445 case INTEL_FAM6_ICELAKE_L:
5446 case INTEL_FAM6_ICELAKE_NNPI:
5447 case INTEL_FAM6_TIGERLAKE_L:
5448 case INTEL_FAM6_TIGERLAKE:
5449 case INTEL_FAM6_ROCKETLAKE:
5450 case INTEL_FAM6_LAKEFIELD:
5451 case INTEL_FAM6_ALDERLAKE:
5452 case INTEL_FAM6_ALDERLAKE_L:
5453 case INTEL_FAM6_ATOM_GRACEMONT:
5454 case INTEL_FAM6_RAPTORLAKE:
5455 case INTEL_FAM6_RAPTORLAKE_P:
5456 case INTEL_FAM6_RAPTORLAKE_S:
5457 case INTEL_FAM6_METEORLAKE:
5458 case INTEL_FAM6_METEORLAKE_L:
5459 return INTEL_FAM6_CANNONLAKE_L;
5460
5461 case INTEL_FAM6_ATOM_TREMONT_L:
5462 return INTEL_FAM6_ATOM_TREMONT;
5463
5464 case INTEL_FAM6_ICELAKE_D:
5465 return INTEL_FAM6_ICELAKE_X;
5466
5467 case INTEL_FAM6_EMERALDRAPIDS_X:
5468 return INTEL_FAM6_SAPPHIRERAPIDS_X;
5469 }
5470 return model;
5471 }
5472
print_dev_latency(void)5473 void print_dev_latency(void)
5474 {
5475 char *path = "/dev/cpu_dma_latency";
5476 int fd;
5477 int value;
5478 int retval;
5479
5480 fd = open(path, O_RDONLY);
5481 if (fd < 0) {
5482 if (debug)
5483 warnx("Read %s failed", path);
5484 return;
5485 }
5486
5487 retval = read(fd, (void *)&value, sizeof(int));
5488 if (retval != sizeof(int)) {
5489 warn("read failed %s", path);
5490 close(fd);
5491 return;
5492 }
5493 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", value, value == 2000000000 ? "default" : "constrained");
5494
5495 close(fd);
5496 }
5497
5498 /*
5499 * Linux-perf manages the HW instructions-retired counter
5500 * by enabling when requested, and hiding rollover
5501 */
linux_perf_init(void)5502 void linux_perf_init(void)
5503 {
5504 if (!BIC_IS_ENABLED(BIC_IPC))
5505 return;
5506
5507 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK))
5508 return;
5509
5510 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
5511 if (fd_instr_count_percpu == NULL)
5512 err(-1, "calloc fd_instr_count_percpu");
5513
5514 BIC_PRESENT(BIC_IPC);
5515 }
5516
process_cpuid()5517 void process_cpuid()
5518 {
5519 unsigned int eax, ebx, ecx, edx;
5520 unsigned int fms, family, model, stepping, ecx_flags, edx_flags;
5521 unsigned long long ucode_patch = 0;
5522 bool ucode_patch_valid = false;
5523
5524 eax = ebx = ecx = edx = 0;
5525
5526 __cpuid(0, max_level, ebx, ecx, edx);
5527
5528 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
5529 genuine_intel = 1;
5530 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
5531 authentic_amd = 1;
5532 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e)
5533 hygon_genuine = 1;
5534
5535 if (!quiet)
5536 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n",
5537 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level);
5538
5539 __cpuid(1, fms, ebx, ecx, edx);
5540 family = (fms >> 8) & 0xf;
5541 model = (fms >> 4) & 0xf;
5542 stepping = fms & 0xf;
5543 if (family == 0xf)
5544 family += (fms >> 20) & 0xff;
5545 if (family >= 6)
5546 model += ((fms >> 16) & 0xf) << 4;
5547 ecx_flags = ecx;
5548 edx_flags = edx;
5549
5550 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch))
5551 warnx("get_msr(UCODE)");
5552 else
5553 ucode_patch_valid = true;
5554
5555 /*
5556 * check max extended function levels of CPUID.
5557 * This is needed to check for invariant TSC.
5558 * This check is valid for both Intel and AMD.
5559 */
5560 ebx = ecx = edx = 0;
5561 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
5562
5563 if (!quiet) {
5564 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d)",
5565 family, model, stepping, family, model, stepping);
5566 if (ucode_patch_valid)
5567 fprintf(outf, " microcode 0x%x", (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF));
5568 fputc('\n', outf);
5569
5570 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level);
5571 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n",
5572 ecx_flags & (1 << 0) ? "SSE3" : "-",
5573 ecx_flags & (1 << 3) ? "MONITOR" : "-",
5574 ecx_flags & (1 << 6) ? "SMX" : "-",
5575 ecx_flags & (1 << 7) ? "EIST" : "-",
5576 ecx_flags & (1 << 8) ? "TM2" : "-",
5577 edx_flags & (1 << 4) ? "TSC" : "-",
5578 edx_flags & (1 << 5) ? "MSR" : "-",
5579 edx_flags & (1 << 22) ? "ACPI-TM" : "-",
5580 edx_flags & (1 << 28) ? "HT" : "-", edx_flags & (1 << 29) ? "TM" : "-");
5581 }
5582 if (genuine_intel) {
5583 model_orig = model;
5584 model = intel_model_duplicates(model);
5585 }
5586
5587 if (!(edx_flags & (1 << 5)))
5588 errx(1, "CPUID: no MSR");
5589
5590 if (max_extended_level >= 0x80000007) {
5591
5592 /*
5593 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
5594 * this check is valid for both Intel and AMD
5595 */
5596 __cpuid(0x80000007, eax, ebx, ecx, edx);
5597 has_invariant_tsc = edx & (1 << 8);
5598 }
5599
5600 /*
5601 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
5602 * this check is valid for both Intel and AMD
5603 */
5604
5605 __cpuid(0x6, eax, ebx, ecx, edx);
5606 has_aperf = ecx & (1 << 0);
5607 if (has_aperf) {
5608 BIC_PRESENT(BIC_Avg_MHz);
5609 BIC_PRESENT(BIC_Busy);
5610 BIC_PRESENT(BIC_Bzy_MHz);
5611 }
5612 do_dts = eax & (1 << 0);
5613 if (do_dts)
5614 BIC_PRESENT(BIC_CoreTmp);
5615 has_turbo = eax & (1 << 1);
5616 do_ptm = eax & (1 << 6);
5617 if (do_ptm)
5618 BIC_PRESENT(BIC_PkgTmp);
5619 has_hwp = eax & (1 << 7);
5620 has_hwp_notify = eax & (1 << 8);
5621 has_hwp_activity_window = eax & (1 << 9);
5622 has_hwp_epp = eax & (1 << 10);
5623 has_hwp_pkg = eax & (1 << 11);
5624 has_epb = ecx & (1 << 3);
5625
5626 if (!quiet)
5627 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, "
5628 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
5629 has_aperf ? "" : "No-",
5630 has_turbo ? "" : "No-",
5631 do_dts ? "" : "No-",
5632 do_ptm ? "" : "No-",
5633 has_hwp ? "" : "No-",
5634 has_hwp_notify ? "" : "No-",
5635 has_hwp_activity_window ? "" : "No-",
5636 has_hwp_epp ? "" : "No-", has_hwp_pkg ? "" : "No-", has_epb ? "" : "No-");
5637
5638 if (!quiet)
5639 decode_misc_enable_msr();
5640
5641 if (max_level >= 0x7 && !quiet) {
5642 int has_sgx;
5643
5644 ecx = 0;
5645
5646 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
5647
5648 has_sgx = ebx & (1 << 2);
5649
5650 is_hybrid = edx & (1 << 15);
5651
5652 fprintf(outf, "CPUID(7): %sSGX %sHybrid\n", has_sgx ? "" : "No-", is_hybrid ? "" : "No-");
5653
5654 if (has_sgx)
5655 decode_feature_control_msr();
5656 }
5657
5658 if (max_level >= 0x15) {
5659 unsigned int eax_crystal;
5660 unsigned int ebx_tsc;
5661
5662 /*
5663 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
5664 */
5665 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
5666 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
5667
5668 if (ebx_tsc != 0) {
5669
5670 if (!quiet && (ebx != 0))
5671 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
5672 eax_crystal, ebx_tsc, crystal_hz);
5673
5674 if (crystal_hz == 0)
5675 switch (model) {
5676 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5677 crystal_hz = 24000000; /* 24.0 MHz */
5678 break;
5679 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
5680 crystal_hz = 25000000; /* 25.0 MHz */
5681 break;
5682 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
5683 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5684 crystal_hz = 19200000; /* 19.2 MHz */
5685 break;
5686 default:
5687 crystal_hz = 0;
5688 }
5689
5690 if (crystal_hz) {
5691 tsc_hz = (unsigned long long)crystal_hz *ebx_tsc / eax_crystal;
5692 if (!quiet)
5693 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
5694 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
5695 }
5696 }
5697 }
5698 if (max_level >= 0x16) {
5699 unsigned int base_mhz, max_mhz, bus_mhz, edx;
5700
5701 /*
5702 * CPUID 16H Base MHz, Max MHz, Bus MHz
5703 */
5704 base_mhz = max_mhz = bus_mhz = edx = 0;
5705
5706 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
5707 if (!quiet)
5708 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
5709 base_mhz, max_mhz, bus_mhz);
5710 }
5711
5712 if (has_aperf)
5713 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
5714
5715 BIC_PRESENT(BIC_IRQ);
5716 BIC_PRESENT(BIC_TSC_MHz);
5717
5718 if (probe_nhm_msrs(family, model)) {
5719 do_nhm_platform_info = 1;
5720 BIC_PRESENT(BIC_CPU_c1);
5721 BIC_PRESENT(BIC_CPU_c3);
5722 BIC_PRESENT(BIC_CPU_c6);
5723 BIC_PRESENT(BIC_SMI);
5724 }
5725 do_snb_cstates = has_snb_msrs(family, model);
5726
5727 if (do_snb_cstates)
5728 BIC_PRESENT(BIC_CPU_c7);
5729
5730 do_irtl_snb = has_snb_msrs(family, model);
5731 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2))
5732 BIC_PRESENT(BIC_Pkgpc2);
5733 if (pkg_cstate_limit >= PCL__3)
5734 BIC_PRESENT(BIC_Pkgpc3);
5735 if (pkg_cstate_limit >= PCL__6)
5736 BIC_PRESENT(BIC_Pkgpc6);
5737 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7))
5738 BIC_PRESENT(BIC_Pkgpc7);
5739 if (has_slv_msrs(family, model)) {
5740 BIC_NOT_PRESENT(BIC_Pkgpc2);
5741 BIC_NOT_PRESENT(BIC_Pkgpc3);
5742 BIC_PRESENT(BIC_Pkgpc6);
5743 BIC_NOT_PRESENT(BIC_Pkgpc7);
5744 BIC_PRESENT(BIC_Mod_c6);
5745 use_c1_residency_msr = 1;
5746 }
5747 if (is_jvl(family, model)) {
5748 BIC_NOT_PRESENT(BIC_CPU_c3);
5749 BIC_NOT_PRESENT(BIC_CPU_c7);
5750 BIC_NOT_PRESENT(BIC_Pkgpc2);
5751 BIC_NOT_PRESENT(BIC_Pkgpc3);
5752 BIC_NOT_PRESENT(BIC_Pkgpc6);
5753 BIC_NOT_PRESENT(BIC_Pkgpc7);
5754 }
5755 if (is_dnv(family, model)) {
5756 BIC_PRESENT(BIC_CPU_c1);
5757 BIC_NOT_PRESENT(BIC_CPU_c3);
5758 BIC_NOT_PRESENT(BIC_Pkgpc3);
5759 BIC_NOT_PRESENT(BIC_CPU_c7);
5760 BIC_NOT_PRESENT(BIC_Pkgpc7);
5761 use_c1_residency_msr = 1;
5762 }
5763 if (is_skx(family, model) || is_icx(family, model) || is_spr(family, model)) {
5764 BIC_NOT_PRESENT(BIC_CPU_c3);
5765 BIC_NOT_PRESENT(BIC_Pkgpc3);
5766 BIC_NOT_PRESENT(BIC_CPU_c7);
5767 BIC_NOT_PRESENT(BIC_Pkgpc7);
5768 }
5769 if (is_bdx(family, model)) {
5770 BIC_NOT_PRESENT(BIC_CPU_c7);
5771 BIC_NOT_PRESENT(BIC_Pkgpc7);
5772 }
5773 if (has_c8910_msrs(family, model)) {
5774 if (pkg_cstate_limit >= PCL__8)
5775 BIC_PRESENT(BIC_Pkgpc8);
5776 if (pkg_cstate_limit >= PCL__9)
5777 BIC_PRESENT(BIC_Pkgpc9);
5778 if (pkg_cstate_limit >= PCL_10)
5779 BIC_PRESENT(BIC_Pkgpc10);
5780 }
5781 do_irtl_hsw = has_c8910_msrs(family, model);
5782 if (has_skl_msrs(family, model)) {
5783 BIC_PRESENT(BIC_Totl_c0);
5784 BIC_PRESENT(BIC_Any_c0);
5785 BIC_PRESENT(BIC_GFX_c0);
5786 BIC_PRESENT(BIC_CPUGFX);
5787 }
5788 do_slm_cstates = is_slm(family, model);
5789 do_knl_cstates = is_knl(family, model);
5790
5791 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || is_ehl(family, model))
5792 BIC_NOT_PRESENT(BIC_CPU_c3);
5793
5794 if (!quiet)
5795 decode_misc_pwr_mgmt_msr();
5796
5797 if (!quiet && has_slv_msrs(family, model))
5798 decode_c6_demotion_policy_msr();
5799
5800 rapl_probe(family, model);
5801 perf_limit_reasons_probe(family, model);
5802 automatic_cstate_conversion_probe(family, model);
5803 prewake_cstate_probe(family, model);
5804
5805 check_tcc_offset(model_orig);
5806
5807 if (!quiet)
5808 dump_cstate_pstate_config_info(family, model);
5809 intel_uncore_frequency_probe();
5810
5811 if (!quiet)
5812 print_dev_latency();
5813 if (!quiet)
5814 dump_sysfs_cstate_config();
5815 if (!quiet)
5816 dump_sysfs_pstate_config();
5817
5818 if (has_skl_msrs(family, model) || is_ehl(family, model))
5819 calculate_tsc_tweak();
5820
5821 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
5822 BIC_PRESENT(BIC_GFX_rc6);
5823
5824 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
5825 BIC_PRESENT(BIC_GFXMHz);
5826
5827 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK))
5828 BIC_PRESENT(BIC_GFXACTMHz);
5829
5830 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK))
5831 BIC_PRESENT(BIC_CPU_LPI);
5832 else
5833 BIC_NOT_PRESENT(BIC_CPU_LPI);
5834
5835 if (!access("/sys/devices/system/cpu/cpu0/thermal_throttle/core_throttle_count", R_OK))
5836 BIC_PRESENT(BIC_CORE_THROT_CNT);
5837 else
5838 BIC_NOT_PRESENT(BIC_CORE_THROT_CNT);
5839
5840 if (!access(sys_lpi_file_sysfs, R_OK)) {
5841 sys_lpi_file = sys_lpi_file_sysfs;
5842 BIC_PRESENT(BIC_SYS_LPI);
5843 } else if (!access(sys_lpi_file_debugfs, R_OK)) {
5844 sys_lpi_file = sys_lpi_file_debugfs;
5845 BIC_PRESENT(BIC_SYS_LPI);
5846 } else {
5847 sys_lpi_file_sysfs = NULL;
5848 BIC_NOT_PRESENT(BIC_SYS_LPI);
5849 }
5850
5851 if (!quiet)
5852 decode_misc_feature_control();
5853
5854 return;
5855 }
5856
5857 /*
5858 * in /dev/cpu/ return success for names that are numbers
5859 * ie. filter out ".", "..", "microcode".
5860 */
dir_filter(const struct dirent * dirp)5861 int dir_filter(const struct dirent *dirp)
5862 {
5863 if (isdigit(dirp->d_name[0]))
5864 return 1;
5865 else
5866 return 0;
5867 }
5868
topology_probe()5869 void topology_probe()
5870 {
5871 int i;
5872 int max_core_id = 0;
5873 int max_package_id = 0;
5874 int max_die_id = 0;
5875 int max_siblings = 0;
5876
5877 /* Initialize num_cpus, max_cpu_num */
5878 set_max_cpu_num();
5879 topo.num_cpus = 0;
5880 for_all_proc_cpus(count_cpus);
5881 if (!summary_only && topo.num_cpus > 1)
5882 BIC_PRESENT(BIC_CPU);
5883
5884 if (debug > 1)
5885 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
5886
5887 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
5888 if (cpus == NULL)
5889 err(1, "calloc cpus");
5890
5891 /*
5892 * Allocate and initialize cpu_present_set
5893 */
5894 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
5895 if (cpu_present_set == NULL)
5896 err(3, "CPU_ALLOC");
5897 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5898 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
5899 for_all_proc_cpus(mark_cpu_present);
5900
5901 /*
5902 * Validate that all cpus in cpu_subset are also in cpu_present_set
5903 */
5904 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) {
5905 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset))
5906 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set))
5907 err(1, "cpu%d not present", i);
5908 }
5909
5910 /*
5911 * Allocate and initialize cpu_affinity_set
5912 */
5913 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
5914 if (cpu_affinity_set == NULL)
5915 err(3, "CPU_ALLOC");
5916 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5917 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
5918
5919 for_all_proc_cpus(init_thread_id);
5920
5921 /*
5922 * For online cpus
5923 * find max_core_id, max_package_id
5924 */
5925 for (i = 0; i <= topo.max_cpu_num; ++i) {
5926 int siblings;
5927
5928 if (cpu_is_not_present(i)) {
5929 if (debug > 1)
5930 fprintf(outf, "cpu%d NOT PRESENT\n", i);
5931 continue;
5932 }
5933
5934 cpus[i].logical_cpu_id = i;
5935
5936 /* get package information */
5937 cpus[i].physical_package_id = get_physical_package_id(i);
5938 if (cpus[i].physical_package_id > max_package_id)
5939 max_package_id = cpus[i].physical_package_id;
5940
5941 /* get die information */
5942 cpus[i].die_id = get_die_id(i);
5943 if (cpus[i].die_id > max_die_id)
5944 max_die_id = cpus[i].die_id;
5945
5946 /* get numa node information */
5947 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]);
5948 if (cpus[i].physical_node_id > topo.max_node_num)
5949 topo.max_node_num = cpus[i].physical_node_id;
5950
5951 /* get core information */
5952 cpus[i].physical_core_id = get_core_id(i);
5953 if (cpus[i].physical_core_id > max_core_id)
5954 max_core_id = cpus[i].physical_core_id;
5955
5956 /* get thread information */
5957 siblings = get_thread_siblings(&cpus[i]);
5958 if (siblings > max_siblings)
5959 max_siblings = siblings;
5960 if (cpus[i].thread_id == 0)
5961 topo.num_cores++;
5962 }
5963
5964 topo.cores_per_node = max_core_id + 1;
5965 if (debug > 1)
5966 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", max_core_id, topo.cores_per_node);
5967 if (!summary_only && topo.cores_per_node > 1)
5968 BIC_PRESENT(BIC_Core);
5969
5970 topo.num_die = max_die_id + 1;
5971 if (debug > 1)
5972 fprintf(outf, "max_die_id %d, sizing for %d die\n", max_die_id, topo.num_die);
5973 if (!summary_only && topo.num_die > 1)
5974 BIC_PRESENT(BIC_Die);
5975
5976 topo.num_packages = max_package_id + 1;
5977 if (debug > 1)
5978 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages);
5979 if (!summary_only && topo.num_packages > 1)
5980 BIC_PRESENT(BIC_Package);
5981
5982 set_node_data();
5983 if (debug > 1)
5984 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg);
5985 if (!summary_only && topo.nodes_per_pkg > 1)
5986 BIC_PRESENT(BIC_Node);
5987
5988 topo.threads_per_core = max_siblings;
5989 if (debug > 1)
5990 fprintf(outf, "max_siblings %d\n", max_siblings);
5991
5992 if (debug < 1)
5993 return;
5994
5995 for (i = 0; i <= topo.max_cpu_num; ++i) {
5996 if (cpu_is_not_present(i))
5997 continue;
5998 fprintf(outf,
5999 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n",
6000 i, cpus[i].physical_package_id, cpus[i].die_id,
6001 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id);
6002 }
6003
6004 }
6005
allocate_counters(struct thread_data ** t,struct core_data ** c,struct pkg_data ** p)6006 void allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
6007 {
6008 int i;
6009 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * topo.num_packages;
6010 int num_threads = topo.threads_per_core * num_cores;
6011
6012 *t = calloc(num_threads, sizeof(struct thread_data));
6013 if (*t == NULL)
6014 goto error;
6015
6016 for (i = 0; i < num_threads; i++)
6017 (*t)[i].cpu_id = -1;
6018
6019 *c = calloc(num_cores, sizeof(struct core_data));
6020 if (*c == NULL)
6021 goto error;
6022
6023 for (i = 0; i < num_cores; i++)
6024 (*c)[i].core_id = -1;
6025
6026 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
6027 if (*p == NULL)
6028 goto error;
6029
6030 for (i = 0; i < topo.num_packages; i++)
6031 (*p)[i].package_id = i;
6032
6033 return;
6034 error:
6035 err(1, "calloc counters");
6036 }
6037
6038 /*
6039 * init_counter()
6040 *
6041 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
6042 */
init_counter(struct thread_data * thread_base,struct core_data * core_base,struct pkg_data * pkg_base,int cpu_id)6043 void init_counter(struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base, int cpu_id)
6044 {
6045 int pkg_id = cpus[cpu_id].physical_package_id;
6046 int node_id = cpus[cpu_id].logical_node_id;
6047 int core_id = cpus[cpu_id].physical_core_id;
6048 int thread_id = cpus[cpu_id].thread_id;
6049 struct thread_data *t;
6050 struct core_data *c;
6051 struct pkg_data *p;
6052
6053 /* Workaround for systems where physical_node_id==-1
6054 * and logical_node_id==(-1 - topo.num_cpus)
6055 */
6056 if (node_id < 0)
6057 node_id = 0;
6058
6059 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id);
6060 c = GET_CORE(core_base, core_id, node_id, pkg_id);
6061 p = GET_PKG(pkg_base, pkg_id);
6062
6063 t->cpu_id = cpu_id;
6064 if (thread_id == 0) {
6065 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
6066 if (cpu_is_first_core_in_package(cpu_id))
6067 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
6068 }
6069
6070 c->core_id = core_id;
6071 p->package_id = pkg_id;
6072 }
6073
initialize_counters(int cpu_id)6074 int initialize_counters(int cpu_id)
6075 {
6076 init_counter(EVEN_COUNTERS, cpu_id);
6077 init_counter(ODD_COUNTERS, cpu_id);
6078 return 0;
6079 }
6080
allocate_output_buffer()6081 void allocate_output_buffer()
6082 {
6083 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048);
6084 outp = output_buffer;
6085 if (outp == NULL)
6086 err(-1, "calloc output buffer");
6087 }
6088
allocate_fd_percpu(void)6089 void allocate_fd_percpu(void)
6090 {
6091 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
6092 if (fd_percpu == NULL)
6093 err(-1, "calloc fd_percpu");
6094 }
6095
allocate_irq_buffers(void)6096 void allocate_irq_buffers(void)
6097 {
6098 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
6099 if (irq_column_2_cpu == NULL)
6100 err(-1, "calloc %d", topo.num_cpus);
6101
6102 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
6103 if (irqs_per_cpu == NULL)
6104 err(-1, "calloc %d", topo.max_cpu_num + 1);
6105 }
6106
setup_all_buffers(void)6107 void setup_all_buffers(void)
6108 {
6109 topology_probe();
6110 allocate_irq_buffers();
6111 allocate_fd_percpu();
6112 allocate_counters(&thread_even, &core_even, &package_even);
6113 allocate_counters(&thread_odd, &core_odd, &package_odd);
6114 allocate_output_buffer();
6115 for_all_proc_cpus(initialize_counters);
6116 }
6117
set_base_cpu(void)6118 void set_base_cpu(void)
6119 {
6120 base_cpu = sched_getcpu();
6121 if (base_cpu < 0)
6122 err(-ENODEV, "No valid cpus found");
6123
6124 if (debug > 1)
6125 fprintf(outf, "base_cpu = %d\n", base_cpu);
6126 }
6127
turbostat_init()6128 void turbostat_init()
6129 {
6130 setup_all_buffers();
6131 set_base_cpu();
6132 check_dev_msr();
6133 check_permissions();
6134 process_cpuid();
6135 linux_perf_init();
6136
6137 if (!quiet)
6138 for_all_cpus(print_hwp, ODD_COUNTERS);
6139
6140 if (!quiet)
6141 for_all_cpus(print_epb, ODD_COUNTERS);
6142
6143 if (!quiet)
6144 for_all_cpus(print_perf_limit, ODD_COUNTERS);
6145
6146 if (!quiet)
6147 for_all_cpus(print_rapl, ODD_COUNTERS);
6148
6149 for_all_cpus(set_temperature_target, ODD_COUNTERS);
6150
6151 for_all_cpus(get_cpu_type, ODD_COUNTERS);
6152 for_all_cpus(get_cpu_type, EVEN_COUNTERS);
6153
6154 if (!quiet)
6155 for_all_cpus(print_thermal, ODD_COUNTERS);
6156
6157 if (!quiet && do_irtl_snb)
6158 print_irtl();
6159
6160 if (DO_BIC(BIC_IPC))
6161 (void)get_instr_count_fd(base_cpu);
6162 }
6163
fork_it(char ** argv)6164 int fork_it(char **argv)
6165 {
6166 pid_t child_pid;
6167 int status;
6168
6169 snapshot_proc_sysfs_files();
6170 status = for_all_cpus(get_counters, EVEN_COUNTERS);
6171 first_counter_read = 0;
6172 if (status)
6173 exit(status);
6174 /* clear affinity side-effect of get_counters() */
6175 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
6176 gettimeofday(&tv_even, (struct timezone *)NULL);
6177
6178 child_pid = fork();
6179 if (!child_pid) {
6180 /* child */
6181 execvp(argv[0], argv);
6182 err(errno, "exec %s", argv[0]);
6183 } else {
6184
6185 /* parent */
6186 if (child_pid == -1)
6187 err(1, "fork");
6188
6189 signal(SIGINT, SIG_IGN);
6190 signal(SIGQUIT, SIG_IGN);
6191 if (waitpid(child_pid, &status, 0) == -1)
6192 err(status, "waitpid");
6193
6194 if (WIFEXITED(status))
6195 status = WEXITSTATUS(status);
6196 }
6197 /*
6198 * n.b. fork_it() does not check for errors from for_all_cpus()
6199 * because re-starting is problematic when forking
6200 */
6201 snapshot_proc_sysfs_files();
6202 for_all_cpus(get_counters, ODD_COUNTERS);
6203 gettimeofday(&tv_odd, (struct timezone *)NULL);
6204 timersub(&tv_odd, &tv_even, &tv_delta);
6205 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
6206 fprintf(outf, "%s: Counter reset detected\n", progname);
6207 else {
6208 compute_average(EVEN_COUNTERS);
6209 format_all_counters(EVEN_COUNTERS);
6210 }
6211
6212 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec / 1000000.0);
6213
6214 flush_output_stderr();
6215
6216 return status;
6217 }
6218
get_and_dump_counters(void)6219 int get_and_dump_counters(void)
6220 {
6221 int status;
6222
6223 snapshot_proc_sysfs_files();
6224 status = for_all_cpus(get_counters, ODD_COUNTERS);
6225 if (status)
6226 return status;
6227
6228 status = for_all_cpus(dump_counters, ODD_COUNTERS);
6229 if (status)
6230 return status;
6231
6232 flush_output_stdout();
6233
6234 return status;
6235 }
6236
print_version()6237 void print_version()
6238 {
6239 fprintf(outf, "turbostat version 2023.03.17 - Len Brown <lenb@kernel.org>\n");
6240 }
6241
6242 #define COMMAND_LINE_SIZE 2048
6243
print_bootcmd(void)6244 void print_bootcmd(void)
6245 {
6246 char bootcmd[COMMAND_LINE_SIZE];
6247 FILE *fp;
6248 int ret;
6249
6250 memset(bootcmd, 0, COMMAND_LINE_SIZE);
6251 fp = fopen("/proc/cmdline", "r");
6252 if (!fp)
6253 return;
6254
6255 ret = fread(bootcmd, sizeof(char), COMMAND_LINE_SIZE - 1, fp);
6256 if (ret) {
6257 bootcmd[ret] = '\0';
6258 /* the last character is already '\n' */
6259 fprintf(outf, "Kernel command line: %s", bootcmd);
6260 }
6261
6262 fclose(fp);
6263 }
6264
add_counter(unsigned int msr_num,char * path,char * name,unsigned int width,enum counter_scope scope,enum counter_type type,enum counter_format format,int flags)6265 int add_counter(unsigned int msr_num, char *path, char *name,
6266 unsigned int width, enum counter_scope scope,
6267 enum counter_type type, enum counter_format format, int flags)
6268 {
6269 struct msr_counter *msrp;
6270
6271 msrp = calloc(1, sizeof(struct msr_counter));
6272 if (msrp == NULL) {
6273 perror("calloc");
6274 exit(1);
6275 }
6276
6277 msrp->msr_num = msr_num;
6278 strncpy(msrp->name, name, NAME_BYTES - 1);
6279 if (path)
6280 strncpy(msrp->path, path, PATH_BYTES - 1);
6281 msrp->width = width;
6282 msrp->type = type;
6283 msrp->format = format;
6284 msrp->flags = flags;
6285
6286 switch (scope) {
6287
6288 case SCOPE_CPU:
6289 msrp->next = sys.tp;
6290 sys.tp = msrp;
6291 sys.added_thread_counters++;
6292 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) {
6293 fprintf(stderr, "exceeded max %d added thread counters\n", MAX_ADDED_COUNTERS);
6294 exit(-1);
6295 }
6296 break;
6297
6298 case SCOPE_CORE:
6299 msrp->next = sys.cp;
6300 sys.cp = msrp;
6301 sys.added_core_counters++;
6302 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
6303 fprintf(stderr, "exceeded max %d added core counters\n", MAX_ADDED_COUNTERS);
6304 exit(-1);
6305 }
6306 break;
6307
6308 case SCOPE_PACKAGE:
6309 msrp->next = sys.pp;
6310 sys.pp = msrp;
6311 sys.added_package_counters++;
6312 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
6313 fprintf(stderr, "exceeded max %d added package counters\n", MAX_ADDED_COUNTERS);
6314 exit(-1);
6315 }
6316 break;
6317 }
6318
6319 return 0;
6320 }
6321
parse_add_command(char * add_command)6322 void parse_add_command(char *add_command)
6323 {
6324 int msr_num = 0;
6325 char *path = NULL;
6326 char name_buffer[NAME_BYTES] = "";
6327 int width = 64;
6328 int fail = 0;
6329 enum counter_scope scope = SCOPE_CPU;
6330 enum counter_type type = COUNTER_CYCLES;
6331 enum counter_format format = FORMAT_DELTA;
6332
6333 while (add_command) {
6334
6335 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
6336 goto next;
6337
6338 if (sscanf(add_command, "msr%d", &msr_num) == 1)
6339 goto next;
6340
6341 if (*add_command == '/') {
6342 path = add_command;
6343 goto next;
6344 }
6345
6346 if (sscanf(add_command, "u%d", &width) == 1) {
6347 if ((width == 32) || (width == 64))
6348 goto next;
6349 width = 64;
6350 }
6351 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
6352 scope = SCOPE_CPU;
6353 goto next;
6354 }
6355 if (!strncmp(add_command, "core", strlen("core"))) {
6356 scope = SCOPE_CORE;
6357 goto next;
6358 }
6359 if (!strncmp(add_command, "package", strlen("package"))) {
6360 scope = SCOPE_PACKAGE;
6361 goto next;
6362 }
6363 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
6364 type = COUNTER_CYCLES;
6365 goto next;
6366 }
6367 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
6368 type = COUNTER_SECONDS;
6369 goto next;
6370 }
6371 if (!strncmp(add_command, "usec", strlen("usec"))) {
6372 type = COUNTER_USEC;
6373 goto next;
6374 }
6375 if (!strncmp(add_command, "raw", strlen("raw"))) {
6376 format = FORMAT_RAW;
6377 goto next;
6378 }
6379 if (!strncmp(add_command, "delta", strlen("delta"))) {
6380 format = FORMAT_DELTA;
6381 goto next;
6382 }
6383 if (!strncmp(add_command, "percent", strlen("percent"))) {
6384 format = FORMAT_PERCENT;
6385 goto next;
6386 }
6387
6388 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
6389 char *eos;
6390
6391 eos = strchr(name_buffer, ',');
6392 if (eos)
6393 *eos = '\0';
6394 goto next;
6395 }
6396
6397 next:
6398 add_command = strchr(add_command, ',');
6399 if (add_command) {
6400 *add_command = '\0';
6401 add_command++;
6402 }
6403
6404 }
6405 if ((msr_num == 0) && (path == NULL)) {
6406 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n");
6407 fail++;
6408 }
6409
6410 /* generate default column header */
6411 if (*name_buffer == '\0') {
6412 if (width == 32)
6413 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
6414 else
6415 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
6416 }
6417
6418 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0))
6419 fail++;
6420
6421 if (fail) {
6422 help();
6423 exit(1);
6424 }
6425 }
6426
is_deferred_add(char * name)6427 int is_deferred_add(char *name)
6428 {
6429 int i;
6430
6431 for (i = 0; i < deferred_add_index; ++i)
6432 if (!strcmp(name, deferred_add_names[i]))
6433 return 1;
6434 return 0;
6435 }
6436
is_deferred_skip(char * name)6437 int is_deferred_skip(char *name)
6438 {
6439 int i;
6440
6441 for (i = 0; i < deferred_skip_index; ++i)
6442 if (!strcmp(name, deferred_skip_names[i]))
6443 return 1;
6444 return 0;
6445 }
6446
probe_sysfs(void)6447 void probe_sysfs(void)
6448 {
6449 char path[64];
6450 char name_buf[16];
6451 FILE *input;
6452 int state;
6453 char *sp;
6454
6455 for (state = 10; state >= 0; --state) {
6456
6457 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
6458 input = fopen(path, "r");
6459 if (input == NULL)
6460 continue;
6461 if (!fgets(name_buf, sizeof(name_buf), input))
6462 err(1, "%s: failed to read file", path);
6463
6464 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
6465 sp = strchr(name_buf, '-');
6466 if (!sp)
6467 sp = strchrnul(name_buf, '\n');
6468 *sp = '%';
6469 *(sp + 1) = '\0';
6470
6471 remove_underbar(name_buf);
6472
6473 fclose(input);
6474
6475 sprintf(path, "cpuidle/state%d/time", state);
6476
6477 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf))
6478 continue;
6479
6480 if (is_deferred_skip(name_buf))
6481 continue;
6482
6483 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, FORMAT_PERCENT, SYSFS_PERCPU);
6484 }
6485
6486 for (state = 10; state >= 0; --state) {
6487
6488 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
6489 input = fopen(path, "r");
6490 if (input == NULL)
6491 continue;
6492 if (!fgets(name_buf, sizeof(name_buf), input))
6493 err(1, "%s: failed to read file", path);
6494 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
6495 sp = strchr(name_buf, '-');
6496 if (!sp)
6497 sp = strchrnul(name_buf, '\n');
6498 *sp = '\0';
6499 fclose(input);
6500
6501 remove_underbar(name_buf);
6502
6503 sprintf(path, "cpuidle/state%d/usage", state);
6504
6505 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf))
6506 continue;
6507
6508 if (is_deferred_skip(name_buf))
6509 continue;
6510
6511 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, FORMAT_DELTA, SYSFS_PERCPU);
6512 }
6513
6514 }
6515
6516 /*
6517 * parse cpuset with following syntax
6518 * 1,2,4..6,8-10 and set bits in cpu_subset
6519 */
parse_cpu_command(char * optarg)6520 void parse_cpu_command(char *optarg)
6521 {
6522 unsigned int start, end;
6523 char *next;
6524
6525 if (!strcmp(optarg, "core")) {
6526 if (cpu_subset)
6527 goto error;
6528 show_core_only++;
6529 return;
6530 }
6531 if (!strcmp(optarg, "package")) {
6532 if (cpu_subset)
6533 goto error;
6534 show_pkg_only++;
6535 return;
6536 }
6537 if (show_core_only || show_pkg_only)
6538 goto error;
6539
6540 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS);
6541 if (cpu_subset == NULL)
6542 err(3, "CPU_ALLOC");
6543 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS);
6544
6545 CPU_ZERO_S(cpu_subset_size, cpu_subset);
6546
6547 next = optarg;
6548
6549 while (next && *next) {
6550
6551 if (*next == '-') /* no negative cpu numbers */
6552 goto error;
6553
6554 start = strtoul(next, &next, 10);
6555
6556 if (start >= CPU_SUBSET_MAXCPUS)
6557 goto error;
6558 CPU_SET_S(start, cpu_subset_size, cpu_subset);
6559
6560 if (*next == '\0')
6561 break;
6562
6563 if (*next == ',') {
6564 next += 1;
6565 continue;
6566 }
6567
6568 if (*next == '-') {
6569 next += 1; /* start range */
6570 } else if (*next == '.') {
6571 next += 1;
6572 if (*next == '.')
6573 next += 1; /* start range */
6574 else
6575 goto error;
6576 }
6577
6578 end = strtoul(next, &next, 10);
6579 if (end <= start)
6580 goto error;
6581
6582 while (++start <= end) {
6583 if (start >= CPU_SUBSET_MAXCPUS)
6584 goto error;
6585 CPU_SET_S(start, cpu_subset_size, cpu_subset);
6586 }
6587
6588 if (*next == ',')
6589 next += 1;
6590 else if (*next != '\0')
6591 goto error;
6592 }
6593
6594 return;
6595
6596 error:
6597 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg);
6598 help();
6599 exit(-1);
6600 }
6601
cmdline(int argc,char ** argv)6602 void cmdline(int argc, char **argv)
6603 {
6604 int opt;
6605 int option_index = 0;
6606 static struct option long_options[] = {
6607 { "add", required_argument, 0, 'a' },
6608 { "cpu", required_argument, 0, 'c' },
6609 { "Dump", no_argument, 0, 'D' },
6610 { "debug", no_argument, 0, 'd' }, /* internal, not documented */
6611 { "enable", required_argument, 0, 'e' },
6612 { "interval", required_argument, 0, 'i' },
6613 { "IPC", no_argument, 0, 'I' },
6614 { "num_iterations", required_argument, 0, 'n' },
6615 { "header_iterations", required_argument, 0, 'N' },
6616 { "help", no_argument, 0, 'h' },
6617 { "hide", required_argument, 0, 'H' }, // meh, -h taken by --help
6618 { "Joules", no_argument, 0, 'J' },
6619 { "list", no_argument, 0, 'l' },
6620 { "out", required_argument, 0, 'o' },
6621 { "quiet", no_argument, 0, 'q' },
6622 { "show", required_argument, 0, 's' },
6623 { "Summary", no_argument, 0, 'S' },
6624 { "TCC", required_argument, 0, 'T' },
6625 { "version", no_argument, 0, 'v' },
6626 { 0, 0, 0, 0 }
6627 };
6628
6629 progname = argv[0];
6630
6631 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", long_options, &option_index)) != -1) {
6632 switch (opt) {
6633 case 'a':
6634 parse_add_command(optarg);
6635 break;
6636 case 'c':
6637 parse_cpu_command(optarg);
6638 break;
6639 case 'D':
6640 dump_only++;
6641 break;
6642 case 'e':
6643 /* --enable specified counter */
6644 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST);
6645 break;
6646 case 'd':
6647 debug++;
6648 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
6649 break;
6650 case 'H':
6651 /*
6652 * --hide: do not show those specified
6653 * multiple invocations simply clear more bits in enabled mask
6654 */
6655 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST);
6656 break;
6657 case 'h':
6658 default:
6659 help();
6660 exit(1);
6661 case 'i':
6662 {
6663 double interval = strtod(optarg, NULL);
6664
6665 if (interval < 0.001) {
6666 fprintf(outf, "interval %f seconds is too small\n", interval);
6667 exit(2);
6668 }
6669
6670 interval_tv.tv_sec = interval_ts.tv_sec = interval;
6671 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000;
6672 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
6673 }
6674 break;
6675 case 'J':
6676 rapl_joules++;
6677 break;
6678 case 'l':
6679 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
6680 list_header_only++;
6681 quiet++;
6682 break;
6683 case 'o':
6684 outf = fopen_or_die(optarg, "w");
6685 break;
6686 case 'q':
6687 quiet = 1;
6688 break;
6689 case 'n':
6690 num_iterations = strtod(optarg, NULL);
6691
6692 if (num_iterations <= 0) {
6693 fprintf(outf, "iterations %d should be positive number\n", num_iterations);
6694 exit(2);
6695 }
6696 break;
6697 case 'N':
6698 header_iterations = strtod(optarg, NULL);
6699
6700 if (header_iterations <= 0) {
6701 fprintf(outf, "iterations %d should be positive number\n", header_iterations);
6702 exit(2);
6703 }
6704 break;
6705 case 's':
6706 /*
6707 * --show: show only those specified
6708 * The 1st invocation will clear and replace the enabled mask
6709 * subsequent invocations can add to it.
6710 */
6711 if (shown == 0)
6712 bic_enabled = bic_lookup(optarg, SHOW_LIST);
6713 else
6714 bic_enabled |= bic_lookup(optarg, SHOW_LIST);
6715 shown = 1;
6716 break;
6717 case 'S':
6718 summary_only++;
6719 break;
6720 case 'T':
6721 tj_max_override = atoi(optarg);
6722 break;
6723 case 'v':
6724 print_version();
6725 exit(0);
6726 break;
6727 }
6728 }
6729 }
6730
set_rlimit(void)6731 void set_rlimit(void)
6732 {
6733 struct rlimit limit;
6734
6735 if (getrlimit(RLIMIT_NOFILE, &limit) < 0)
6736 err(1, "Failed to get rlimit");
6737
6738 if (limit.rlim_max < MAX_NOFILE)
6739 limit.rlim_max = MAX_NOFILE;
6740 if (limit.rlim_cur < MAX_NOFILE)
6741 limit.rlim_cur = MAX_NOFILE;
6742
6743 if (setrlimit(RLIMIT_NOFILE, &limit) < 0)
6744 err(1, "Failed to set rlimit");
6745 }
6746
main(int argc,char ** argv)6747 int main(int argc, char **argv)
6748 {
6749 outf = stderr;
6750 cmdline(argc, argv);
6751
6752 if (!quiet) {
6753 print_version();
6754 print_bootcmd();
6755 }
6756
6757 probe_sysfs();
6758
6759 if (!getuid())
6760 set_rlimit();
6761
6762 turbostat_init();
6763
6764 msr_sum_record();
6765
6766 /* dump counters and exit */
6767 if (dump_only)
6768 return get_and_dump_counters();
6769
6770 /* list header and exit */
6771 if (list_header_only) {
6772 print_header(",");
6773 flush_output_stdout();
6774 return 0;
6775 }
6776
6777 /*
6778 * if any params left, it must be a command to fork
6779 */
6780 if (argc - optind)
6781 return fork_it(argv + optind);
6782 else
6783 turbostat_loop();
6784
6785 return 0;
6786 }
6787