1 /* 2 * turbostat -- show CPU frequency and C-state residency 3 * on modern Intel turbo-capable processors. 4 * 5 * Copyright (c) 2013 Intel Corporation. 6 * Len Brown <len.brown@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #define _GNU_SOURCE 23 #include MSRHEADER 24 #include INTEL_FAMILY_HEADER 25 #include <stdarg.h> 26 #include <stdio.h> 27 #include <err.h> 28 #include <unistd.h> 29 #include <sys/types.h> 30 #include <sys/wait.h> 31 #include <sys/stat.h> 32 #include <sys/resource.h> 33 #include <fcntl.h> 34 #include <signal.h> 35 #include <sys/time.h> 36 #include <stdlib.h> 37 #include <getopt.h> 38 #include <dirent.h> 39 #include <string.h> 40 #include <ctype.h> 41 #include <sched.h> 42 #include <time.h> 43 #include <cpuid.h> 44 #include <linux/capability.h> 45 #include <errno.h> 46 47 char *proc_stat = "/proc/stat"; 48 FILE *outf; 49 int *fd_percpu; 50 struct timespec interval_ts = {5, 0}; 51 unsigned int debug; 52 unsigned int rapl_joules; 53 unsigned int summary_only; 54 unsigned int dump_only; 55 unsigned int do_snb_cstates; 56 unsigned int do_knl_cstates; 57 unsigned int do_pc2; 58 unsigned int do_pc3; 59 unsigned int do_pc6; 60 unsigned int do_pc7; 61 unsigned int do_c8_c9_c10; 62 unsigned int do_skl_residency; 63 unsigned int do_slm_cstates; 64 unsigned int use_c1_residency_msr; 65 unsigned int has_aperf; 66 unsigned int has_epb; 67 unsigned int do_irtl_snb; 68 unsigned int do_irtl_hsw; 69 unsigned int units = 1000000; /* MHz etc */ 70 unsigned int genuine_intel; 71 unsigned int has_invariant_tsc; 72 unsigned int do_nhm_platform_info; 73 unsigned int aperf_mperf_multiplier = 1; 74 double bclk; 75 double base_hz; 76 unsigned int has_base_hz; 77 double tsc_tweak = 1.0; 78 unsigned int show_pkg_only; 79 unsigned int show_core_only; 80 char *output_buffer, *outp; 81 unsigned int do_rapl; 82 unsigned int do_dts; 83 unsigned int do_ptm; 84 unsigned long long gfx_cur_rc6_ms; 85 unsigned int gfx_cur_mhz; 86 unsigned int tcc_activation_temp; 87 unsigned int tcc_activation_temp_override; 88 double rapl_power_units, rapl_time_units; 89 double rapl_dram_energy_units, rapl_energy_units; 90 double rapl_joule_counter_range; 91 unsigned int do_core_perf_limit_reasons; 92 unsigned int do_gfx_perf_limit_reasons; 93 unsigned int do_ring_perf_limit_reasons; 94 unsigned int crystal_hz; 95 unsigned long long tsc_hz; 96 int base_cpu; 97 double discover_bclk(unsigned int family, unsigned int model); 98 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 99 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 100 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 101 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 102 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 103 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 104 105 #define RAPL_PKG (1 << 0) 106 /* 0x610 MSR_PKG_POWER_LIMIT */ 107 /* 0x611 MSR_PKG_ENERGY_STATUS */ 108 #define RAPL_PKG_PERF_STATUS (1 << 1) 109 /* 0x613 MSR_PKG_PERF_STATUS */ 110 #define RAPL_PKG_POWER_INFO (1 << 2) 111 /* 0x614 MSR_PKG_POWER_INFO */ 112 113 #define RAPL_DRAM (1 << 3) 114 /* 0x618 MSR_DRAM_POWER_LIMIT */ 115 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 116 #define RAPL_DRAM_PERF_STATUS (1 << 4) 117 /* 0x61b MSR_DRAM_PERF_STATUS */ 118 #define RAPL_DRAM_POWER_INFO (1 << 5) 119 /* 0x61c MSR_DRAM_POWER_INFO */ 120 121 #define RAPL_CORES_POWER_LIMIT (1 << 6) 122 /* 0x638 MSR_PP0_POWER_LIMIT */ 123 #define RAPL_CORE_POLICY (1 << 7) 124 /* 0x63a MSR_PP0_POLICY */ 125 126 #define RAPL_GFX (1 << 8) 127 /* 0x640 MSR_PP1_POWER_LIMIT */ 128 /* 0x641 MSR_PP1_ENERGY_STATUS */ 129 /* 0x642 MSR_PP1_POLICY */ 130 131 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 132 /* 0x639 MSR_PP0_ENERGY_STATUS */ 133 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 134 #define TJMAX_DEFAULT 100 135 136 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 137 138 /* 139 * buffer size used by sscanf() for added column names 140 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 141 */ 142 #define NAME_BYTES 20 143 144 int backwards_count; 145 char *progname; 146 147 cpu_set_t *cpu_present_set, *cpu_affinity_set; 148 size_t cpu_present_setsize, cpu_affinity_setsize; 149 #define MAX_ADDED_COUNTERS 16 150 151 struct thread_data { 152 unsigned long long tsc; 153 unsigned long long aperf; 154 unsigned long long mperf; 155 unsigned long long c1; 156 unsigned int irq_count; 157 unsigned int smi_count; 158 unsigned int cpu_id; 159 unsigned int flags; 160 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 161 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 162 unsigned long long counter[MAX_ADDED_COUNTERS]; 163 } *thread_even, *thread_odd; 164 165 struct core_data { 166 unsigned long long c3; 167 unsigned long long c6; 168 unsigned long long c7; 169 unsigned int core_temp_c; 170 unsigned int core_id; 171 unsigned long long counter[MAX_ADDED_COUNTERS]; 172 } *core_even, *core_odd; 173 174 struct pkg_data { 175 unsigned long long pc2; 176 unsigned long long pc3; 177 unsigned long long pc6; 178 unsigned long long pc7; 179 unsigned long long pc8; 180 unsigned long long pc9; 181 unsigned long long pc10; 182 unsigned long long pkg_wtd_core_c0; 183 unsigned long long pkg_any_core_c0; 184 unsigned long long pkg_any_gfxe_c0; 185 unsigned long long pkg_both_core_gfxe_c0; 186 long long gfx_rc6_ms; 187 unsigned int gfx_mhz; 188 unsigned int package_id; 189 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 190 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 191 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 192 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 193 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 194 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 195 unsigned int pkg_temp_c; 196 unsigned long long counter[MAX_ADDED_COUNTERS]; 197 } *package_even, *package_odd; 198 199 #define ODD_COUNTERS thread_odd, core_odd, package_odd 200 #define EVEN_COUNTERS thread_even, core_even, package_even 201 202 #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \ 203 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \ 204 topo.num_threads_per_core + \ 205 (core_no) * topo.num_threads_per_core + (thread_no)) 206 #define GET_CORE(core_base, core_no, pkg_no) \ 207 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no)) 208 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 209 210 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; 211 enum counter_type {COUNTER_CYCLES, COUNTER_SECONDS}; 212 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; 213 214 struct msr_counter { 215 unsigned int msr_num; 216 char name[NAME_BYTES]; 217 unsigned int width; 218 enum counter_type type; 219 enum counter_format format; 220 struct msr_counter *next; 221 unsigned int flags; 222 #define FLAGS_HIDE (1 << 0) 223 #define FLAGS_SHOW (1 << 1) 224 }; 225 226 struct sys_counters { 227 unsigned int added_thread_counters; 228 unsigned int added_core_counters; 229 unsigned int added_package_counters; 230 struct msr_counter *tp; 231 struct msr_counter *cp; 232 struct msr_counter *pp; 233 } sys; 234 235 struct system_summary { 236 struct thread_data threads; 237 struct core_data cores; 238 struct pkg_data packages; 239 } average; 240 241 242 struct topo_params { 243 int num_packages; 244 int num_cpus; 245 int num_cores; 246 int max_cpu_num; 247 int num_cores_per_pkg; 248 int num_threads_per_core; 249 } topo; 250 251 struct timeval tv_even, tv_odd, tv_delta; 252 253 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 254 int *irqs_per_cpu; /* indexed by cpu_num */ 255 256 void setup_all_buffers(void); 257 258 int cpu_is_not_present(int cpu) 259 { 260 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 261 } 262 /* 263 * run func(thread, core, package) in topology order 264 * skip non-present cpus 265 */ 266 267 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 268 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 269 { 270 int retval, pkg_no, core_no, thread_no; 271 272 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 273 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { 274 for (thread_no = 0; thread_no < 275 topo.num_threads_per_core; ++thread_no) { 276 struct thread_data *t; 277 struct core_data *c; 278 struct pkg_data *p; 279 280 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); 281 282 if (cpu_is_not_present(t->cpu_id)) 283 continue; 284 285 c = GET_CORE(core_base, core_no, pkg_no); 286 p = GET_PKG(pkg_base, pkg_no); 287 288 retval = func(t, c, p); 289 if (retval) 290 return retval; 291 } 292 } 293 } 294 return 0; 295 } 296 297 int cpu_migrate(int cpu) 298 { 299 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 300 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 301 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 302 return -1; 303 else 304 return 0; 305 } 306 int get_msr_fd(int cpu) 307 { 308 char pathname[32]; 309 int fd; 310 311 fd = fd_percpu[cpu]; 312 313 if (fd) 314 return fd; 315 316 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 317 fd = open(pathname, O_RDONLY); 318 if (fd < 0) 319 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 320 321 fd_percpu[cpu] = fd; 322 323 return fd; 324 } 325 326 int get_msr(int cpu, off_t offset, unsigned long long *msr) 327 { 328 ssize_t retval; 329 330 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 331 332 if (retval != sizeof *msr) 333 err(-1, "msr %d offset 0x%llx read failed", cpu, (unsigned long long)offset); 334 335 return 0; 336 } 337 338 /* 339 * Each string in this array is compared in --show and --hide cmdline. 340 * Thus, strings that are proper sub-sets must follow their more specific peers. 341 */ 342 struct msr_counter bic[] = { 343 { 0x0, "Package" }, 344 { 0x0, "Avg_MHz" }, 345 { 0x0, "Bzy_MHz" }, 346 { 0x0, "TSC_MHz" }, 347 { 0x0, "IRQ" }, 348 { 0x0, "SMI", 32, 0, FORMAT_DELTA, NULL}, 349 { 0x0, "Busy%" }, 350 { 0x0, "CPU%c1" }, 351 { 0x0, "CPU%c3" }, 352 { 0x0, "CPU%c6" }, 353 { 0x0, "CPU%c7" }, 354 { 0x0, "ThreadC" }, 355 { 0x0, "CoreTmp" }, 356 { 0x0, "CoreCnt" }, 357 { 0x0, "PkgTmp" }, 358 { 0x0, "GFX%rc6" }, 359 { 0x0, "GFXMHz" }, 360 { 0x0, "Pkg%pc2" }, 361 { 0x0, "Pkg%pc3" }, 362 { 0x0, "Pkg%pc6" }, 363 { 0x0, "Pkg%pc7" }, 364 { 0x0, "PkgWatt" }, 365 { 0x0, "CorWatt" }, 366 { 0x0, "GFXWatt" }, 367 { 0x0, "PkgCnt" }, 368 { 0x0, "RAMWatt" }, 369 { 0x0, "PKG_%" }, 370 { 0x0, "RAM_%" }, 371 { 0x0, "Pkg_J" }, 372 { 0x0, "Cor_J" }, 373 { 0x0, "GFX_J" }, 374 { 0x0, "RAM_J" }, 375 { 0x0, "Core" }, 376 { 0x0, "CPU" }, 377 }; 378 379 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 380 #define BIC_Package (1ULL << 0) 381 #define BIC_Avg_MHz (1ULL << 1) 382 #define BIC_Bzy_MHz (1ULL << 2) 383 #define BIC_TSC_MHz (1ULL << 3) 384 #define BIC_IRQ (1ULL << 4) 385 #define BIC_SMI (1ULL << 5) 386 #define BIC_Busy (1ULL << 6) 387 #define BIC_CPU_c1 (1ULL << 7) 388 #define BIC_CPU_c3 (1ULL << 8) 389 #define BIC_CPU_c6 (1ULL << 9) 390 #define BIC_CPU_c7 (1ULL << 10) 391 #define BIC_ThreadC (1ULL << 11) 392 #define BIC_CoreTmp (1ULL << 12) 393 #define BIC_CoreCnt (1ULL << 13) 394 #define BIC_PkgTmp (1ULL << 14) 395 #define BIC_GFX_rc6 (1ULL << 15) 396 #define BIC_GFXMHz (1ULL << 16) 397 #define BIC_Pkgpc2 (1ULL << 17) 398 #define BIC_Pkgpc3 (1ULL << 18) 399 #define BIC_Pkgpc6 (1ULL << 19) 400 #define BIC_Pkgpc7 (1ULL << 20) 401 #define BIC_PkgWatt (1ULL << 21) 402 #define BIC_CorWatt (1ULL << 22) 403 #define BIC_GFXWatt (1ULL << 23) 404 #define BIC_PkgCnt (1ULL << 24) 405 #define BIC_RAMWatt (1ULL << 27) 406 #define BIC_PKG__ (1ULL << 28) 407 #define BIC_RAM__ (1ULL << 29) 408 #define BIC_Pkg_J (1ULL << 30) 409 #define BIC_Cor_J (1ULL << 31) 410 #define BIC_GFX_J (1ULL << 30) 411 #define BIC_RAM_J (1ULL << 31) 412 #define BIC_Core (1ULL << 32) 413 #define BIC_CPU (1ULL << 33) 414 415 unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL; 416 unsigned long long bic_present; 417 418 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 419 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 420 421 /* 422 * bic_lookup 423 * for all the strings in comma separate name_list, 424 * set the approprate bit in return value. 425 */ 426 unsigned long long bic_lookup(char *name_list) 427 { 428 int i; 429 unsigned long long retval = 0; 430 431 while (name_list) { 432 char *comma; 433 434 comma = strchr(name_list, ','); 435 436 if (comma) 437 *comma = '\0'; 438 439 for (i = 0; i < MAX_BIC; ++i) { 440 if (!strcmp(name_list, bic[i].name)) { 441 retval |= (1ULL << i); 442 break; 443 } 444 } 445 if (i == MAX_BIC) { 446 fprintf(stderr, "Invalid counter name: %s\n", name_list); 447 exit(-1); 448 } 449 450 name_list = comma; 451 if (name_list) 452 name_list++; 453 454 } 455 return retval; 456 } 457 458 void print_header(void) 459 { 460 struct msr_counter *mp; 461 462 if (DO_BIC(BIC_Package)) 463 outp += sprintf(outp, "\tPackage"); 464 if (DO_BIC(BIC_Core)) 465 outp += sprintf(outp, "\tCore"); 466 if (DO_BIC(BIC_CPU)) 467 outp += sprintf(outp, "\tCPU"); 468 if (DO_BIC(BIC_Avg_MHz)) 469 outp += sprintf(outp, "\tAvg_MHz"); 470 if (DO_BIC(BIC_Busy)) 471 outp += sprintf(outp, "\tBusy%%"); 472 if (DO_BIC(BIC_Bzy_MHz)) 473 outp += sprintf(outp, "\tBzy_MHz"); 474 if (DO_BIC(BIC_TSC_MHz)) 475 outp += sprintf(outp, "\tTSC_MHz"); 476 477 if (!debug) 478 goto done; 479 480 if (DO_BIC(BIC_IRQ)) 481 outp += sprintf(outp, "\tIRQ"); 482 if (DO_BIC(BIC_SMI)) 483 outp += sprintf(outp, "\tSMI"); 484 485 if (DO_BIC(BIC_CPU_c1)) 486 outp += sprintf(outp, "\tCPU%%c1"); 487 488 for (mp = sys.tp; mp; mp = mp->next) { 489 if (mp->format == FORMAT_RAW) { 490 if (mp->width == 64) 491 outp += sprintf(outp, "\t%18.18s", mp->name); 492 else 493 outp += sprintf(outp, "\t%10.10s", mp->name); 494 } else { 495 outp += sprintf(outp, "\t%-7.7s", mp->name); 496 } 497 } 498 499 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) 500 outp += sprintf(outp, "\tCPU%%c3"); 501 if (DO_BIC(BIC_CPU_c6)) 502 outp += sprintf(outp, "\tCPU%%c6"); 503 if (DO_BIC(BIC_CPU_c7)) 504 outp += sprintf(outp, "\tCPU%%c7"); 505 506 507 if (DO_BIC(BIC_CoreTmp)) 508 outp += sprintf(outp, "\tCoreTmp"); 509 510 for (mp = sys.cp; mp; mp = mp->next) { 511 if (mp->format == FORMAT_RAW) { 512 if (mp->width == 64) 513 outp += sprintf(outp, "\t%18.18s", mp->name); 514 else 515 outp += sprintf(outp, "\t%10.10s", mp->name); 516 } else { 517 outp += sprintf(outp, "\t%-7.7s", mp->name); 518 } 519 } 520 521 if (DO_BIC(BIC_PkgTmp)) 522 outp += sprintf(outp, "\tPkgTmp"); 523 524 if (DO_BIC(BIC_GFX_rc6)) 525 outp += sprintf(outp, "\tGFX%%rc6"); 526 527 if (DO_BIC(BIC_GFXMHz)) 528 outp += sprintf(outp, "\tGFXMHz"); 529 530 if (do_skl_residency) { 531 outp += sprintf(outp, "\tTotl%%C0"); 532 outp += sprintf(outp, "\tAny%%C0"); 533 outp += sprintf(outp, "\tGFX%%C0"); 534 outp += sprintf(outp, "\tCPUGFX%%"); 535 } 536 537 if (do_pc2) 538 outp += sprintf(outp, "\tPkg%%pc2"); 539 if (do_pc3) 540 outp += sprintf(outp, "\tPkg%%pc3"); 541 if (do_pc6) 542 outp += sprintf(outp, "\tPkg%%pc6"); 543 if (do_pc7) 544 outp += sprintf(outp, "\tPkg%%pc7"); 545 if (do_c8_c9_c10) { 546 outp += sprintf(outp, "\tPkg%%pc8"); 547 outp += sprintf(outp, "\tPkg%%pc9"); 548 outp += sprintf(outp, "\tPk%%pc10"); 549 } 550 551 if (do_rapl && !rapl_joules) { 552 if (DO_BIC(BIC_PkgWatt)) 553 outp += sprintf(outp, "\tPkgWatt"); 554 if (DO_BIC(BIC_CorWatt)) 555 outp += sprintf(outp, "\tCorWatt"); 556 if (DO_BIC(BIC_GFXWatt)) 557 outp += sprintf(outp, "\tGFXWatt"); 558 if (DO_BIC(BIC_RAMWatt)) 559 outp += sprintf(outp, "\tRAMWatt"); 560 if (DO_BIC(BIC_PKG__)) 561 outp += sprintf(outp, "\tPKG_%%"); 562 if (DO_BIC(BIC_RAM__)) 563 outp += sprintf(outp, "\tRAM_%%"); 564 } else if (do_rapl && rapl_joules) { 565 if (DO_BIC(BIC_Pkg_J)) 566 outp += sprintf(outp, "\tPkg_J"); 567 if (DO_BIC(BIC_Cor_J)) 568 outp += sprintf(outp, "\tCor_J"); 569 if (DO_BIC(BIC_GFX_J)) 570 outp += sprintf(outp, "\tGFX_J"); 571 if (DO_BIC(BIC_RAM_J)) 572 outp += sprintf(outp, "\tRAM_J"); 573 if (DO_BIC(BIC_PKG__)) 574 outp += sprintf(outp, "\tPKG_%%"); 575 if (DO_BIC(BIC_RAM__)) 576 outp += sprintf(outp, "\tRAM_%%"); 577 } 578 for (mp = sys.pp; mp; mp = mp->next) { 579 if (mp->format == FORMAT_RAW) { 580 if (mp->width == 64) 581 outp += sprintf(outp, "\t%18.18s", mp->name); 582 else 583 outp += sprintf(outp, "\t%10.10s", mp->name); 584 } else { 585 outp += sprintf(outp, "\t%-7.7s", mp->name); 586 } 587 } 588 589 done: 590 outp += sprintf(outp, "\n"); 591 } 592 593 int dump_counters(struct thread_data *t, struct core_data *c, 594 struct pkg_data *p) 595 { 596 int i; 597 struct msr_counter *mp; 598 599 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 600 601 if (t) { 602 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 603 t->cpu_id, t->flags); 604 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 605 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 606 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 607 outp += sprintf(outp, "c1: %016llX\n", t->c1); 608 609 if (DO_BIC(BIC_IRQ)) 610 outp += sprintf(outp, "IRQ: %08X\n", t->irq_count); 611 if (DO_BIC(BIC_SMI)) 612 outp += sprintf(outp, "SMI: %08X\n", t->smi_count); 613 614 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 615 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", 616 i, mp->msr_num, t->counter[i]); 617 } 618 } 619 620 if (c) { 621 outp += sprintf(outp, "core: %d\n", c->core_id); 622 outp += sprintf(outp, "c3: %016llX\n", c->c3); 623 outp += sprintf(outp, "c6: %016llX\n", c->c6); 624 outp += sprintf(outp, "c7: %016llX\n", c->c7); 625 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 626 627 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 628 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", 629 i, mp->msr_num, c->counter[i]); 630 } 631 } 632 633 if (p) { 634 outp += sprintf(outp, "package: %d\n", p->package_id); 635 636 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 637 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 638 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 639 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 640 641 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 642 if (do_pc3) 643 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 644 if (do_pc6) 645 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 646 if (do_pc7) 647 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 648 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 649 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 650 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 651 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); 652 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); 653 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); 654 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); 655 outp += sprintf(outp, "Throttle PKG: %0X\n", 656 p->rapl_pkg_perf_status); 657 outp += sprintf(outp, "Throttle RAM: %0X\n", 658 p->rapl_dram_perf_status); 659 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 660 661 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 662 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", 663 i, mp->msr_num, p->counter[i]); 664 } 665 } 666 667 outp += sprintf(outp, "\n"); 668 669 return 0; 670 } 671 672 /* 673 * column formatting convention & formats 674 */ 675 int format_counters(struct thread_data *t, struct core_data *c, 676 struct pkg_data *p) 677 { 678 double interval_float; 679 char *fmt8; 680 int i; 681 struct msr_counter *mp; 682 683 /* if showing only 1st thread in core and this isn't one, bail out */ 684 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 685 return 0; 686 687 /* if showing only 1st thread in pkg and this isn't one, bail out */ 688 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 689 return 0; 690 691 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; 692 693 /* topo columns, print blanks on 1st (average) line */ 694 if (t == &average.threads) { 695 if (DO_BIC(BIC_Package)) 696 outp += sprintf(outp, "\t-"); 697 if (DO_BIC(BIC_Core)) 698 outp += sprintf(outp, "\t-"); 699 if (DO_BIC(BIC_CPU)) 700 outp += sprintf(outp, "\t-"); 701 } else { 702 if (DO_BIC(BIC_Package)) { 703 if (p) 704 outp += sprintf(outp, "\t%d", p->package_id); 705 else 706 outp += sprintf(outp, "\t-"); 707 } 708 if (DO_BIC(BIC_Core)) { 709 if (c) 710 outp += sprintf(outp, "\t%d", c->core_id); 711 else 712 outp += sprintf(outp, "\t-"); 713 } 714 if (DO_BIC(BIC_CPU)) 715 outp += sprintf(outp, "\t%d", t->cpu_id); 716 } 717 718 if (DO_BIC(BIC_Avg_MHz)) 719 outp += sprintf(outp, "\t%.0f", 720 1.0 / units * t->aperf / interval_float); 721 722 if (DO_BIC(BIC_Busy)) 723 outp += sprintf(outp, "\t%.2f", 100.0 * t->mperf/t->tsc/tsc_tweak); 724 725 if (DO_BIC(BIC_Bzy_MHz)) { 726 if (has_base_hz) 727 outp += sprintf(outp, "\t%.0f", base_hz / units * t->aperf / t->mperf); 728 else 729 outp += sprintf(outp, "\t%.0f", 730 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float); 731 } 732 733 if (DO_BIC(BIC_TSC_MHz)) 734 outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float); 735 736 if (!debug) 737 goto done; 738 739 /* IRQ */ 740 if (DO_BIC(BIC_IRQ)) 741 outp += sprintf(outp, "\t%d", t->irq_count); 742 743 /* SMI */ 744 if (DO_BIC(BIC_SMI)) 745 outp += sprintf(outp, "\t%d", t->smi_count); 746 747 /* C1 */ 748 if (DO_BIC(BIC_CPU_c1)) 749 outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/t->tsc); 750 751 /* Added counters */ 752 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 753 if (mp->format == FORMAT_RAW) { 754 if (mp->width == 32) 755 outp += sprintf(outp, "\t0x%08lx", (unsigned long) t->counter[i]); 756 else 757 outp += sprintf(outp, "\t0x%016llx", t->counter[i]); 758 } else if (mp->format == FORMAT_DELTA) { 759 outp += sprintf(outp, "\t%lld", t->counter[i]); 760 } else if (mp->format == FORMAT_PERCENT) { 761 outp += sprintf(outp, "\t%.2f", 100.0 * t->counter[i]/t->tsc); 762 } 763 } 764 765 /* print per-core data only for 1st thread in core */ 766 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 767 goto done; 768 769 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) 770 outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/t->tsc); 771 if (DO_BIC(BIC_CPU_c6)) 772 outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/t->tsc); 773 if (DO_BIC(BIC_CPU_c7)) 774 outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc); 775 776 if (DO_BIC(BIC_CoreTmp)) 777 outp += sprintf(outp, "\t%d", c->core_temp_c); 778 779 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 780 if (mp->format == FORMAT_RAW) { 781 if (mp->width == 32) 782 outp += sprintf(outp, "\t0x%08lx", (unsigned long) c->counter[i]); 783 else 784 outp += sprintf(outp, "\t0x%016llx", c->counter[i]); 785 } else if (mp->format == FORMAT_DELTA) { 786 outp += sprintf(outp, "\t%lld", c->counter[i]); 787 } else if (mp->format == FORMAT_PERCENT) { 788 outp += sprintf(outp, "\t%.2f", 100.0 * c->counter[i]/t->tsc); 789 } 790 } 791 792 /* print per-package data only for 1st core in package */ 793 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 794 goto done; 795 796 /* PkgTmp */ 797 if (DO_BIC(BIC_PkgTmp)) 798 outp += sprintf(outp, "\t%d", p->pkg_temp_c); 799 800 /* GFXrc6 */ 801 if (DO_BIC(BIC_GFX_rc6)) { 802 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 803 outp += sprintf(outp, "\t**.**"); 804 } else { 805 outp += sprintf(outp, "\t%.2f", 806 p->gfx_rc6_ms / 10.0 / interval_float); 807 } 808 } 809 810 /* GFXMHz */ 811 if (DO_BIC(BIC_GFXMHz)) 812 outp += sprintf(outp, "\t%d", p->gfx_mhz); 813 814 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 815 if (do_skl_residency) { 816 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc); 817 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_core_c0/t->tsc); 818 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc); 819 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc); 820 } 821 822 if (do_pc2) 823 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc2/t->tsc); 824 if (do_pc3) 825 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc3/t->tsc); 826 if (do_pc6) 827 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc6/t->tsc); 828 if (do_pc7) 829 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc7/t->tsc); 830 if (do_c8_c9_c10) { 831 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc8/t->tsc); 832 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc9/t->tsc); 833 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc10/t->tsc); 834 } 835 836 /* 837 * If measurement interval exceeds minimum RAPL Joule Counter range, 838 * indicate that results are suspect by printing "**" in fraction place. 839 */ 840 if (interval_float < rapl_joule_counter_range) 841 fmt8 = "\t%.2f"; 842 else 843 fmt8 = "%6.0f**"; 844 845 if (DO_BIC(BIC_PkgWatt)) 846 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float); 847 if (DO_BIC(BIC_CorWatt)) 848 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float); 849 if (DO_BIC(BIC_GFXWatt)) 850 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float); 851 if (DO_BIC(BIC_RAMWatt)) 852 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float); 853 if (DO_BIC(BIC_Pkg_J)) 854 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units); 855 if (DO_BIC(BIC_Cor_J)) 856 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units); 857 if (DO_BIC(BIC_GFX_J)) 858 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units); 859 if (DO_BIC(BIC_RAM_J)) 860 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units); 861 if (DO_BIC(BIC_PKG__)) 862 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 863 if (DO_BIC(BIC_RAM__)) 864 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 865 866 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 867 if (mp->format == FORMAT_RAW) { 868 if (mp->width == 32) 869 outp += sprintf(outp, "\t0x%08lx", (unsigned long) p->counter[i]); 870 else 871 outp += sprintf(outp, "\t0x%016llx", p->counter[i]); 872 } else if (mp->format == FORMAT_DELTA) { 873 outp += sprintf(outp, "\t%lld", p->counter[i]); 874 } else if (mp->format == FORMAT_PERCENT) { 875 outp += sprintf(outp, "\t%.2f", 100.0 * p->counter[i]/t->tsc); 876 } 877 } 878 879 done: 880 outp += sprintf(outp, "\n"); 881 882 return 0; 883 } 884 885 void flush_output_stdout(void) 886 { 887 FILE *filep; 888 889 if (outf == stderr) 890 filep = stdout; 891 else 892 filep = outf; 893 894 fputs(output_buffer, filep); 895 fflush(filep); 896 897 outp = output_buffer; 898 } 899 void flush_output_stderr(void) 900 { 901 fputs(output_buffer, outf); 902 fflush(outf); 903 outp = output_buffer; 904 } 905 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 906 { 907 static int printed; 908 909 if (!printed || !summary_only) 910 print_header(); 911 912 if (topo.num_cpus > 1) 913 format_counters(&average.threads, &average.cores, 914 &average.packages); 915 916 printed = 1; 917 918 if (summary_only) 919 return; 920 921 for_all_cpus(format_counters, t, c, p); 922 } 923 924 #define DELTA_WRAP32(new, old) \ 925 if (new > old) { \ 926 old = new - old; \ 927 } else { \ 928 old = 0x100000000 + new - old; \ 929 } 930 931 int 932 delta_package(struct pkg_data *new, struct pkg_data *old) 933 { 934 int i; 935 struct msr_counter *mp; 936 937 if (do_skl_residency) { 938 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 939 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 940 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 941 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 942 } 943 old->pc2 = new->pc2 - old->pc2; 944 if (do_pc3) 945 old->pc3 = new->pc3 - old->pc3; 946 if (do_pc6) 947 old->pc6 = new->pc6 - old->pc6; 948 if (do_pc7) 949 old->pc7 = new->pc7 - old->pc7; 950 old->pc8 = new->pc8 - old->pc8; 951 old->pc9 = new->pc9 - old->pc9; 952 old->pc10 = new->pc10 - old->pc10; 953 old->pkg_temp_c = new->pkg_temp_c; 954 955 /* flag an error when rc6 counter resets/wraps */ 956 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 957 old->gfx_rc6_ms = -1; 958 else 959 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 960 961 old->gfx_mhz = new->gfx_mhz; 962 963 DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 964 DELTA_WRAP32(new->energy_cores, old->energy_cores); 965 DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 966 DELTA_WRAP32(new->energy_dram, old->energy_dram); 967 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 968 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 969 970 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 971 if (mp->format == FORMAT_RAW) 972 old->counter[i] = new->counter[i]; 973 else 974 old->counter[i] = new->counter[i] - old->counter[i]; 975 } 976 977 return 0; 978 } 979 980 void 981 delta_core(struct core_data *new, struct core_data *old) 982 { 983 int i; 984 struct msr_counter *mp; 985 986 old->c3 = new->c3 - old->c3; 987 old->c6 = new->c6 - old->c6; 988 old->c7 = new->c7 - old->c7; 989 old->core_temp_c = new->core_temp_c; 990 991 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 992 if (mp->format == FORMAT_RAW) 993 old->counter[i] = new->counter[i]; 994 else 995 old->counter[i] = new->counter[i] - old->counter[i]; 996 } 997 } 998 999 /* 1000 * old = new - old 1001 */ 1002 int 1003 delta_thread(struct thread_data *new, struct thread_data *old, 1004 struct core_data *core_delta) 1005 { 1006 int i; 1007 struct msr_counter *mp; 1008 1009 old->tsc = new->tsc - old->tsc; 1010 1011 /* check for TSC < 1 Mcycles over interval */ 1012 if (old->tsc < (1000 * 1000)) 1013 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1014 "You can disable all c-states by booting with \"idle=poll\"\n" 1015 "or just the deep ones with \"processor.max_cstate=1\""); 1016 1017 old->c1 = new->c1 - old->c1; 1018 1019 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1020 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1021 old->aperf = new->aperf - old->aperf; 1022 old->mperf = new->mperf - old->mperf; 1023 } else { 1024 return -1; 1025 } 1026 } 1027 1028 1029 if (use_c1_residency_msr) { 1030 /* 1031 * Some models have a dedicated C1 residency MSR, 1032 * which should be more accurate than the derivation below. 1033 */ 1034 } else { 1035 /* 1036 * As counter collection is not atomic, 1037 * it is possible for mperf's non-halted cycles + idle states 1038 * to exceed TSC's all cycles: show c1 = 0% in that case. 1039 */ 1040 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc) 1041 old->c1 = 0; 1042 else { 1043 /* normal case, derive c1 */ 1044 old->c1 = old->tsc - old->mperf - core_delta->c3 1045 - core_delta->c6 - core_delta->c7; 1046 } 1047 } 1048 1049 if (old->mperf == 0) { 1050 if (debug > 1) 1051 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1052 old->mperf = 1; /* divide by 0 protection */ 1053 } 1054 1055 if (DO_BIC(BIC_IRQ)) 1056 old->irq_count = new->irq_count - old->irq_count; 1057 1058 if (DO_BIC(BIC_SMI)) 1059 old->smi_count = new->smi_count - old->smi_count; 1060 1061 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1062 if (mp->format == FORMAT_RAW) 1063 old->counter[i] = new->counter[i]; 1064 else 1065 old->counter[i] = new->counter[i] - old->counter[i]; 1066 } 1067 return 0; 1068 } 1069 1070 int delta_cpu(struct thread_data *t, struct core_data *c, 1071 struct pkg_data *p, struct thread_data *t2, 1072 struct core_data *c2, struct pkg_data *p2) 1073 { 1074 int retval = 0; 1075 1076 /* calculate core delta only for 1st thread in core */ 1077 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1078 delta_core(c, c2); 1079 1080 /* always calculate thread delta */ 1081 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1082 if (retval) 1083 return retval; 1084 1085 /* calculate package delta only for 1st core in package */ 1086 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1087 retval = delta_package(p, p2); 1088 1089 return retval; 1090 } 1091 1092 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1093 { 1094 int i; 1095 struct msr_counter *mp; 1096 1097 t->tsc = 0; 1098 t->aperf = 0; 1099 t->mperf = 0; 1100 t->c1 = 0; 1101 1102 t->irq_count = 0; 1103 t->smi_count = 0; 1104 1105 /* tells format_counters to dump all fields from this set */ 1106 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1107 1108 c->c3 = 0; 1109 c->c6 = 0; 1110 c->c7 = 0; 1111 c->core_temp_c = 0; 1112 1113 p->pkg_wtd_core_c0 = 0; 1114 p->pkg_any_core_c0 = 0; 1115 p->pkg_any_gfxe_c0 = 0; 1116 p->pkg_both_core_gfxe_c0 = 0; 1117 1118 p->pc2 = 0; 1119 if (do_pc3) 1120 p->pc3 = 0; 1121 if (do_pc6) 1122 p->pc6 = 0; 1123 if (do_pc7) 1124 p->pc7 = 0; 1125 p->pc8 = 0; 1126 p->pc9 = 0; 1127 p->pc10 = 0; 1128 1129 p->energy_pkg = 0; 1130 p->energy_dram = 0; 1131 p->energy_cores = 0; 1132 p->energy_gfx = 0; 1133 p->rapl_pkg_perf_status = 0; 1134 p->rapl_dram_perf_status = 0; 1135 p->pkg_temp_c = 0; 1136 1137 p->gfx_rc6_ms = 0; 1138 p->gfx_mhz = 0; 1139 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1140 t->counter[i] = 0; 1141 1142 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1143 c->counter[i] = 0; 1144 1145 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1146 p->counter[i] = 0; 1147 } 1148 int sum_counters(struct thread_data *t, struct core_data *c, 1149 struct pkg_data *p) 1150 { 1151 int i; 1152 struct msr_counter *mp; 1153 1154 average.threads.tsc += t->tsc; 1155 average.threads.aperf += t->aperf; 1156 average.threads.mperf += t->mperf; 1157 average.threads.c1 += t->c1; 1158 1159 average.threads.irq_count += t->irq_count; 1160 average.threads.smi_count += t->smi_count; 1161 1162 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1163 if (mp->format == FORMAT_RAW) 1164 continue; 1165 average.threads.counter[i] += t->counter[i]; 1166 } 1167 1168 /* sum per-core values only for 1st thread in core */ 1169 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1170 return 0; 1171 1172 average.cores.c3 += c->c3; 1173 average.cores.c6 += c->c6; 1174 average.cores.c7 += c->c7; 1175 1176 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1177 1178 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1179 if (mp->format == FORMAT_RAW) 1180 continue; 1181 average.cores.counter[i] += c->counter[i]; 1182 } 1183 1184 /* sum per-pkg values only for 1st core in pkg */ 1185 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1186 return 0; 1187 1188 if (do_skl_residency) { 1189 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1190 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1191 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1192 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1193 } 1194 1195 average.packages.pc2 += p->pc2; 1196 if (do_pc3) 1197 average.packages.pc3 += p->pc3; 1198 if (do_pc6) 1199 average.packages.pc6 += p->pc6; 1200 if (do_pc7) 1201 average.packages.pc7 += p->pc7; 1202 average.packages.pc8 += p->pc8; 1203 average.packages.pc9 += p->pc9; 1204 average.packages.pc10 += p->pc10; 1205 1206 average.packages.energy_pkg += p->energy_pkg; 1207 average.packages.energy_dram += p->energy_dram; 1208 average.packages.energy_cores += p->energy_cores; 1209 average.packages.energy_gfx += p->energy_gfx; 1210 1211 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1212 average.packages.gfx_mhz = p->gfx_mhz; 1213 1214 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1215 1216 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1217 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1218 1219 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1220 if (mp->format == FORMAT_RAW) 1221 continue; 1222 average.packages.counter[i] += p->counter[i]; 1223 } 1224 return 0; 1225 } 1226 /* 1227 * sum the counters for all cpus in the system 1228 * compute the weighted average 1229 */ 1230 void compute_average(struct thread_data *t, struct core_data *c, 1231 struct pkg_data *p) 1232 { 1233 int i; 1234 struct msr_counter *mp; 1235 1236 clear_counters(&average.threads, &average.cores, &average.packages); 1237 1238 for_all_cpus(sum_counters, t, c, p); 1239 1240 average.threads.tsc /= topo.num_cpus; 1241 average.threads.aperf /= topo.num_cpus; 1242 average.threads.mperf /= topo.num_cpus; 1243 average.threads.c1 /= topo.num_cpus; 1244 1245 average.cores.c3 /= topo.num_cores; 1246 average.cores.c6 /= topo.num_cores; 1247 average.cores.c7 /= topo.num_cores; 1248 1249 if (do_skl_residency) { 1250 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1251 average.packages.pkg_any_core_c0 /= topo.num_packages; 1252 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1253 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1254 } 1255 1256 average.packages.pc2 /= topo.num_packages; 1257 if (do_pc3) 1258 average.packages.pc3 /= topo.num_packages; 1259 if (do_pc6) 1260 average.packages.pc6 /= topo.num_packages; 1261 if (do_pc7) 1262 average.packages.pc7 /= topo.num_packages; 1263 1264 average.packages.pc8 /= topo.num_packages; 1265 average.packages.pc9 /= topo.num_packages; 1266 average.packages.pc10 /= topo.num_packages; 1267 1268 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1269 if (mp->format == FORMAT_RAW) 1270 continue; 1271 average.threads.counter[i] /= topo.num_cpus; 1272 } 1273 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1274 if (mp->format == FORMAT_RAW) 1275 continue; 1276 average.cores.counter[i] /= topo.num_cores; 1277 } 1278 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1279 if (mp->format == FORMAT_RAW) 1280 continue; 1281 average.packages.counter[i] /= topo.num_packages; 1282 } 1283 } 1284 1285 static unsigned long long rdtsc(void) 1286 { 1287 unsigned int low, high; 1288 1289 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1290 1291 return low | ((unsigned long long)high) << 32; 1292 } 1293 1294 /* 1295 * get_counters(...) 1296 * migrate to cpu 1297 * acquire and record local counters for that cpu 1298 */ 1299 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1300 { 1301 int cpu = t->cpu_id; 1302 unsigned long long msr; 1303 int aperf_mperf_retry_count = 0; 1304 struct msr_counter *mp; 1305 int i; 1306 1307 if (cpu_migrate(cpu)) { 1308 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1309 return -1; 1310 } 1311 1312 retry: 1313 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1314 1315 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1316 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1317 1318 /* 1319 * The TSC, APERF and MPERF must be read together for 1320 * APERF/MPERF and MPERF/TSC to give accurate results. 1321 * 1322 * Unfortunately, APERF and MPERF are read by 1323 * individual system call, so delays may occur 1324 * between them. If the time to read them 1325 * varies by a large amount, we re-read them. 1326 */ 1327 1328 /* 1329 * This initial dummy APERF read has been seen to 1330 * reduce jitter in the subsequent reads. 1331 */ 1332 1333 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1334 return -3; 1335 1336 t->tsc = rdtsc(); /* re-read close to APERF */ 1337 1338 tsc_before = t->tsc; 1339 1340 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1341 return -3; 1342 1343 tsc_between = rdtsc(); 1344 1345 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1346 return -4; 1347 1348 tsc_after = rdtsc(); 1349 1350 aperf_time = tsc_between - tsc_before; 1351 mperf_time = tsc_after - tsc_between; 1352 1353 /* 1354 * If the system call latency to read APERF and MPERF 1355 * differ by more than 2x, then try again. 1356 */ 1357 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1358 aperf_mperf_retry_count++; 1359 if (aperf_mperf_retry_count < 5) 1360 goto retry; 1361 else 1362 warnx("cpu%d jitter %lld %lld", 1363 cpu, aperf_time, mperf_time); 1364 } 1365 aperf_mperf_retry_count = 0; 1366 1367 t->aperf = t->aperf * aperf_mperf_multiplier; 1368 t->mperf = t->mperf * aperf_mperf_multiplier; 1369 } 1370 1371 if (DO_BIC(BIC_IRQ)) 1372 t->irq_count = irqs_per_cpu[cpu]; 1373 if (DO_BIC(BIC_SMI)) { 1374 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1375 return -5; 1376 t->smi_count = msr & 0xFFFFFFFF; 1377 } 1378 1379 if (use_c1_residency_msr) { 1380 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 1381 return -6; 1382 } 1383 1384 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1385 if (get_msr(cpu, mp->msr_num, &t->counter[i])) 1386 return -10; 1387 } 1388 1389 1390 /* collect core counters only for 1st thread in core */ 1391 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1392 return 0; 1393 1394 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) { 1395 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1396 return -6; 1397 } 1398 1399 if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) { 1400 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1401 return -7; 1402 } else if (do_knl_cstates) { 1403 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1404 return -7; 1405 } 1406 1407 if (DO_BIC(BIC_CPU_c7)) 1408 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1409 return -8; 1410 1411 if (DO_BIC(BIC_CoreTmp)) { 1412 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1413 return -9; 1414 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1415 } 1416 1417 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1418 if (get_msr(cpu, mp->msr_num, &c->counter[i])) 1419 return -10; 1420 } 1421 1422 /* collect package counters only for 1st core in package */ 1423 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1424 return 0; 1425 1426 if (do_skl_residency) { 1427 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 1428 return -10; 1429 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 1430 return -11; 1431 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 1432 return -12; 1433 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 1434 return -13; 1435 } 1436 if (do_pc3) 1437 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 1438 return -9; 1439 if (do_pc6) 1440 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 1441 return -10; 1442 if (do_pc2) 1443 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 1444 return -11; 1445 if (do_pc7) 1446 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 1447 return -12; 1448 if (do_c8_c9_c10) { 1449 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 1450 return -13; 1451 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 1452 return -13; 1453 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 1454 return -13; 1455 } 1456 if (do_rapl & RAPL_PKG) { 1457 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 1458 return -13; 1459 p->energy_pkg = msr & 0xFFFFFFFF; 1460 } 1461 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 1462 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 1463 return -14; 1464 p->energy_cores = msr & 0xFFFFFFFF; 1465 } 1466 if (do_rapl & RAPL_DRAM) { 1467 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 1468 return -15; 1469 p->energy_dram = msr & 0xFFFFFFFF; 1470 } 1471 if (do_rapl & RAPL_GFX) { 1472 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 1473 return -16; 1474 p->energy_gfx = msr & 0xFFFFFFFF; 1475 } 1476 if (do_rapl & RAPL_PKG_PERF_STATUS) { 1477 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 1478 return -16; 1479 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 1480 } 1481 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 1482 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 1483 return -16; 1484 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 1485 } 1486 if (DO_BIC(BIC_PkgTmp)) { 1487 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 1488 return -17; 1489 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1490 } 1491 1492 if (DO_BIC(BIC_GFX_rc6)) 1493 p->gfx_rc6_ms = gfx_cur_rc6_ms; 1494 1495 if (DO_BIC(BIC_GFXMHz)) 1496 p->gfx_mhz = gfx_cur_mhz; 1497 1498 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1499 if (get_msr(cpu, mp->msr_num, &p->counter[i])) 1500 return -10; 1501 } 1502 1503 return 0; 1504 } 1505 1506 /* 1507 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 1508 * If you change the values, note they are used both in comparisons 1509 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 1510 */ 1511 1512 #define PCLUKN 0 /* Unknown */ 1513 #define PCLRSV 1 /* Reserved */ 1514 #define PCL__0 2 /* PC0 */ 1515 #define PCL__1 3 /* PC1 */ 1516 #define PCL__2 4 /* PC2 */ 1517 #define PCL__3 5 /* PC3 */ 1518 #define PCL__4 6 /* PC4 */ 1519 #define PCL__6 7 /* PC6 */ 1520 #define PCL_6N 8 /* PC6 No Retention */ 1521 #define PCL_6R 9 /* PC6 Retention */ 1522 #define PCL__7 10 /* PC7 */ 1523 #define PCL_7S 11 /* PC7 Shrink */ 1524 #define PCL__8 12 /* PC8 */ 1525 #define PCL__9 13 /* PC9 */ 1526 #define PCLUNL 14 /* Unlimited */ 1527 1528 int pkg_cstate_limit = PCLUKN; 1529 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 1530 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"}; 1531 1532 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1533 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1534 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1535 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1536 int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1537 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1538 int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1539 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1540 1541 1542 static void 1543 calculate_tsc_tweak() 1544 { 1545 tsc_tweak = base_hz / tsc_hz; 1546 } 1547 1548 static void 1549 dump_nhm_platform_info(void) 1550 { 1551 unsigned long long msr; 1552 unsigned int ratio; 1553 1554 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 1555 1556 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 1557 1558 ratio = (msr >> 40) & 0xFF; 1559 fprintf(outf, "%d * %.0f = %.0f MHz max efficiency frequency\n", 1560 ratio, bclk, ratio * bclk); 1561 1562 ratio = (msr >> 8) & 0xFF; 1563 fprintf(outf, "%d * %.0f = %.0f MHz base frequency\n", 1564 ratio, bclk, ratio * bclk); 1565 1566 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 1567 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 1568 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 1569 1570 return; 1571 } 1572 1573 static void 1574 dump_hsw_turbo_ratio_limits(void) 1575 { 1576 unsigned long long msr; 1577 unsigned int ratio; 1578 1579 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 1580 1581 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 1582 1583 ratio = (msr >> 8) & 0xFF; 1584 if (ratio) 1585 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 18 active cores\n", 1586 ratio, bclk, ratio * bclk); 1587 1588 ratio = (msr >> 0) & 0xFF; 1589 if (ratio) 1590 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 17 active cores\n", 1591 ratio, bclk, ratio * bclk); 1592 return; 1593 } 1594 1595 static void 1596 dump_ivt_turbo_ratio_limits(void) 1597 { 1598 unsigned long long msr; 1599 unsigned int ratio; 1600 1601 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 1602 1603 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 1604 1605 ratio = (msr >> 56) & 0xFF; 1606 if (ratio) 1607 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 16 active cores\n", 1608 ratio, bclk, ratio * bclk); 1609 1610 ratio = (msr >> 48) & 0xFF; 1611 if (ratio) 1612 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 15 active cores\n", 1613 ratio, bclk, ratio * bclk); 1614 1615 ratio = (msr >> 40) & 0xFF; 1616 if (ratio) 1617 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 14 active cores\n", 1618 ratio, bclk, ratio * bclk); 1619 1620 ratio = (msr >> 32) & 0xFF; 1621 if (ratio) 1622 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 13 active cores\n", 1623 ratio, bclk, ratio * bclk); 1624 1625 ratio = (msr >> 24) & 0xFF; 1626 if (ratio) 1627 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 12 active cores\n", 1628 ratio, bclk, ratio * bclk); 1629 1630 ratio = (msr >> 16) & 0xFF; 1631 if (ratio) 1632 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 11 active cores\n", 1633 ratio, bclk, ratio * bclk); 1634 1635 ratio = (msr >> 8) & 0xFF; 1636 if (ratio) 1637 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 10 active cores\n", 1638 ratio, bclk, ratio * bclk); 1639 1640 ratio = (msr >> 0) & 0xFF; 1641 if (ratio) 1642 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 9 active cores\n", 1643 ratio, bclk, ratio * bclk); 1644 return; 1645 } 1646 1647 static void 1648 dump_nhm_turbo_ratio_limits(void) 1649 { 1650 unsigned long long msr; 1651 unsigned int ratio; 1652 1653 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 1654 1655 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 1656 1657 ratio = (msr >> 56) & 0xFF; 1658 if (ratio) 1659 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 8 active cores\n", 1660 ratio, bclk, ratio * bclk); 1661 1662 ratio = (msr >> 48) & 0xFF; 1663 if (ratio) 1664 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 7 active cores\n", 1665 ratio, bclk, ratio * bclk); 1666 1667 ratio = (msr >> 40) & 0xFF; 1668 if (ratio) 1669 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 6 active cores\n", 1670 ratio, bclk, ratio * bclk); 1671 1672 ratio = (msr >> 32) & 0xFF; 1673 if (ratio) 1674 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 5 active cores\n", 1675 ratio, bclk, ratio * bclk); 1676 1677 ratio = (msr >> 24) & 0xFF; 1678 if (ratio) 1679 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 4 active cores\n", 1680 ratio, bclk, ratio * bclk); 1681 1682 ratio = (msr >> 16) & 0xFF; 1683 if (ratio) 1684 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 3 active cores\n", 1685 ratio, bclk, ratio * bclk); 1686 1687 ratio = (msr >> 8) & 0xFF; 1688 if (ratio) 1689 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 2 active cores\n", 1690 ratio, bclk, ratio * bclk); 1691 1692 ratio = (msr >> 0) & 0xFF; 1693 if (ratio) 1694 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 1 active cores\n", 1695 ratio, bclk, ratio * bclk); 1696 return; 1697 } 1698 1699 static void 1700 dump_knl_turbo_ratio_limits(void) 1701 { 1702 const unsigned int buckets_no = 7; 1703 1704 unsigned long long msr; 1705 int delta_cores, delta_ratio; 1706 int i, b_nr; 1707 unsigned int cores[buckets_no]; 1708 unsigned int ratio[buckets_no]; 1709 1710 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 1711 1712 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 1713 base_cpu, msr); 1714 1715 /** 1716 * Turbo encoding in KNL is as follows: 1717 * [0] -- Reserved 1718 * [7:1] -- Base value of number of active cores of bucket 1. 1719 * [15:8] -- Base value of freq ratio of bucket 1. 1720 * [20:16] -- +ve delta of number of active cores of bucket 2. 1721 * i.e. active cores of bucket 2 = 1722 * active cores of bucket 1 + delta 1723 * [23:21] -- Negative delta of freq ratio of bucket 2. 1724 * i.e. freq ratio of bucket 2 = 1725 * freq ratio of bucket 1 - delta 1726 * [28:24]-- +ve delta of number of active cores of bucket 3. 1727 * [31:29]-- -ve delta of freq ratio of bucket 3. 1728 * [36:32]-- +ve delta of number of active cores of bucket 4. 1729 * [39:37]-- -ve delta of freq ratio of bucket 4. 1730 * [44:40]-- +ve delta of number of active cores of bucket 5. 1731 * [47:45]-- -ve delta of freq ratio of bucket 5. 1732 * [52:48]-- +ve delta of number of active cores of bucket 6. 1733 * [55:53]-- -ve delta of freq ratio of bucket 6. 1734 * [60:56]-- +ve delta of number of active cores of bucket 7. 1735 * [63:61]-- -ve delta of freq ratio of bucket 7. 1736 */ 1737 1738 b_nr = 0; 1739 cores[b_nr] = (msr & 0xFF) >> 1; 1740 ratio[b_nr] = (msr >> 8) & 0xFF; 1741 1742 for (i = 16; i < 64; i += 8) { 1743 delta_cores = (msr >> i) & 0x1F; 1744 delta_ratio = (msr >> (i + 5)) & 0x7; 1745 1746 cores[b_nr + 1] = cores[b_nr] + delta_cores; 1747 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 1748 b_nr++; 1749 } 1750 1751 for (i = buckets_no - 1; i >= 0; i--) 1752 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 1753 fprintf(outf, 1754 "%d * %.0f = %.0f MHz max turbo %d active cores\n", 1755 ratio[i], bclk, ratio[i] * bclk, cores[i]); 1756 } 1757 1758 static void 1759 dump_nhm_cst_cfg(void) 1760 { 1761 unsigned long long msr; 1762 1763 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); 1764 1765 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 1766 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 1767 1768 fprintf(outf, "cpu%d: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", base_cpu, msr); 1769 1770 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n", 1771 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 1772 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 1773 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 1774 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 1775 (msr & (1 << 15)) ? "" : "UN", 1776 (unsigned int)msr & 0xF, 1777 pkg_cstate_limit_strings[pkg_cstate_limit]); 1778 return; 1779 } 1780 1781 static void 1782 dump_config_tdp(void) 1783 { 1784 unsigned long long msr; 1785 1786 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 1787 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 1788 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 1789 1790 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 1791 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 1792 if (msr) { 1793 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 1794 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 1795 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 1796 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 1797 } 1798 fprintf(outf, ")\n"); 1799 1800 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 1801 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 1802 if (msr) { 1803 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 1804 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 1805 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 1806 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 1807 } 1808 fprintf(outf, ")\n"); 1809 1810 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 1811 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 1812 if ((msr) & 0x3) 1813 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 1814 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 1815 fprintf(outf, ")\n"); 1816 1817 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 1818 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 1819 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 1820 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 1821 fprintf(outf, ")\n"); 1822 } 1823 1824 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 1825 1826 void print_irtl(void) 1827 { 1828 unsigned long long msr; 1829 1830 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 1831 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 1832 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1833 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1834 1835 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 1836 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 1837 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1838 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1839 1840 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 1841 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 1842 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1843 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1844 1845 if (!do_irtl_hsw) 1846 return; 1847 1848 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 1849 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 1850 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1851 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1852 1853 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 1854 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 1855 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1856 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1857 1858 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 1859 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 1860 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1861 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1862 1863 } 1864 void free_fd_percpu(void) 1865 { 1866 int i; 1867 1868 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 1869 if (fd_percpu[i] != 0) 1870 close(fd_percpu[i]); 1871 } 1872 1873 free(fd_percpu); 1874 } 1875 1876 void free_all_buffers(void) 1877 { 1878 CPU_FREE(cpu_present_set); 1879 cpu_present_set = NULL; 1880 cpu_present_setsize = 0; 1881 1882 CPU_FREE(cpu_affinity_set); 1883 cpu_affinity_set = NULL; 1884 cpu_affinity_setsize = 0; 1885 1886 free(thread_even); 1887 free(core_even); 1888 free(package_even); 1889 1890 thread_even = NULL; 1891 core_even = NULL; 1892 package_even = NULL; 1893 1894 free(thread_odd); 1895 free(core_odd); 1896 free(package_odd); 1897 1898 thread_odd = NULL; 1899 core_odd = NULL; 1900 package_odd = NULL; 1901 1902 free(output_buffer); 1903 output_buffer = NULL; 1904 outp = NULL; 1905 1906 free_fd_percpu(); 1907 1908 free(irq_column_2_cpu); 1909 free(irqs_per_cpu); 1910 } 1911 1912 /* 1913 * Open a file, and exit on failure 1914 */ 1915 FILE *fopen_or_die(const char *path, const char *mode) 1916 { 1917 FILE *filep = fopen(path, mode); 1918 if (!filep) 1919 err(1, "%s: open failed", path); 1920 return filep; 1921 } 1922 1923 /* 1924 * Parse a file containing a single int. 1925 */ 1926 int parse_int_file(const char *fmt, ...) 1927 { 1928 va_list args; 1929 char path[PATH_MAX]; 1930 FILE *filep; 1931 int value; 1932 1933 va_start(args, fmt); 1934 vsnprintf(path, sizeof(path), fmt, args); 1935 va_end(args); 1936 filep = fopen_or_die(path, "r"); 1937 if (fscanf(filep, "%d", &value) != 1) 1938 err(1, "%s: failed to parse number from file", path); 1939 fclose(filep); 1940 return value; 1941 } 1942 1943 /* 1944 * get_cpu_position_in_core(cpu) 1945 * return the position of the CPU among its HT siblings in the core 1946 * return -1 if the sibling is not in list 1947 */ 1948 int get_cpu_position_in_core(int cpu) 1949 { 1950 char path[64]; 1951 FILE *filep; 1952 int this_cpu; 1953 char character; 1954 int i; 1955 1956 sprintf(path, 1957 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", 1958 cpu); 1959 filep = fopen(path, "r"); 1960 if (filep == NULL) { 1961 perror(path); 1962 exit(1); 1963 } 1964 1965 for (i = 0; i < topo.num_threads_per_core; i++) { 1966 fscanf(filep, "%d", &this_cpu); 1967 if (this_cpu == cpu) { 1968 fclose(filep); 1969 return i; 1970 } 1971 1972 /* Account for no separator after last thread*/ 1973 if (i != (topo.num_threads_per_core - 1)) 1974 fscanf(filep, "%c", &character); 1975 } 1976 1977 fclose(filep); 1978 return -1; 1979 } 1980 1981 /* 1982 * cpu_is_first_core_in_package(cpu) 1983 * return 1 if given CPU is 1st core in package 1984 */ 1985 int cpu_is_first_core_in_package(int cpu) 1986 { 1987 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 1988 } 1989 1990 int get_physical_package_id(int cpu) 1991 { 1992 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 1993 } 1994 1995 int get_core_id(int cpu) 1996 { 1997 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 1998 } 1999 2000 int get_num_ht_siblings(int cpu) 2001 { 2002 char path[80]; 2003 FILE *filep; 2004 int sib1; 2005 int matches = 0; 2006 char character; 2007 char str[100]; 2008 char *ch; 2009 2010 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu); 2011 filep = fopen_or_die(path, "r"); 2012 2013 /* 2014 * file format: 2015 * A ',' separated or '-' separated set of numbers 2016 * (eg 1-2 or 1,3,4,5) 2017 */ 2018 fscanf(filep, "%d%c\n", &sib1, &character); 2019 fseek(filep, 0, SEEK_SET); 2020 fgets(str, 100, filep); 2021 ch = strchr(str, character); 2022 while (ch != NULL) { 2023 matches++; 2024 ch = strchr(ch+1, character); 2025 } 2026 2027 fclose(filep); 2028 return matches+1; 2029 } 2030 2031 /* 2032 * run func(thread, core, package) in topology order 2033 * skip non-present cpus 2034 */ 2035 2036 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 2037 struct pkg_data *, struct thread_data *, struct core_data *, 2038 struct pkg_data *), struct thread_data *thread_base, 2039 struct core_data *core_base, struct pkg_data *pkg_base, 2040 struct thread_data *thread_base2, struct core_data *core_base2, 2041 struct pkg_data *pkg_base2) 2042 { 2043 int retval, pkg_no, core_no, thread_no; 2044 2045 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2046 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { 2047 for (thread_no = 0; thread_no < 2048 topo.num_threads_per_core; ++thread_no) { 2049 struct thread_data *t, *t2; 2050 struct core_data *c, *c2; 2051 struct pkg_data *p, *p2; 2052 2053 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); 2054 2055 if (cpu_is_not_present(t->cpu_id)) 2056 continue; 2057 2058 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no); 2059 2060 c = GET_CORE(core_base, core_no, pkg_no); 2061 c2 = GET_CORE(core_base2, core_no, pkg_no); 2062 2063 p = GET_PKG(pkg_base, pkg_no); 2064 p2 = GET_PKG(pkg_base2, pkg_no); 2065 2066 retval = func(t, c, p, t2, c2, p2); 2067 if (retval) 2068 return retval; 2069 } 2070 } 2071 } 2072 return 0; 2073 } 2074 2075 /* 2076 * run func(cpu) on every cpu in /proc/stat 2077 * return max_cpu number 2078 */ 2079 int for_all_proc_cpus(int (func)(int)) 2080 { 2081 FILE *fp; 2082 int cpu_num; 2083 int retval; 2084 2085 fp = fopen_or_die(proc_stat, "r"); 2086 2087 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 2088 if (retval != 0) 2089 err(1, "%s: failed to parse format", proc_stat); 2090 2091 while (1) { 2092 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 2093 if (retval != 1) 2094 break; 2095 2096 retval = func(cpu_num); 2097 if (retval) { 2098 fclose(fp); 2099 return(retval); 2100 } 2101 } 2102 fclose(fp); 2103 return 0; 2104 } 2105 2106 void re_initialize(void) 2107 { 2108 free_all_buffers(); 2109 setup_all_buffers(); 2110 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2111 } 2112 2113 2114 /* 2115 * count_cpus() 2116 * remember the last one seen, it will be the max 2117 */ 2118 int count_cpus(int cpu) 2119 { 2120 if (topo.max_cpu_num < cpu) 2121 topo.max_cpu_num = cpu; 2122 2123 topo.num_cpus += 1; 2124 return 0; 2125 } 2126 int mark_cpu_present(int cpu) 2127 { 2128 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 2129 return 0; 2130 } 2131 2132 /* 2133 * snapshot_proc_interrupts() 2134 * 2135 * read and record summary of /proc/interrupts 2136 * 2137 * return 1 if config change requires a restart, else return 0 2138 */ 2139 int snapshot_proc_interrupts(void) 2140 { 2141 static FILE *fp; 2142 int column, retval; 2143 2144 if (fp == NULL) 2145 fp = fopen_or_die("/proc/interrupts", "r"); 2146 else 2147 rewind(fp); 2148 2149 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 2150 for (column = 0; column < topo.num_cpus; ++column) { 2151 int cpu_number; 2152 2153 retval = fscanf(fp, " CPU%d", &cpu_number); 2154 if (retval != 1) 2155 break; 2156 2157 if (cpu_number > topo.max_cpu_num) { 2158 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 2159 return 1; 2160 } 2161 2162 irq_column_2_cpu[column] = cpu_number; 2163 irqs_per_cpu[cpu_number] = 0; 2164 } 2165 2166 /* read /proc/interrupt count lines and sum up irqs per cpu */ 2167 while (1) { 2168 int column; 2169 char buf[64]; 2170 2171 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 2172 if (retval != 1) 2173 break; 2174 2175 /* read the count per cpu */ 2176 for (column = 0; column < topo.num_cpus; ++column) { 2177 2178 int cpu_number, irq_count; 2179 2180 retval = fscanf(fp, " %d", &irq_count); 2181 if (retval != 1) 2182 break; 2183 2184 cpu_number = irq_column_2_cpu[column]; 2185 irqs_per_cpu[cpu_number] += irq_count; 2186 2187 } 2188 2189 while (getc(fp) != '\n') 2190 ; /* flush interrupt description */ 2191 2192 } 2193 return 0; 2194 } 2195 /* 2196 * snapshot_gfx_rc6_ms() 2197 * 2198 * record snapshot of 2199 * /sys/class/drm/card0/power/rc6_residency_ms 2200 * 2201 * return 1 if config change requires a restart, else return 0 2202 */ 2203 int snapshot_gfx_rc6_ms(void) 2204 { 2205 FILE *fp; 2206 int retval; 2207 2208 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 2209 2210 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 2211 if (retval != 1) 2212 err(1, "GFX rc6"); 2213 2214 fclose(fp); 2215 2216 return 0; 2217 } 2218 /* 2219 * snapshot_gfx_mhz() 2220 * 2221 * record snapshot of 2222 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 2223 * 2224 * return 1 if config change requires a restart, else return 0 2225 */ 2226 int snapshot_gfx_mhz(void) 2227 { 2228 static FILE *fp; 2229 int retval; 2230 2231 if (fp == NULL) 2232 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 2233 else 2234 rewind(fp); 2235 2236 retval = fscanf(fp, "%d", &gfx_cur_mhz); 2237 if (retval != 1) 2238 err(1, "GFX MHz"); 2239 2240 return 0; 2241 } 2242 2243 /* 2244 * snapshot /proc and /sys files 2245 * 2246 * return 1 if configuration restart needed, else return 0 2247 */ 2248 int snapshot_proc_sysfs_files(void) 2249 { 2250 if (snapshot_proc_interrupts()) 2251 return 1; 2252 2253 if (DO_BIC(BIC_GFX_rc6)) 2254 snapshot_gfx_rc6_ms(); 2255 2256 if (DO_BIC(BIC_GFXMHz)) 2257 snapshot_gfx_mhz(); 2258 2259 return 0; 2260 } 2261 2262 void turbostat_loop() 2263 { 2264 int retval; 2265 int restarted = 0; 2266 2267 restart: 2268 restarted++; 2269 2270 snapshot_proc_sysfs_files(); 2271 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2272 if (retval < -1) { 2273 exit(retval); 2274 } else if (retval == -1) { 2275 if (restarted > 1) { 2276 exit(retval); 2277 } 2278 re_initialize(); 2279 goto restart; 2280 } 2281 restarted = 0; 2282 gettimeofday(&tv_even, (struct timezone *)NULL); 2283 2284 while (1) { 2285 if (for_all_proc_cpus(cpu_is_not_present)) { 2286 re_initialize(); 2287 goto restart; 2288 } 2289 nanosleep(&interval_ts, NULL); 2290 if (snapshot_proc_sysfs_files()) 2291 goto restart; 2292 retval = for_all_cpus(get_counters, ODD_COUNTERS); 2293 if (retval < -1) { 2294 exit(retval); 2295 } else if (retval == -1) { 2296 re_initialize(); 2297 goto restart; 2298 } 2299 gettimeofday(&tv_odd, (struct timezone *)NULL); 2300 timersub(&tv_odd, &tv_even, &tv_delta); 2301 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 2302 re_initialize(); 2303 goto restart; 2304 } 2305 compute_average(EVEN_COUNTERS); 2306 format_all_counters(EVEN_COUNTERS); 2307 flush_output_stdout(); 2308 nanosleep(&interval_ts, NULL); 2309 if (snapshot_proc_sysfs_files()) 2310 goto restart; 2311 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2312 if (retval < -1) { 2313 exit(retval); 2314 } else if (retval == -1) { 2315 re_initialize(); 2316 goto restart; 2317 } 2318 gettimeofday(&tv_even, (struct timezone *)NULL); 2319 timersub(&tv_even, &tv_odd, &tv_delta); 2320 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 2321 re_initialize(); 2322 goto restart; 2323 } 2324 compute_average(ODD_COUNTERS); 2325 format_all_counters(ODD_COUNTERS); 2326 flush_output_stdout(); 2327 } 2328 } 2329 2330 void check_dev_msr() 2331 { 2332 struct stat sb; 2333 char pathname[32]; 2334 2335 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 2336 if (stat(pathname, &sb)) 2337 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 2338 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 2339 } 2340 2341 void check_permissions() 2342 { 2343 struct __user_cap_header_struct cap_header_data; 2344 cap_user_header_t cap_header = &cap_header_data; 2345 struct __user_cap_data_struct cap_data_data; 2346 cap_user_data_t cap_data = &cap_data_data; 2347 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); 2348 int do_exit = 0; 2349 char pathname[32]; 2350 2351 /* check for CAP_SYS_RAWIO */ 2352 cap_header->pid = getpid(); 2353 cap_header->version = _LINUX_CAPABILITY_VERSION; 2354 if (capget(cap_header, cap_data) < 0) 2355 err(-6, "capget(2) failed"); 2356 2357 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { 2358 do_exit++; 2359 warnx("capget(CAP_SYS_RAWIO) failed," 2360 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 2361 } 2362 2363 /* test file permissions */ 2364 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 2365 if (euidaccess(pathname, R_OK)) { 2366 do_exit++; 2367 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 2368 } 2369 2370 /* if all else fails, thell them to be root */ 2371 if (do_exit) 2372 if (getuid() != 0) 2373 warnx("... or simply run as root"); 2374 2375 if (do_exit) 2376 exit(-6); 2377 } 2378 2379 /* 2380 * NHM adds support for additional MSRs: 2381 * 2382 * MSR_SMI_COUNT 0x00000034 2383 * 2384 * MSR_PLATFORM_INFO 0x000000ce 2385 * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 2386 * 2387 * MSR_PKG_C3_RESIDENCY 0x000003f8 2388 * MSR_PKG_C6_RESIDENCY 0x000003f9 2389 * MSR_CORE_C3_RESIDENCY 0x000003fc 2390 * MSR_CORE_C6_RESIDENCY 0x000003fd 2391 * 2392 * Side effect: 2393 * sets global pkg_cstate_limit to decode MSR_NHM_SNB_PKG_CST_CFG_CTL 2394 */ 2395 int probe_nhm_msrs(unsigned int family, unsigned int model) 2396 { 2397 unsigned long long msr; 2398 unsigned int base_ratio; 2399 int *pkg_cstate_limits; 2400 2401 if (!genuine_intel) 2402 return 0; 2403 2404 if (family != 6) 2405 return 0; 2406 2407 bclk = discover_bclk(family, model); 2408 2409 switch (model) { 2410 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 2411 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 2412 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 2413 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 2414 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 2415 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 2416 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 2417 pkg_cstate_limits = nhm_pkg_cstate_limits; 2418 break; 2419 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 2420 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 2421 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 2422 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 2423 pkg_cstate_limits = snb_pkg_cstate_limits; 2424 break; 2425 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 2426 case INTEL_FAM6_HASWELL_X: /* HSX */ 2427 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 2428 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 2429 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 2430 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 2431 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2432 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2433 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 2434 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 2435 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 2436 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 2437 pkg_cstate_limits = hsw_pkg_cstate_limits; 2438 break; 2439 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 2440 pkg_cstate_limits = skx_pkg_cstate_limits; 2441 break; 2442 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 2443 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 2444 pkg_cstate_limits = slv_pkg_cstate_limits; 2445 break; 2446 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 2447 pkg_cstate_limits = amt_pkg_cstate_limits; 2448 break; 2449 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 2450 case INTEL_FAM6_XEON_PHI_KNM: 2451 pkg_cstate_limits = phi_pkg_cstate_limits; 2452 break; 2453 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 2454 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 2455 pkg_cstate_limits = bxt_pkg_cstate_limits; 2456 break; 2457 default: 2458 return 0; 2459 } 2460 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); 2461 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 2462 2463 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2464 base_ratio = (msr >> 8) & 0xFF; 2465 2466 base_hz = base_ratio * bclk * 1000000; 2467 has_base_hz = 1; 2468 return 1; 2469 } 2470 int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model) 2471 { 2472 switch (model) { 2473 /* Nehalem compatible, but do not include turbo-ratio limit support */ 2474 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 2475 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 2476 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 2477 case INTEL_FAM6_XEON_PHI_KNM: 2478 return 0; 2479 default: 2480 return 1; 2481 } 2482 } 2483 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 2484 { 2485 if (!genuine_intel) 2486 return 0; 2487 2488 if (family != 6) 2489 return 0; 2490 2491 switch (model) { 2492 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 2493 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 2494 return 1; 2495 default: 2496 return 0; 2497 } 2498 } 2499 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 2500 { 2501 if (!genuine_intel) 2502 return 0; 2503 2504 if (family != 6) 2505 return 0; 2506 2507 switch (model) { 2508 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 2509 return 1; 2510 default: 2511 return 0; 2512 } 2513 } 2514 2515 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 2516 { 2517 if (!genuine_intel) 2518 return 0; 2519 2520 if (family != 6) 2521 return 0; 2522 2523 switch (model) { 2524 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 2525 case INTEL_FAM6_XEON_PHI_KNM: 2526 return 1; 2527 default: 2528 return 0; 2529 } 2530 } 2531 int has_config_tdp(unsigned int family, unsigned int model) 2532 { 2533 if (!genuine_intel) 2534 return 0; 2535 2536 if (family != 6) 2537 return 0; 2538 2539 switch (model) { 2540 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 2541 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 2542 case INTEL_FAM6_HASWELL_X: /* HSX */ 2543 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 2544 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 2545 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 2546 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 2547 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2548 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2549 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 2550 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 2551 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 2552 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 2553 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 2554 2555 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 2556 case INTEL_FAM6_XEON_PHI_KNM: 2557 return 1; 2558 default: 2559 return 0; 2560 } 2561 } 2562 2563 static void 2564 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 2565 { 2566 if (!do_nhm_platform_info) 2567 return; 2568 2569 dump_nhm_platform_info(); 2570 2571 if (has_hsw_turbo_ratio_limit(family, model)) 2572 dump_hsw_turbo_ratio_limits(); 2573 2574 if (has_ivt_turbo_ratio_limit(family, model)) 2575 dump_ivt_turbo_ratio_limits(); 2576 2577 if (has_nhm_turbo_ratio_limit(family, model)) 2578 dump_nhm_turbo_ratio_limits(); 2579 2580 if (has_knl_turbo_ratio_limit(family, model)) 2581 dump_knl_turbo_ratio_limits(); 2582 2583 if (has_config_tdp(family, model)) 2584 dump_config_tdp(); 2585 2586 dump_nhm_cst_cfg(); 2587 } 2588 2589 2590 /* 2591 * print_epb() 2592 * Decode the ENERGY_PERF_BIAS MSR 2593 */ 2594 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2595 { 2596 unsigned long long msr; 2597 char *epb_string; 2598 int cpu; 2599 2600 if (!has_epb) 2601 return 0; 2602 2603 cpu = t->cpu_id; 2604 2605 /* EPB is per-package */ 2606 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2607 return 0; 2608 2609 if (cpu_migrate(cpu)) { 2610 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2611 return -1; 2612 } 2613 2614 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) 2615 return 0; 2616 2617 switch (msr & 0xF) { 2618 case ENERGY_PERF_BIAS_PERFORMANCE: 2619 epb_string = "performance"; 2620 break; 2621 case ENERGY_PERF_BIAS_NORMAL: 2622 epb_string = "balanced"; 2623 break; 2624 case ENERGY_PERF_BIAS_POWERSAVE: 2625 epb_string = "powersave"; 2626 break; 2627 default: 2628 epb_string = "custom"; 2629 break; 2630 } 2631 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); 2632 2633 return 0; 2634 } 2635 /* 2636 * print_hwp() 2637 * Decode the MSR_HWP_CAPABILITIES 2638 */ 2639 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2640 { 2641 unsigned long long msr; 2642 int cpu; 2643 2644 if (!has_hwp) 2645 return 0; 2646 2647 cpu = t->cpu_id; 2648 2649 /* MSR_HWP_CAPABILITIES is per-package */ 2650 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2651 return 0; 2652 2653 if (cpu_migrate(cpu)) { 2654 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2655 return -1; 2656 } 2657 2658 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 2659 return 0; 2660 2661 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 2662 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 2663 2664 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 2665 if ((msr & (1 << 0)) == 0) 2666 return 0; 2667 2668 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 2669 return 0; 2670 2671 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 2672 "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n", 2673 cpu, msr, 2674 (unsigned int)HWP_HIGHEST_PERF(msr), 2675 (unsigned int)HWP_GUARANTEED_PERF(msr), 2676 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 2677 (unsigned int)HWP_LOWEST_PERF(msr)); 2678 2679 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 2680 return 0; 2681 2682 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 2683 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n", 2684 cpu, msr, 2685 (unsigned int)(((msr) >> 0) & 0xff), 2686 (unsigned int)(((msr) >> 8) & 0xff), 2687 (unsigned int)(((msr) >> 16) & 0xff), 2688 (unsigned int)(((msr) >> 24) & 0xff), 2689 (unsigned int)(((msr) >> 32) & 0xff3), 2690 (unsigned int)(((msr) >> 42) & 0x1)); 2691 2692 if (has_hwp_pkg) { 2693 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 2694 return 0; 2695 2696 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 2697 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n", 2698 cpu, msr, 2699 (unsigned int)(((msr) >> 0) & 0xff), 2700 (unsigned int)(((msr) >> 8) & 0xff), 2701 (unsigned int)(((msr) >> 16) & 0xff), 2702 (unsigned int)(((msr) >> 24) & 0xff), 2703 (unsigned int)(((msr) >> 32) & 0xff3)); 2704 } 2705 if (has_hwp_notify) { 2706 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 2707 return 0; 2708 2709 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 2710 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 2711 cpu, msr, 2712 ((msr) & 0x1) ? "EN" : "Dis", 2713 ((msr) & 0x2) ? "EN" : "Dis"); 2714 } 2715 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 2716 return 0; 2717 2718 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 2719 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 2720 cpu, msr, 2721 ((msr) & 0x1) ? "" : "No-", 2722 ((msr) & 0x2) ? "" : "No-"); 2723 2724 return 0; 2725 } 2726 2727 /* 2728 * print_perf_limit() 2729 */ 2730 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2731 { 2732 unsigned long long msr; 2733 int cpu; 2734 2735 cpu = t->cpu_id; 2736 2737 /* per-package */ 2738 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2739 return 0; 2740 2741 if (cpu_migrate(cpu)) { 2742 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2743 return -1; 2744 } 2745 2746 if (do_core_perf_limit_reasons) { 2747 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 2748 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2749 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 2750 (msr & 1 << 15) ? "bit15, " : "", 2751 (msr & 1 << 14) ? "bit14, " : "", 2752 (msr & 1 << 13) ? "Transitions, " : "", 2753 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 2754 (msr & 1 << 11) ? "PkgPwrL2, " : "", 2755 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2756 (msr & 1 << 9) ? "CorePwr, " : "", 2757 (msr & 1 << 8) ? "Amps, " : "", 2758 (msr & 1 << 6) ? "VR-Therm, " : "", 2759 (msr & 1 << 5) ? "Auto-HWP, " : "", 2760 (msr & 1 << 4) ? "Graphics, " : "", 2761 (msr & 1 << 2) ? "bit2, " : "", 2762 (msr & 1 << 1) ? "ThermStatus, " : "", 2763 (msr & 1 << 0) ? "PROCHOT, " : ""); 2764 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 2765 (msr & 1 << 31) ? "bit31, " : "", 2766 (msr & 1 << 30) ? "bit30, " : "", 2767 (msr & 1 << 29) ? "Transitions, " : "", 2768 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 2769 (msr & 1 << 27) ? "PkgPwrL2, " : "", 2770 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2771 (msr & 1 << 25) ? "CorePwr, " : "", 2772 (msr & 1 << 24) ? "Amps, " : "", 2773 (msr & 1 << 22) ? "VR-Therm, " : "", 2774 (msr & 1 << 21) ? "Auto-HWP, " : "", 2775 (msr & 1 << 20) ? "Graphics, " : "", 2776 (msr & 1 << 18) ? "bit18, " : "", 2777 (msr & 1 << 17) ? "ThermStatus, " : "", 2778 (msr & 1 << 16) ? "PROCHOT, " : ""); 2779 2780 } 2781 if (do_gfx_perf_limit_reasons) { 2782 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 2783 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2784 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 2785 (msr & 1 << 0) ? "PROCHOT, " : "", 2786 (msr & 1 << 1) ? "ThermStatus, " : "", 2787 (msr & 1 << 4) ? "Graphics, " : "", 2788 (msr & 1 << 6) ? "VR-Therm, " : "", 2789 (msr & 1 << 8) ? "Amps, " : "", 2790 (msr & 1 << 9) ? "GFXPwr, " : "", 2791 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2792 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 2793 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 2794 (msr & 1 << 16) ? "PROCHOT, " : "", 2795 (msr & 1 << 17) ? "ThermStatus, " : "", 2796 (msr & 1 << 20) ? "Graphics, " : "", 2797 (msr & 1 << 22) ? "VR-Therm, " : "", 2798 (msr & 1 << 24) ? "Amps, " : "", 2799 (msr & 1 << 25) ? "GFXPwr, " : "", 2800 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2801 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 2802 } 2803 if (do_ring_perf_limit_reasons) { 2804 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 2805 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2806 fprintf(outf, " (Active: %s%s%s%s%s%s)", 2807 (msr & 1 << 0) ? "PROCHOT, " : "", 2808 (msr & 1 << 1) ? "ThermStatus, " : "", 2809 (msr & 1 << 6) ? "VR-Therm, " : "", 2810 (msr & 1 << 8) ? "Amps, " : "", 2811 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2812 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 2813 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 2814 (msr & 1 << 16) ? "PROCHOT, " : "", 2815 (msr & 1 << 17) ? "ThermStatus, " : "", 2816 (msr & 1 << 22) ? "VR-Therm, " : "", 2817 (msr & 1 << 24) ? "Amps, " : "", 2818 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2819 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 2820 } 2821 return 0; 2822 } 2823 2824 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 2825 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 2826 2827 double get_tdp(unsigned int model) 2828 { 2829 unsigned long long msr; 2830 2831 if (do_rapl & RAPL_PKG_POWER_INFO) 2832 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 2833 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 2834 2835 switch (model) { 2836 case INTEL_FAM6_ATOM_SILVERMONT1: 2837 case INTEL_FAM6_ATOM_SILVERMONT2: 2838 return 30.0; 2839 default: 2840 return 135.0; 2841 } 2842 } 2843 2844 /* 2845 * rapl_dram_energy_units_probe() 2846 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 2847 */ 2848 static double 2849 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 2850 { 2851 /* only called for genuine_intel, family 6 */ 2852 2853 switch (model) { 2854 case INTEL_FAM6_HASWELL_X: /* HSX */ 2855 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2856 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2857 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 2858 case INTEL_FAM6_XEON_PHI_KNM: 2859 return (rapl_dram_energy_units = 15.3 / 1000000); 2860 default: 2861 return (rapl_energy_units); 2862 } 2863 } 2864 2865 2866 /* 2867 * rapl_probe() 2868 * 2869 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 2870 */ 2871 void rapl_probe(unsigned int family, unsigned int model) 2872 { 2873 unsigned long long msr; 2874 unsigned int time_unit; 2875 double tdp; 2876 2877 if (!genuine_intel) 2878 return; 2879 2880 if (family != 6) 2881 return; 2882 2883 switch (model) { 2884 case INTEL_FAM6_SANDYBRIDGE: 2885 case INTEL_FAM6_IVYBRIDGE: 2886 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 2887 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 2888 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 2889 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 2890 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 2891 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 2892 if (rapl_joules) { 2893 BIC_PRESENT(BIC_Pkg_J); 2894 BIC_PRESENT(BIC_Cor_J); 2895 BIC_PRESENT(BIC_GFX_J); 2896 } else { 2897 BIC_PRESENT(BIC_PkgWatt); 2898 BIC_PRESENT(BIC_CorWatt); 2899 BIC_PRESENT(BIC_GFXWatt); 2900 } 2901 break; 2902 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 2903 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 2904 if (rapl_joules) 2905 BIC_PRESENT(BIC_Pkg_J); 2906 else 2907 BIC_PRESENT(BIC_PkgWatt); 2908 break; 2909 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 2910 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 2911 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 2912 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 2913 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 2914 BIC_PRESENT(BIC_PKG__); 2915 BIC_PRESENT(BIC_RAM__); 2916 if (rapl_joules) { 2917 BIC_PRESENT(BIC_Pkg_J); 2918 BIC_PRESENT(BIC_Cor_J); 2919 BIC_PRESENT(BIC_RAM_J); 2920 } else { 2921 BIC_PRESENT(BIC_PkgWatt); 2922 BIC_PRESENT(BIC_CorWatt); 2923 BIC_PRESENT(BIC_RAMWatt); 2924 } 2925 break; 2926 case INTEL_FAM6_HASWELL_X: /* HSX */ 2927 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2928 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2929 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 2930 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 2931 case INTEL_FAM6_XEON_PHI_KNM: 2932 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 2933 BIC_PRESENT(BIC_PKG__); 2934 BIC_PRESENT(BIC_RAM__); 2935 if (rapl_joules) { 2936 BIC_PRESENT(BIC_Pkg_J); 2937 BIC_PRESENT(BIC_RAM_J); 2938 } else { 2939 BIC_PRESENT(BIC_PkgWatt); 2940 BIC_PRESENT(BIC_RAMWatt); 2941 } 2942 break; 2943 case INTEL_FAM6_SANDYBRIDGE_X: 2944 case INTEL_FAM6_IVYBRIDGE_X: 2945 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 2946 BIC_PRESENT(BIC_PKG__); 2947 BIC_PRESENT(BIC_RAM__); 2948 if (rapl_joules) { 2949 BIC_PRESENT(BIC_Pkg_J); 2950 BIC_PRESENT(BIC_Cor_J); 2951 BIC_PRESENT(BIC_RAM_J); 2952 } else { 2953 BIC_PRESENT(BIC_PkgWatt); 2954 BIC_PRESENT(BIC_CorWatt); 2955 BIC_PRESENT(BIC_RAMWatt); 2956 } 2957 break; 2958 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 2959 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 2960 do_rapl = RAPL_PKG | RAPL_CORES; 2961 if (rapl_joules) { 2962 BIC_PRESENT(BIC_Pkg_J); 2963 BIC_PRESENT(BIC_Cor_J); 2964 } else { 2965 BIC_PRESENT(BIC_PkgWatt); 2966 BIC_PRESENT(BIC_CorWatt); 2967 } 2968 break; 2969 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 2970 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 2971 BIC_PRESENT(BIC_PKG__); 2972 BIC_PRESENT(BIC_RAM__); 2973 if (rapl_joules) { 2974 BIC_PRESENT(BIC_Pkg_J); 2975 BIC_PRESENT(BIC_Cor_J); 2976 BIC_PRESENT(BIC_RAM_J); 2977 } else { 2978 BIC_PRESENT(BIC_PkgWatt); 2979 BIC_PRESENT(BIC_CorWatt); 2980 BIC_PRESENT(BIC_RAMWatt); 2981 } 2982 break; 2983 default: 2984 return; 2985 } 2986 2987 /* units on package 0, verify later other packages match */ 2988 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 2989 return; 2990 2991 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 2992 if (model == INTEL_FAM6_ATOM_SILVERMONT1) 2993 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 2994 else 2995 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 2996 2997 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 2998 2999 time_unit = msr >> 16 & 0xF; 3000 if (time_unit == 0) 3001 time_unit = 0xA; 3002 3003 rapl_time_units = 1.0 / (1 << (time_unit)); 3004 3005 tdp = get_tdp(model); 3006 3007 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 3008 if (debug) 3009 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 3010 3011 return; 3012 } 3013 3014 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 3015 { 3016 if (!genuine_intel) 3017 return; 3018 3019 if (family != 6) 3020 return; 3021 3022 switch (model) { 3023 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3024 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3025 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3026 do_gfx_perf_limit_reasons = 1; 3027 case INTEL_FAM6_HASWELL_X: /* HSX */ 3028 do_core_perf_limit_reasons = 1; 3029 do_ring_perf_limit_reasons = 1; 3030 default: 3031 return; 3032 } 3033 } 3034 3035 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3036 { 3037 unsigned long long msr; 3038 unsigned int dts; 3039 int cpu; 3040 3041 if (!(do_dts || do_ptm)) 3042 return 0; 3043 3044 cpu = t->cpu_id; 3045 3046 /* DTS is per-core, no need to print for each thread */ 3047 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 3048 return 0; 3049 3050 if (cpu_migrate(cpu)) { 3051 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3052 return -1; 3053 } 3054 3055 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 3056 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 3057 return 0; 3058 3059 dts = (msr >> 16) & 0x7F; 3060 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 3061 cpu, msr, tcc_activation_temp - dts); 3062 3063 #ifdef THERM_DEBUG 3064 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 3065 return 0; 3066 3067 dts = (msr >> 16) & 0x7F; 3068 dts2 = (msr >> 8) & 0x7F; 3069 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 3070 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 3071 #endif 3072 } 3073 3074 3075 if (do_dts) { 3076 unsigned int resolution; 3077 3078 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 3079 return 0; 3080 3081 dts = (msr >> 16) & 0x7F; 3082 resolution = (msr >> 27) & 0xF; 3083 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 3084 cpu, msr, tcc_activation_temp - dts, resolution); 3085 3086 #ifdef THERM_DEBUG 3087 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 3088 return 0; 3089 3090 dts = (msr >> 16) & 0x7F; 3091 dts2 = (msr >> 8) & 0x7F; 3092 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 3093 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 3094 #endif 3095 } 3096 3097 return 0; 3098 } 3099 3100 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 3101 { 3102 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 3103 cpu, label, 3104 ((msr >> 15) & 1) ? "EN" : "DIS", 3105 ((msr >> 0) & 0x7FFF) * rapl_power_units, 3106 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 3107 (((msr >> 16) & 1) ? "EN" : "DIS")); 3108 3109 return; 3110 } 3111 3112 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3113 { 3114 unsigned long long msr; 3115 int cpu; 3116 3117 if (!do_rapl) 3118 return 0; 3119 3120 /* RAPL counters are per package, so print only for 1st thread/package */ 3121 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3122 return 0; 3123 3124 cpu = t->cpu_id; 3125 if (cpu_migrate(cpu)) { 3126 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3127 return -1; 3128 } 3129 3130 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 3131 return -1; 3132 3133 if (debug) { 3134 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx " 3135 "(%f Watts, %f Joules, %f sec.)\n", cpu, msr, 3136 rapl_power_units, rapl_energy_units, rapl_time_units); 3137 } 3138 if (do_rapl & RAPL_PKG_POWER_INFO) { 3139 3140 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 3141 return -5; 3142 3143 3144 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 3145 cpu, msr, 3146 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3147 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3148 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3149 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 3150 3151 } 3152 if (do_rapl & RAPL_PKG) { 3153 3154 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 3155 return -9; 3156 3157 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 3158 cpu, msr, (msr >> 63) & 1 ? "": "UN"); 3159 3160 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 3161 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 3162 cpu, 3163 ((msr >> 47) & 1) ? "EN" : "DIS", 3164 ((msr >> 32) & 0x7FFF) * rapl_power_units, 3165 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 3166 ((msr >> 48) & 1) ? "EN" : "DIS"); 3167 } 3168 3169 if (do_rapl & RAPL_DRAM_POWER_INFO) { 3170 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 3171 return -6; 3172 3173 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 3174 cpu, msr, 3175 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3176 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3177 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3178 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 3179 } 3180 if (do_rapl & RAPL_DRAM) { 3181 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 3182 return -9; 3183 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 3184 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 3185 3186 print_power_limit_msr(cpu, msr, "DRAM Limit"); 3187 } 3188 if (do_rapl & RAPL_CORE_POLICY) { 3189 if (debug) { 3190 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 3191 return -7; 3192 3193 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 3194 } 3195 } 3196 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 3197 if (debug) { 3198 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 3199 return -9; 3200 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 3201 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 3202 print_power_limit_msr(cpu, msr, "Cores Limit"); 3203 } 3204 } 3205 if (do_rapl & RAPL_GFX) { 3206 if (debug) { 3207 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 3208 return -8; 3209 3210 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 3211 3212 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 3213 return -9; 3214 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 3215 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 3216 print_power_limit_msr(cpu, msr, "GFX Limit"); 3217 } 3218 } 3219 return 0; 3220 } 3221 3222 /* 3223 * SNB adds support for additional MSRs: 3224 * 3225 * MSR_PKG_C7_RESIDENCY 0x000003fa 3226 * MSR_CORE_C7_RESIDENCY 0x000003fe 3227 * MSR_PKG_C2_RESIDENCY 0x0000060d 3228 */ 3229 3230 int has_snb_msrs(unsigned int family, unsigned int model) 3231 { 3232 if (!genuine_intel) 3233 return 0; 3234 3235 switch (model) { 3236 case INTEL_FAM6_SANDYBRIDGE: 3237 case INTEL_FAM6_SANDYBRIDGE_X: 3238 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3239 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3240 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3241 case INTEL_FAM6_HASWELL_X: /* HSW */ 3242 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3243 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3244 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3245 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3246 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3247 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3248 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3249 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3250 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3251 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3252 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3253 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3254 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3255 return 1; 3256 } 3257 return 0; 3258 } 3259 3260 /* 3261 * HSW adds support for additional MSRs: 3262 * 3263 * MSR_PKG_C8_RESIDENCY 0x00000630 3264 * MSR_PKG_C9_RESIDENCY 0x00000631 3265 * MSR_PKG_C10_RESIDENCY 0x00000632 3266 * 3267 * MSR_PKGC8_IRTL 0x00000633 3268 * MSR_PKGC9_IRTL 0x00000634 3269 * MSR_PKGC10_IRTL 0x00000635 3270 * 3271 */ 3272 int has_hsw_msrs(unsigned int family, unsigned int model) 3273 { 3274 if (!genuine_intel) 3275 return 0; 3276 3277 switch (model) { 3278 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3279 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3280 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3281 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3282 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3283 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3284 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3285 return 1; 3286 } 3287 return 0; 3288 } 3289 3290 /* 3291 * SKL adds support for additional MSRS: 3292 * 3293 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 3294 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 3295 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 3296 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 3297 */ 3298 int has_skl_msrs(unsigned int family, unsigned int model) 3299 { 3300 if (!genuine_intel) 3301 return 0; 3302 3303 switch (model) { 3304 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3305 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3306 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3307 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3308 return 1; 3309 } 3310 return 0; 3311 } 3312 3313 3314 3315 int is_slm(unsigned int family, unsigned int model) 3316 { 3317 if (!genuine_intel) 3318 return 0; 3319 switch (model) { 3320 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 3321 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 3322 return 1; 3323 } 3324 return 0; 3325 } 3326 3327 int is_knl(unsigned int family, unsigned int model) 3328 { 3329 if (!genuine_intel) 3330 return 0; 3331 switch (model) { 3332 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3333 case INTEL_FAM6_XEON_PHI_KNM: 3334 return 1; 3335 } 3336 return 0; 3337 } 3338 3339 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 3340 { 3341 if (is_knl(family, model)) 3342 return 1024; 3343 return 1; 3344 } 3345 3346 #define SLM_BCLK_FREQS 5 3347 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 3348 3349 double slm_bclk(void) 3350 { 3351 unsigned long long msr = 3; 3352 unsigned int i; 3353 double freq; 3354 3355 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 3356 fprintf(outf, "SLM BCLK: unknown\n"); 3357 3358 i = msr & 0xf; 3359 if (i >= SLM_BCLK_FREQS) { 3360 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 3361 i = 3; 3362 } 3363 freq = slm_freq_table[i]; 3364 3365 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 3366 3367 return freq; 3368 } 3369 3370 double discover_bclk(unsigned int family, unsigned int model) 3371 { 3372 if (has_snb_msrs(family, model) || is_knl(family, model)) 3373 return 100.00; 3374 else if (is_slm(family, model)) 3375 return slm_bclk(); 3376 else 3377 return 133.33; 3378 } 3379 3380 /* 3381 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 3382 * the Thermal Control Circuit (TCC) activates. 3383 * This is usually equal to tjMax. 3384 * 3385 * Older processors do not have this MSR, so there we guess, 3386 * but also allow cmdline over-ride with -T. 3387 * 3388 * Several MSR temperature values are in units of degrees-C 3389 * below this value, including the Digital Thermal Sensor (DTS), 3390 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 3391 */ 3392 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3393 { 3394 unsigned long long msr; 3395 unsigned int target_c_local; 3396 int cpu; 3397 3398 /* tcc_activation_temp is used only for dts or ptm */ 3399 if (!(do_dts || do_ptm)) 3400 return 0; 3401 3402 /* this is a per-package concept */ 3403 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3404 return 0; 3405 3406 cpu = t->cpu_id; 3407 if (cpu_migrate(cpu)) { 3408 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3409 return -1; 3410 } 3411 3412 if (tcc_activation_temp_override != 0) { 3413 tcc_activation_temp = tcc_activation_temp_override; 3414 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 3415 cpu, tcc_activation_temp); 3416 return 0; 3417 } 3418 3419 /* Temperature Target MSR is Nehalem and newer only */ 3420 if (!do_nhm_platform_info) 3421 goto guess; 3422 3423 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 3424 goto guess; 3425 3426 target_c_local = (msr >> 16) & 0xFF; 3427 3428 if (debug) 3429 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 3430 cpu, msr, target_c_local); 3431 3432 if (!target_c_local) 3433 goto guess; 3434 3435 tcc_activation_temp = target_c_local; 3436 3437 return 0; 3438 3439 guess: 3440 tcc_activation_temp = TJMAX_DEFAULT; 3441 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 3442 cpu, tcc_activation_temp); 3443 3444 return 0; 3445 } 3446 3447 void decode_feature_control_msr(void) 3448 { 3449 unsigned long long msr; 3450 3451 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) 3452 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 3453 base_cpu, msr, 3454 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", 3455 msr & (1 << 18) ? "SGX" : ""); 3456 } 3457 3458 void decode_misc_enable_msr(void) 3459 { 3460 unsigned long long msr; 3461 3462 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 3463 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n", 3464 base_cpu, msr, 3465 msr & (1 << 3) ? "TCC" : "", 3466 msr & (1 << 16) ? "EIST" : "", 3467 msr & (1 << 18) ? "MONITOR" : ""); 3468 } 3469 3470 /* 3471 * Decode MSR_MISC_PWR_MGMT 3472 * 3473 * Decode the bits according to the Nehalem documentation 3474 * bit[0] seems to continue to have same meaning going forward 3475 * bit[1] less so... 3476 */ 3477 void decode_misc_pwr_mgmt_msr(void) 3478 { 3479 unsigned long long msr; 3480 3481 if (!do_nhm_platform_info) 3482 return; 3483 3484 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 3485 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 3486 base_cpu, msr, 3487 msr & (1 << 0) ? "DIS" : "EN", 3488 msr & (1 << 1) ? "EN" : "DIS", 3489 msr & (1 << 8) ? "EN" : "DIS"); 3490 } 3491 3492 void process_cpuid() 3493 { 3494 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level; 3495 unsigned int fms, family, model, stepping; 3496 3497 eax = ebx = ecx = edx = 0; 3498 3499 __cpuid(0, max_level, ebx, ecx, edx); 3500 3501 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) 3502 genuine_intel = 1; 3503 3504 if (debug) 3505 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 3506 (char *)&ebx, (char *)&edx, (char *)&ecx); 3507 3508 __cpuid(1, fms, ebx, ecx, edx); 3509 family = (fms >> 8) & 0xf; 3510 model = (fms >> 4) & 0xf; 3511 stepping = fms & 0xf; 3512 if (family == 6 || family == 0xf) 3513 model += ((fms >> 16) & 0xf) << 4; 3514 3515 if (debug) { 3516 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 3517 max_level, family, model, stepping, family, model, stepping); 3518 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n", 3519 ecx & (1 << 0) ? "SSE3" : "-", 3520 ecx & (1 << 3) ? "MONITOR" : "-", 3521 ecx & (1 << 6) ? "SMX" : "-", 3522 ecx & (1 << 7) ? "EIST" : "-", 3523 ecx & (1 << 8) ? "TM2" : "-", 3524 edx & (1 << 4) ? "TSC" : "-", 3525 edx & (1 << 5) ? "MSR" : "-", 3526 edx & (1 << 22) ? "ACPI-TM" : "-", 3527 edx & (1 << 29) ? "TM" : "-"); 3528 } 3529 3530 if (!(edx & (1 << 5))) 3531 errx(1, "CPUID: no MSR"); 3532 3533 /* 3534 * check max extended function levels of CPUID. 3535 * This is needed to check for invariant TSC. 3536 * This check is valid for both Intel and AMD. 3537 */ 3538 ebx = ecx = edx = 0; 3539 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 3540 3541 if (max_extended_level >= 0x80000007) { 3542 3543 /* 3544 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 3545 * this check is valid for both Intel and AMD 3546 */ 3547 __cpuid(0x80000007, eax, ebx, ecx, edx); 3548 has_invariant_tsc = edx & (1 << 8); 3549 } 3550 3551 /* 3552 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 3553 * this check is valid for both Intel and AMD 3554 */ 3555 3556 __cpuid(0x6, eax, ebx, ecx, edx); 3557 has_aperf = ecx & (1 << 0); 3558 if (has_aperf) { 3559 BIC_PRESENT(BIC_Avg_MHz); 3560 BIC_PRESENT(BIC_Busy); 3561 BIC_PRESENT(BIC_Bzy_MHz); 3562 } 3563 do_dts = eax & (1 << 0); 3564 if (do_dts) 3565 BIC_PRESENT(BIC_CoreTmp); 3566 do_ptm = eax & (1 << 6); 3567 if (do_ptm) 3568 BIC_PRESENT(BIC_PkgTmp); 3569 has_hwp = eax & (1 << 7); 3570 has_hwp_notify = eax & (1 << 8); 3571 has_hwp_activity_window = eax & (1 << 9); 3572 has_hwp_epp = eax & (1 << 10); 3573 has_hwp_pkg = eax & (1 << 11); 3574 has_epb = ecx & (1 << 3); 3575 3576 if (debug) 3577 fprintf(outf, "CPUID(6): %sAPERF, %sDTS, %sPTM, %sHWP, " 3578 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 3579 has_aperf ? "" : "No-", 3580 do_dts ? "" : "No-", 3581 do_ptm ? "" : "No-", 3582 has_hwp ? "" : "No-", 3583 has_hwp_notify ? "" : "No-", 3584 has_hwp_activity_window ? "" : "No-", 3585 has_hwp_epp ? "" : "No-", 3586 has_hwp_pkg ? "" : "No-", 3587 has_epb ? "" : "No-"); 3588 3589 if (debug) 3590 decode_misc_enable_msr(); 3591 3592 if (max_level >= 0x7 && debug) { 3593 int has_sgx; 3594 3595 ecx = 0; 3596 3597 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 3598 3599 has_sgx = ebx & (1 << 2); 3600 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 3601 3602 if (has_sgx) 3603 decode_feature_control_msr(); 3604 } 3605 3606 if (max_level >= 0x15) { 3607 unsigned int eax_crystal; 3608 unsigned int ebx_tsc; 3609 3610 /* 3611 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 3612 */ 3613 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 3614 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 3615 3616 if (ebx_tsc != 0) { 3617 3618 if (debug && (ebx != 0)) 3619 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 3620 eax_crystal, ebx_tsc, crystal_hz); 3621 3622 if (crystal_hz == 0) 3623 switch(model) { 3624 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3625 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3626 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3627 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3628 crystal_hz = 24000000; /* 24.0 MHz */ 3629 break; 3630 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3631 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3632 crystal_hz = 25000000; /* 25.0 MHz */ 3633 break; 3634 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3635 crystal_hz = 19200000; /* 19.2 MHz */ 3636 break; 3637 default: 3638 crystal_hz = 0; 3639 } 3640 3641 if (crystal_hz) { 3642 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 3643 if (debug) 3644 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 3645 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 3646 } 3647 } 3648 } 3649 if (max_level >= 0x16) { 3650 unsigned int base_mhz, max_mhz, bus_mhz, edx; 3651 3652 /* 3653 * CPUID 16H Base MHz, Max MHz, Bus MHz 3654 */ 3655 base_mhz = max_mhz = bus_mhz = edx = 0; 3656 3657 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 3658 if (debug) 3659 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 3660 base_mhz, max_mhz, bus_mhz); 3661 } 3662 3663 if (has_aperf) 3664 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 3665 3666 BIC_PRESENT(BIC_IRQ); 3667 BIC_PRESENT(BIC_TSC_MHz); 3668 3669 if (probe_nhm_msrs(family, model)) { 3670 do_nhm_platform_info = 1; 3671 BIC_PRESENT(BIC_CPU_c1); 3672 BIC_PRESENT(BIC_CPU_c3); 3673 BIC_PRESENT(BIC_CPU_c6); 3674 BIC_PRESENT(BIC_SMI); 3675 } 3676 do_snb_cstates = has_snb_msrs(family, model); 3677 3678 if (do_snb_cstates) 3679 BIC_PRESENT(BIC_CPU_c7); 3680 3681 do_irtl_snb = has_snb_msrs(family, model); 3682 do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2); 3683 do_pc3 = (pkg_cstate_limit >= PCL__3); 3684 do_pc6 = (pkg_cstate_limit >= PCL__6); 3685 do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7); 3686 do_c8_c9_c10 = has_hsw_msrs(family, model); 3687 do_irtl_hsw = has_hsw_msrs(family, model); 3688 do_skl_residency = has_skl_msrs(family, model); 3689 do_slm_cstates = is_slm(family, model); 3690 do_knl_cstates = is_knl(family, model); 3691 3692 if (debug) 3693 decode_misc_pwr_mgmt_msr(); 3694 3695 rapl_probe(family, model); 3696 perf_limit_reasons_probe(family, model); 3697 3698 if (debug) 3699 dump_cstate_pstate_config_info(family, model); 3700 3701 if (has_skl_msrs(family, model)) 3702 calculate_tsc_tweak(); 3703 3704 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 3705 BIC_PRESENT(BIC_GFX_rc6); 3706 3707 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 3708 BIC_PRESENT(BIC_GFXMHz); 3709 3710 return; 3711 } 3712 3713 void help() 3714 { 3715 fprintf(outf, 3716 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 3717 "\n" 3718 "Turbostat forks the specified COMMAND and prints statistics\n" 3719 "when COMMAND completes.\n" 3720 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 3721 "to print statistics, until interrupted.\n" 3722 "--add add a counter\n" 3723 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 3724 "--debug run in \"debug\" mode\n" 3725 "--interval sec Override default 5-second measurement interval\n" 3726 "--help print this help message\n" 3727 "--out file create or truncate \"file\" for all output\n" 3728 "--version print version information\n" 3729 "\n" 3730 "For more help, run \"man turbostat\"\n"); 3731 } 3732 3733 3734 /* 3735 * in /dev/cpu/ return success for names that are numbers 3736 * ie. filter out ".", "..", "microcode". 3737 */ 3738 int dir_filter(const struct dirent *dirp) 3739 { 3740 if (isdigit(dirp->d_name[0])) 3741 return 1; 3742 else 3743 return 0; 3744 } 3745 3746 int open_dev_cpu_msr(int dummy1) 3747 { 3748 return 0; 3749 } 3750 3751 void topology_probe() 3752 { 3753 int i; 3754 int max_core_id = 0; 3755 int max_package_id = 0; 3756 int max_siblings = 0; 3757 struct cpu_topology { 3758 int core_id; 3759 int physical_package_id; 3760 } *cpus; 3761 3762 /* Initialize num_cpus, max_cpu_num */ 3763 topo.num_cpus = 0; 3764 topo.max_cpu_num = 0; 3765 for_all_proc_cpus(count_cpus); 3766 if (!summary_only && topo.num_cpus > 1) 3767 BIC_PRESENT(BIC_CPU); 3768 3769 if (debug > 1) 3770 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 3771 3772 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 3773 if (cpus == NULL) 3774 err(1, "calloc cpus"); 3775 3776 /* 3777 * Allocate and initialize cpu_present_set 3778 */ 3779 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 3780 if (cpu_present_set == NULL) 3781 err(3, "CPU_ALLOC"); 3782 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3783 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 3784 for_all_proc_cpus(mark_cpu_present); 3785 3786 /* 3787 * Allocate and initialize cpu_affinity_set 3788 */ 3789 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 3790 if (cpu_affinity_set == NULL) 3791 err(3, "CPU_ALLOC"); 3792 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3793 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 3794 3795 3796 /* 3797 * For online cpus 3798 * find max_core_id, max_package_id 3799 */ 3800 for (i = 0; i <= topo.max_cpu_num; ++i) { 3801 int siblings; 3802 3803 if (cpu_is_not_present(i)) { 3804 if (debug > 1) 3805 fprintf(outf, "cpu%d NOT PRESENT\n", i); 3806 continue; 3807 } 3808 cpus[i].core_id = get_core_id(i); 3809 if (cpus[i].core_id > max_core_id) 3810 max_core_id = cpus[i].core_id; 3811 3812 cpus[i].physical_package_id = get_physical_package_id(i); 3813 if (cpus[i].physical_package_id > max_package_id) 3814 max_package_id = cpus[i].physical_package_id; 3815 3816 siblings = get_num_ht_siblings(i); 3817 if (siblings > max_siblings) 3818 max_siblings = siblings; 3819 if (debug > 1) 3820 fprintf(outf, "cpu %d pkg %d core %d\n", 3821 i, cpus[i].physical_package_id, cpus[i].core_id); 3822 } 3823 topo.num_cores_per_pkg = max_core_id + 1; 3824 if (debug > 1) 3825 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 3826 max_core_id, topo.num_cores_per_pkg); 3827 if (debug && !summary_only && topo.num_cores_per_pkg > 1) 3828 BIC_PRESENT(BIC_Core); 3829 3830 topo.num_packages = max_package_id + 1; 3831 if (debug > 1) 3832 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 3833 max_package_id, topo.num_packages); 3834 if (debug && !summary_only && topo.num_packages > 1) 3835 BIC_PRESENT(BIC_Package); 3836 3837 topo.num_threads_per_core = max_siblings; 3838 if (debug > 1) 3839 fprintf(outf, "max_siblings %d\n", max_siblings); 3840 3841 free(cpus); 3842 } 3843 3844 void 3845 allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) 3846 { 3847 int i; 3848 3849 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg * 3850 topo.num_packages, sizeof(struct thread_data)); 3851 if (*t == NULL) 3852 goto error; 3853 3854 for (i = 0; i < topo.num_threads_per_core * 3855 topo.num_cores_per_pkg * topo.num_packages; i++) 3856 (*t)[i].cpu_id = -1; 3857 3858 *c = calloc(topo.num_cores_per_pkg * topo.num_packages, 3859 sizeof(struct core_data)); 3860 if (*c == NULL) 3861 goto error; 3862 3863 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++) 3864 (*c)[i].core_id = -1; 3865 3866 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 3867 if (*p == NULL) 3868 goto error; 3869 3870 for (i = 0; i < topo.num_packages; i++) 3871 (*p)[i].package_id = i; 3872 3873 return; 3874 error: 3875 err(1, "calloc counters"); 3876 } 3877 /* 3878 * init_counter() 3879 * 3880 * set cpu_id, core_num, pkg_num 3881 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 3882 * 3883 * increment topo.num_cores when 1st core in pkg seen 3884 */ 3885 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 3886 struct pkg_data *pkg_base, int thread_num, int core_num, 3887 int pkg_num, int cpu_id) 3888 { 3889 struct thread_data *t; 3890 struct core_data *c; 3891 struct pkg_data *p; 3892 3893 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num); 3894 c = GET_CORE(core_base, core_num, pkg_num); 3895 p = GET_PKG(pkg_base, pkg_num); 3896 3897 t->cpu_id = cpu_id; 3898 if (thread_num == 0) { 3899 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 3900 if (cpu_is_first_core_in_package(cpu_id)) 3901 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 3902 } 3903 3904 c->core_id = core_num; 3905 p->package_id = pkg_num; 3906 } 3907 3908 3909 int initialize_counters(int cpu_id) 3910 { 3911 int my_thread_id, my_core_id, my_package_id; 3912 3913 my_package_id = get_physical_package_id(cpu_id); 3914 my_core_id = get_core_id(cpu_id); 3915 my_thread_id = get_cpu_position_in_core(cpu_id); 3916 if (!my_thread_id) 3917 topo.num_cores++; 3918 3919 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); 3920 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); 3921 return 0; 3922 } 3923 3924 void allocate_output_buffer() 3925 { 3926 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); 3927 outp = output_buffer; 3928 if (outp == NULL) 3929 err(-1, "calloc output buffer"); 3930 } 3931 void allocate_fd_percpu(void) 3932 { 3933 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 3934 if (fd_percpu == NULL) 3935 err(-1, "calloc fd_percpu"); 3936 } 3937 void allocate_irq_buffers(void) 3938 { 3939 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 3940 if (irq_column_2_cpu == NULL) 3941 err(-1, "calloc %d", topo.num_cpus); 3942 3943 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 3944 if (irqs_per_cpu == NULL) 3945 err(-1, "calloc %d", topo.max_cpu_num + 1); 3946 } 3947 void setup_all_buffers(void) 3948 { 3949 topology_probe(); 3950 allocate_irq_buffers(); 3951 allocate_fd_percpu(); 3952 allocate_counters(&thread_even, &core_even, &package_even); 3953 allocate_counters(&thread_odd, &core_odd, &package_odd); 3954 allocate_output_buffer(); 3955 for_all_proc_cpus(initialize_counters); 3956 } 3957 3958 void set_base_cpu(void) 3959 { 3960 base_cpu = sched_getcpu(); 3961 if (base_cpu < 0) 3962 err(-ENODEV, "No valid cpus found"); 3963 3964 if (debug > 1) 3965 fprintf(outf, "base_cpu = %d\n", base_cpu); 3966 } 3967 3968 void turbostat_init() 3969 { 3970 setup_all_buffers(); 3971 set_base_cpu(); 3972 check_dev_msr(); 3973 check_permissions(); 3974 process_cpuid(); 3975 3976 3977 if (debug) 3978 for_all_cpus(print_hwp, ODD_COUNTERS); 3979 3980 if (debug) 3981 for_all_cpus(print_epb, ODD_COUNTERS); 3982 3983 if (debug) 3984 for_all_cpus(print_perf_limit, ODD_COUNTERS); 3985 3986 if (debug) 3987 for_all_cpus(print_rapl, ODD_COUNTERS); 3988 3989 for_all_cpus(set_temperature_target, ODD_COUNTERS); 3990 3991 if (debug) 3992 for_all_cpus(print_thermal, ODD_COUNTERS); 3993 3994 if (debug && do_irtl_snb) 3995 print_irtl(); 3996 } 3997 3998 int fork_it(char **argv) 3999 { 4000 pid_t child_pid; 4001 int status; 4002 4003 status = for_all_cpus(get_counters, EVEN_COUNTERS); 4004 if (status) 4005 exit(status); 4006 /* clear affinity side-effect of get_counters() */ 4007 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 4008 gettimeofday(&tv_even, (struct timezone *)NULL); 4009 4010 child_pid = fork(); 4011 if (!child_pid) { 4012 /* child */ 4013 execvp(argv[0], argv); 4014 } else { 4015 4016 /* parent */ 4017 if (child_pid == -1) 4018 err(1, "fork"); 4019 4020 signal(SIGINT, SIG_IGN); 4021 signal(SIGQUIT, SIG_IGN); 4022 if (waitpid(child_pid, &status, 0) == -1) 4023 err(status, "waitpid"); 4024 } 4025 /* 4026 * n.b. fork_it() does not check for errors from for_all_cpus() 4027 * because re-starting is problematic when forking 4028 */ 4029 for_all_cpus(get_counters, ODD_COUNTERS); 4030 gettimeofday(&tv_odd, (struct timezone *)NULL); 4031 timersub(&tv_odd, &tv_even, &tv_delta); 4032 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 4033 fprintf(outf, "%s: Counter reset detected\n", progname); 4034 else { 4035 compute_average(EVEN_COUNTERS); 4036 format_all_counters(EVEN_COUNTERS); 4037 } 4038 4039 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 4040 4041 flush_output_stderr(); 4042 4043 return status; 4044 } 4045 4046 int get_and_dump_counters(void) 4047 { 4048 int status; 4049 4050 status = for_all_cpus(get_counters, ODD_COUNTERS); 4051 if (status) 4052 return status; 4053 4054 status = for_all_cpus(dump_counters, ODD_COUNTERS); 4055 if (status) 4056 return status; 4057 4058 flush_output_stdout(); 4059 4060 return status; 4061 } 4062 4063 void print_version() { 4064 fprintf(outf, "turbostat version 4.16 24 Dec 2016" 4065 " - Len Brown <lenb@kernel.org>\n"); 4066 } 4067 4068 int add_counter(unsigned int msr_num, char *name, unsigned int width, 4069 enum counter_scope scope, enum counter_type type, 4070 enum counter_format format) 4071 { 4072 struct msr_counter *msrp; 4073 4074 msrp = calloc(1, sizeof(struct msr_counter)); 4075 if (msrp == NULL) { 4076 perror("calloc"); 4077 exit(1); 4078 } 4079 4080 msrp->msr_num = msr_num; 4081 strncpy(msrp->name, name, NAME_BYTES); 4082 msrp->width = width; 4083 msrp->type = type; 4084 msrp->format = format; 4085 4086 switch (scope) { 4087 4088 case SCOPE_CPU: 4089 msrp->next = sys.tp; 4090 sys.tp = msrp; 4091 sys.added_thread_counters++; 4092 if (sys.added_thread_counters > MAX_ADDED_COUNTERS) { 4093 fprintf(stderr, "exceeded max %d added thread counters\n", 4094 MAX_ADDED_COUNTERS); 4095 exit(-1); 4096 } 4097 break; 4098 4099 case SCOPE_CORE: 4100 msrp->next = sys.cp; 4101 sys.cp = msrp; 4102 sys.added_core_counters++; 4103 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 4104 fprintf(stderr, "exceeded max %d added core counters\n", 4105 MAX_ADDED_COUNTERS); 4106 exit(-1); 4107 } 4108 break; 4109 4110 case SCOPE_PACKAGE: 4111 msrp->next = sys.pp; 4112 sys.pp = msrp; 4113 sys.added_package_counters++; 4114 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 4115 fprintf(stderr, "exceeded max %d added package counters\n", 4116 MAX_ADDED_COUNTERS); 4117 exit(-1); 4118 } 4119 break; 4120 } 4121 4122 return 0; 4123 } 4124 4125 void parse_add_command(char *add_command) 4126 { 4127 int msr_num = 0; 4128 char name_buffer[NAME_BYTES]; 4129 int width = 64; 4130 int fail = 0; 4131 enum counter_scope scope = SCOPE_CPU; 4132 enum counter_type type = COUNTER_CYCLES; 4133 enum counter_format format = FORMAT_DELTA; 4134 4135 while (add_command) { 4136 4137 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 4138 goto next; 4139 4140 if (sscanf(add_command, "msr%d", &msr_num) == 1) 4141 goto next; 4142 4143 if (sscanf(add_command, "u%d", &width) == 1) { 4144 if ((width == 32) || (width == 64)) 4145 goto next; 4146 width = 64; 4147 } 4148 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 4149 scope = SCOPE_CPU; 4150 goto next; 4151 } 4152 if (!strncmp(add_command, "core", strlen("core"))) { 4153 scope = SCOPE_CORE; 4154 goto next; 4155 } 4156 if (!strncmp(add_command, "package", strlen("package"))) { 4157 scope = SCOPE_PACKAGE; 4158 goto next; 4159 } 4160 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 4161 type = COUNTER_CYCLES; 4162 goto next; 4163 } 4164 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 4165 type = COUNTER_SECONDS; 4166 goto next; 4167 } 4168 if (!strncmp(add_command, "raw", strlen("raw"))) { 4169 format = FORMAT_RAW; 4170 goto next; 4171 } 4172 if (!strncmp(add_command, "delta", strlen("delta"))) { 4173 format = FORMAT_DELTA; 4174 goto next; 4175 } 4176 if (!strncmp(add_command, "percent", strlen("percent"))) { 4177 format = FORMAT_PERCENT; 4178 goto next; 4179 } 4180 4181 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 4182 char *eos; 4183 4184 eos = strchr(name_buffer, ','); 4185 if (eos) 4186 *eos = '\0'; 4187 goto next; 4188 } 4189 4190 next: 4191 add_command = strchr(add_command, ','); 4192 if (add_command) 4193 add_command++; 4194 4195 } 4196 if (msr_num == 0) { 4197 fprintf(stderr, "--add: (msrDDD | msr0xXXX) required\n"); 4198 fail++; 4199 } 4200 4201 /* generate default column header */ 4202 if (*name_buffer == '\0') { 4203 if (format == FORMAT_RAW) { 4204 if (width == 32) 4205 sprintf(name_buffer, "msr%d", msr_num); 4206 else 4207 sprintf(name_buffer, "MSR%d", msr_num); 4208 } else if (format == FORMAT_DELTA) { 4209 if (width == 32) 4210 sprintf(name_buffer, "cnt%d", msr_num); 4211 else 4212 sprintf(name_buffer, "CNT%d", msr_num); 4213 } else if (format == FORMAT_PERCENT) { 4214 if (width == 32) 4215 sprintf(name_buffer, "msr%d%%", msr_num); 4216 else 4217 sprintf(name_buffer, "MSR%d%%", msr_num); 4218 } 4219 } 4220 4221 if (add_counter(msr_num, name_buffer, width, scope, type, format)) 4222 fail++; 4223 4224 if (fail) { 4225 help(); 4226 exit(1); 4227 } 4228 } 4229 /* 4230 * HIDE_LIST - hide this list of counters, show the rest [default] 4231 * SHOW_LIST - show this list of counters, hide the rest 4232 */ 4233 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 4234 4235 int shown; 4236 /* 4237 * parse_show_hide() - process cmdline to set default counter action 4238 */ 4239 void parse_show_hide(char *optarg, enum show_hide_mode new_mode) 4240 { 4241 /* 4242 * --show: show only those specified 4243 * The 1st invocation will clear and replace the enabled mask 4244 * subsequent invocations can add to it. 4245 */ 4246 if (new_mode == SHOW_LIST) { 4247 if (shown == 0) 4248 bic_enabled = bic_lookup(optarg); 4249 else 4250 bic_enabled |= bic_lookup(optarg); 4251 shown = 1; 4252 4253 return; 4254 } 4255 4256 /* 4257 * --hide: do not show those specified 4258 * multiple invocations simply clear more bits in enabled mask 4259 */ 4260 bic_enabled &= ~bic_lookup(optarg); 4261 } 4262 4263 void cmdline(int argc, char **argv) 4264 { 4265 int opt; 4266 int option_index = 0; 4267 static struct option long_options[] = { 4268 {"add", required_argument, 0, 'a'}, 4269 {"Dump", no_argument, 0, 'D'}, 4270 {"debug", no_argument, 0, 'd'}, 4271 {"interval", required_argument, 0, 'i'}, 4272 {"help", no_argument, 0, 'h'}, 4273 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help 4274 {"Joules", no_argument, 0, 'J'}, 4275 {"out", required_argument, 0, 'o'}, 4276 {"Package", no_argument, 0, 'p'}, 4277 {"processor", no_argument, 0, 'p'}, 4278 {"show", required_argument, 0, 's'}, 4279 {"Summary", no_argument, 0, 'S'}, 4280 {"TCC", required_argument, 0, 'T'}, 4281 {"version", no_argument, 0, 'v' }, 4282 {0, 0, 0, 0 } 4283 }; 4284 4285 progname = argv[0]; 4286 4287 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpST:v", 4288 long_options, &option_index)) != -1) { 4289 switch (opt) { 4290 case 'a': 4291 parse_add_command(optarg); 4292 break; 4293 case 'D': 4294 dump_only++; 4295 break; 4296 case 'd': 4297 debug++; 4298 break; 4299 case 'H': 4300 parse_show_hide(optarg, HIDE_LIST); 4301 break; 4302 case 'h': 4303 default: 4304 help(); 4305 exit(1); 4306 case 'i': 4307 { 4308 double interval = strtod(optarg, NULL); 4309 4310 if (interval < 0.001) { 4311 fprintf(outf, "interval %f seconds is too small\n", 4312 interval); 4313 exit(2); 4314 } 4315 4316 interval_ts.tv_sec = interval; 4317 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 4318 } 4319 break; 4320 case 'J': 4321 rapl_joules++; 4322 break; 4323 case 'o': 4324 outf = fopen_or_die(optarg, "w"); 4325 break; 4326 case 'P': 4327 show_pkg_only++; 4328 break; 4329 case 'p': 4330 show_core_only++; 4331 break; 4332 case 's': 4333 parse_show_hide(optarg, SHOW_LIST); 4334 break; 4335 case 'S': 4336 summary_only++; 4337 break; 4338 case 'T': 4339 tcc_activation_temp_override = atoi(optarg); 4340 break; 4341 case 'v': 4342 print_version(); 4343 exit(0); 4344 break; 4345 } 4346 } 4347 } 4348 4349 int main(int argc, char **argv) 4350 { 4351 outf = stderr; 4352 4353 cmdline(argc, argv); 4354 4355 if (debug) 4356 print_version(); 4357 4358 turbostat_init(); 4359 4360 /* dump counters and exit */ 4361 if (dump_only) 4362 return get_and_dump_counters(); 4363 4364 /* 4365 * if any params left, it must be a command to fork 4366 */ 4367 if (argc - optind) 4368 return fork_it(argv + optind); 4369 else 4370 turbostat_loop(); 4371 4372 return 0; 4373 } 4374