arm64: tegra: Fixup SYSRAM references

[ Upstream commit 7fa307524a4d721d4a04523018509882c5414e72 ]

The json-schema bindings for SRAM expect the nodes to be called "sram"
rather than "sysram" or "sh

arm64: tegra: Fixup SYSRAM references

[ Upstream commit 7fa307524a4d721d4a04523018509882c5414e72 ]

The json-schema bindings for SRAM expect the nodes to be called "sram"
rather than "sysram" or "shmem". Furthermore, place the brackets around
the SYSRAM references such that a two-element array is created rather
than a two-element array nested in a single-element array. This is not
relevant for device tree itself, but allows the nodes to be properly
validated against json-schema bindings.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: tegra: Adjust length of CCPLEX cluster MMIO region

[ Upstream commit 2b14cbd643feea5fc17c6e8bead4e71088c69acd ]

The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4
MiB - 1.

arm64: tegra: Adjust length of CCPLEX cluster MMIO region

[ Upstream commit 2b14cbd643feea5fc17c6e8bead4e71088c69acd ]

The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4
MiB - 1. This was likely presumed to be the "limit" rather than length.
Fix it up.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: tegra: Add missing interconnects property for USB on Tegra186

The device tree node for the XUDC (USB device mode controller) is
missing the interconnects property that describes the path to m

arm64: tegra: Add missing interconnects property for USB on Tegra186

The device tree node for the XUDC (USB device mode controller) is
missing the interconnects property that describes the path to memory for
the controller. Add the property so that the things like the DMA mask
can be set by the operating system.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add PWM nodes on Tegra186

These PWMs can be used for fan or LED backlight control. Add the device
tree nodes for all existing controllers found on Tegra186 SoCs. None of
these are enab

arm64: tegra: Add PWM nodes on Tegra186

These PWMs can be used for fan or LED backlight control. Add the device
tree nodes for all existing controllers found on Tegra186 SoCs. None of
these are enabled by default, which is left for the board DTS files to
do when necessary.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Hook up memory controller to SMMU on Tegra186

On Tegra186 and later, the memory controller needs to be programmed in
coordination with any of the ARM SMMU instances to configure the st

arm64: tegra: Hook up memory controller to SMMU on Tegra186

On Tegra186 and later, the memory controller needs to be programmed in
coordination with any of the ARM SMMU instances to configure the stream
ID used for each memory client.

To support this, add a phandle reference to the memory controller to the
SMMU device tree node.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Use correct compatible string for Tegra186 SMMU

The SMMU found on Tegra186 requires interoperation with the memory
controller in order to program stream ID overrides. The generic ARM S

arm64: tegra: Use correct compatible string for Tegra186 SMMU

The SMMU found on Tegra186 requires interoperation with the memory
controller in order to program stream ID overrides. The generic ARM SMMU
500 compatible is therefore inaccurate. Replace it with a more correct,
SoC-specific compatible string.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add unit-address for ACONNECT on Tegra186

The ACONNECT device tree node has a unit-address on all other SoC
generations and there's really no reason not to have it on Tegra186.

Review

arm64: tegra: Add unit-address for ACONNECT on Tegra186

The ACONNECT device tree node has a unit-address on all other SoC
generations and there's really no reason not to have it on Tegra186.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Audio graph sound card for Jetson TX2

Enable support for audio-graph based sound card on Jetson TX2. Based
on the board design following I/O modules are enabled.
* All I2S instances

arm64: tegra: Audio graph sound card for Jetson TX2

Enable support for audio-graph based sound card on Jetson TX2. Based
on the board design following I/O modules are enabled.
* All I2S instances (I2S1 ... I2S6)
* All DSPK instances (DSPK1, DSPK2)
* DMIC1, DMIC2 and DMIC3

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Enable AHCI on Jetson TX2

This patch enables AHCI on Jetson TX2.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Add XUSB pad controller interrupt

This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194
XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake
event happen

arm64: tegra: Add XUSB pad controller interrupt

This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194
XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake
event happens. This is required for supporting XUSB host controller
ELPG.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix GIC400 missing GICH/GICV register regions

GIC400 has full support for virtualization, and yet the tegra186
DT doesn't expose the GICH/GICV regions (despite exposing the
maintenance

arm64: tegra: Fix GIC400 missing GICH/GICV register regions

GIC400 has full support for virtualization, and yet the tegra186
DT doesn't expose the GICH/GICV regions (despite exposing the
maintenance interrupt that only makes sense for virtualization).

Add the missing regions, based on the hunch that the HW doesn't
use the CPU build-in interfaces, but instead the external ones
provided by the GIC. KVM's virtual GIC now works with this change.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add missing CPU PMUs on Tegra186

Add the description of CPU PMUs for both the Denver and A57 clusters,
which enables the perf subsystem.

Signed-off-by: Marc Zyngier <maz@kernel.org>
S

arm64: tegra: Add missing CPU PMUs on Tegra186

Add the description of CPU PMUs for both the Denver and A57 clusters,
which enables the perf subsystem.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add DT binding for AHUB components

This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194.
Bindings for following modules are added.
* AHUB added as a child node under A

arm64: tegra: Add DT binding for AHUB components

This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194.
Bindings for following modules are added.
* AHUB added as a child node under ACONNECT
* AHUB includes many HW accelerators and below components are added
as its children.
* ADMAIF
* I2S
* DMIC
* DSPK (added for Tegra186 and Tegra194 only, since Tegra210 does
not have this module)

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add missing timeout clock to Tegra186 SDMMC nodes

commit 39cb62cb8973 ("arm64: tegra: Add Tegra186 support")

Tegra186 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clo

arm64: tegra: Add missing timeout clock to Tegra186 SDMMC nodes

commit 39cb62cb8973 ("arm64: tegra: Add Tegra186 support")

Tegra186 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.

Tegra186 SDMMC advertises 12Mhz as timeout clock frequency in host
capability register and uses it by default.

So, this clock should be kept enabled by the SDMMC driver.

Fixes: 39cb62cb8973 ("arm64: tegra: Add Tegra186 support")
Cc: stable <stable@vger.kernel.org> # 5.4
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Link: https://lore.kernel.org/r/1598548861-32373-6-git-send-email-skomatineni@nvidia.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

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arm64: tegra: Use standard names for SRAM nodes

SRAM nodes should be named sram@<unit-address> to match the bindings.

While at it, also remove the unneeded, custom compatible string for
SRAM partit

arm64: tegra: Use standard names for SRAM nodes

SRAM nodes should be named sram@<unit-address> to match the bindings.

While at it, also remove the unneeded, custom compatible string for
SRAM partition nodes.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Do not mark display hub as simple bus

The display hub on Tegra186 and Tegra194 is not a simple bus, so drop
the corresponding compatible string.

Signed-off-by: Thierry Reding <treding

arm64: tegra: Do not mark display hub as simple bus

The display hub on Tegra186 and Tegra194 is not a simple bus, so drop
the corresponding compatible string.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix {clock,reset}-names ordering

It's very difficult to describe string lists that can be in arbitrary
order using the json-schema based validation tooling. Since the OS is
not going t

arm64: tegra: Fix {clock,reset}-names ordering

It's very difficult to describe string lists that can be in arbitrary
order using the json-schema based validation tooling. Since the OS is
not going to care either way, take the easy way out and reorder these
entries to match the order defined in the bindings.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Remove XUSB pad controller interrupt from XUSB node

The XUSB controller doesn't need the XUSB pad controller's interrupt, so
remove it.

Signed-off-by: Thierry Reding <treding@nvidia.c

arm64: tegra: Remove XUSB pad controller interrupt from XUSB node

The XUSB controller doesn't need the XUSB pad controller's interrupt, so
remove it.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Do not mark host1x as simple bus

The host1x is not a simple bus, so drop the corresponding compatible
string.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Use proper tuple notation

Tuple boundaries should be marked by < and > to make it clear which
cells are part of the same tuple. This also helps the json-schema based
validation tooling

arm64: tegra: Use proper tuple notation

Tuple boundaries should be marked by < and > to make it clear which
cells are part of the same tuple. This also helps the json-schema based
validation tooling to properly parse this data.

While at it, also remove the "immovable" bit from PCI addresses. All of
these addresses are in fact "movable".

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename sdhci nodes to mmc

The new json-schema based validation tools require SD/MMC controller
nodes to be named mmc. Rename all references to them.

Signed-off-by: Thierry Reding <tre

arm64: tegra: Rename sdhci nodes to mmc

The new json-schema based validation tools require SD/MMC controller
nodes to be named mmc. Rename all references to them.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add interrupt-names for host1x

Interrupt names are used to distinguish between the syncpoint and
general host1x interrupts. Make sure they are available in the DT so
that drivers can u

arm64: tegra: Add interrupt-names for host1x

Interrupt names are used to distinguish between the syncpoint and
general host1x interrupts. Make sure they are available in the DT so
that drivers can use them if necessary.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Describe interconnect paths on Tegra186

The interface used by clients of the memory controller can be configured
in a number of different ways. Describe this path using the interconnec

arm64: tegra: Describe interconnect paths on Tegra186

The interface used by clients of the memory controller can be configured
in a number of different ways. Describe this path using the interconnect
bindings to enable the configuration of these parameters.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Use standard notation for interrupts

It is customary to use angle brackets around each tuple in the
interrupts property.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Fix #address-cells/#size-cells for SRAM on Tegra186

The standard mmio-sram bindings require the #address- and #size-cells
properties to be 1.

Signed-off-by: Thierry Reding <treding@nv

arm64: tegra: Fix #address-cells/#size-cells for SRAM on Tegra186

The standard mmio-sram bindings require the #address- and #size-cells
properties to be 1.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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