1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra186-clock.h>
3#include <dt-bindings/gpio/tegra186-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/memory/tegra186-mc.h>
7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8#include <dt-bindings/power/tegra186-powergate.h>
9#include <dt-bindings/reset/tegra186-reset.h>
10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
11
12/ {
13	compatible = "nvidia,tegra186";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	misc@100000 {
19		compatible = "nvidia,tegra186-misc";
20		reg = <0x0 0x00100000 0x0 0xf000>,
21		      <0x0 0x0010f000 0x0 0x1000>;
22	};
23
24	gpio: gpio@2200000 {
25		compatible = "nvidia,tegra186-gpio";
26		reg-names = "security", "gpio";
27		reg = <0x0 0x2200000 0x0 0x10000>,
28		      <0x0 0x2210000 0x0 0x10000>;
29		interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
30			     <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
31			     <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
33			     <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
34			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35		#interrupt-cells = <2>;
36		interrupt-controller;
37		#gpio-cells = <2>;
38		gpio-controller;
39	};
40
41	ethernet@2490000 {
42		compatible = "nvidia,tegra186-eqos",
43			     "snps,dwc-qos-ethernet-4.10";
44		reg = <0x0 0x02490000 0x0 0x10000>;
45		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56			 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57			 <&bpmp TEGRA186_CLK_EQOS_RX>,
58			 <&bpmp TEGRA186_CLK_EQOS_TX>,
59			 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61		resets = <&bpmp TEGRA186_RESET_EQOS>;
62		reset-names = "eqos";
63		interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
64				<&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
65		interconnect-names = "dma-mem", "write";
66		iommus = <&smmu TEGRA186_SID_EQOS>;
67		status = "disabled";
68
69		snps,write-requests = <1>;
70		snps,read-requests = <3>;
71		snps,burst-map = <0x7>;
72		snps,txpbl = <32>;
73		snps,rxpbl = <8>;
74	};
75
76	aconnect@2900000 {
77		compatible = "nvidia,tegra186-aconnect",
78			     "nvidia,tegra210-aconnect";
79		clocks = <&bpmp TEGRA186_CLK_APE>,
80			 <&bpmp TEGRA186_CLK_APB2APE>;
81		clock-names = "ape", "apb2ape";
82		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
83		#address-cells = <1>;
84		#size-cells = <1>;
85		ranges = <0x02900000 0x0 0x02900000 0x200000>;
86		status = "disabled";
87
88		adma: dma-controller@2930000 {
89			compatible = "nvidia,tegra186-adma";
90			reg = <0x02930000 0x20000>;
91			interrupt-parent = <&agic>;
92			interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
93				      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
94				      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
95				      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
96				      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
97				      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
98				      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
99				      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
100				      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
101				      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
102				      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
103				      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
104				      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
105				      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
106				      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
107				      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
108				      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
109				      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
110				      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
111				      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
112				      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
113				      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
114				      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
115				      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
116				      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
117				      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
118				      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
119				      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
120				      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
121				      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
122				      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
123				      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
124			#dma-cells = <1>;
125			clocks = <&bpmp TEGRA186_CLK_AHUB>;
126			clock-names = "d_audio";
127			status = "disabled";
128		};
129
130		agic: interrupt-controller@2a40000 {
131			compatible = "nvidia,tegra186-agic",
132				     "nvidia,tegra210-agic";
133			#interrupt-cells = <3>;
134			interrupt-controller;
135			reg = <0x02a41000 0x1000>,
136			      <0x02a42000 0x2000>;
137			interrupts = <GIC_SPI 145
138				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
139			clocks = <&bpmp TEGRA186_CLK_APE>;
140			clock-names = "clk";
141			status = "disabled";
142		};
143
144		tegra_ahub: ahub@2900800 {
145			compatible = "nvidia,tegra186-ahub";
146			reg = <0x02900800 0x800>;
147			clocks = <&bpmp TEGRA186_CLK_AHUB>;
148			clock-names = "ahub";
149			assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
150			assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
151			#address-cells = <1>;
152			#size-cells = <1>;
153			ranges = <0x02900800 0x02900800 0x11800>;
154			status = "disabled";
155
156			tegra_admaif: admaif@290f000 {
157				compatible = "nvidia,tegra186-admaif";
158				reg = <0x0290f000 0x1000>;
159				dmas = <&adma 1>, <&adma 1>,
160				       <&adma 2>, <&adma 2>,
161				       <&adma 3>, <&adma 3>,
162				       <&adma 4>, <&adma 4>,
163				       <&adma 5>, <&adma 5>,
164				       <&adma 6>, <&adma 6>,
165				       <&adma 7>, <&adma 7>,
166				       <&adma 8>, <&adma 8>,
167				       <&adma 9>, <&adma 9>,
168				       <&adma 10>, <&adma 10>,
169				       <&adma 11>, <&adma 11>,
170				       <&adma 12>, <&adma 12>,
171				       <&adma 13>, <&adma 13>,
172				       <&adma 14>, <&adma 14>,
173				       <&adma 15>, <&adma 15>,
174				       <&adma 16>, <&adma 16>,
175				       <&adma 17>, <&adma 17>,
176				       <&adma 18>, <&adma 18>,
177				       <&adma 19>, <&adma 19>,
178				       <&adma 20>, <&adma 20>;
179				dma-names = "rx1", "tx1",
180					    "rx2", "tx2",
181					    "rx3", "tx3",
182					    "rx4", "tx4",
183					    "rx5", "tx5",
184					    "rx6", "tx6",
185					    "rx7", "tx7",
186					    "rx8", "tx8",
187					    "rx9", "tx9",
188					    "rx10", "tx10",
189					    "rx11", "tx11",
190					    "rx12", "tx12",
191					    "rx13", "tx13",
192					    "rx14", "tx14",
193					    "rx15", "tx15",
194					    "rx16", "tx16",
195					    "rx17", "tx17",
196					    "rx18", "tx18",
197					    "rx19", "tx19",
198					    "rx20", "tx20";
199				status = "disabled";
200			};
201
202			tegra_i2s1: i2s@2901000 {
203				compatible = "nvidia,tegra186-i2s",
204					     "nvidia,tegra210-i2s";
205				reg = <0x2901000 0x100>;
206				clocks = <&bpmp TEGRA186_CLK_I2S1>,
207					 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
208				clock-names = "i2s", "sync_input";
209				assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
210				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
211				assigned-clock-rates = <1536000>;
212				sound-name-prefix = "I2S1";
213				status = "disabled";
214			};
215
216			tegra_i2s2: i2s@2901100 {
217				compatible = "nvidia,tegra186-i2s",
218					     "nvidia,tegra210-i2s";
219				reg = <0x2901100 0x100>;
220				clocks = <&bpmp TEGRA186_CLK_I2S2>,
221					 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
222				clock-names = "i2s", "sync_input";
223				assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
224				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
225				assigned-clock-rates = <1536000>;
226				sound-name-prefix = "I2S2";
227				status = "disabled";
228			};
229
230			tegra_i2s3: i2s@2901200 {
231				compatible = "nvidia,tegra186-i2s",
232					     "nvidia,tegra210-i2s";
233				reg = <0x2901200 0x100>;
234				clocks = <&bpmp TEGRA186_CLK_I2S3>,
235					 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
236				clock-names = "i2s", "sync_input";
237				assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
238				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
239				assigned-clock-rates = <1536000>;
240				sound-name-prefix = "I2S3";
241				status = "disabled";
242			};
243
244			tegra_i2s4: i2s@2901300 {
245				compatible = "nvidia,tegra186-i2s",
246					     "nvidia,tegra210-i2s";
247				reg = <0x2901300 0x100>;
248				clocks = <&bpmp TEGRA186_CLK_I2S4>,
249					 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
250				clock-names = "i2s", "sync_input";
251				assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
252				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
253				assigned-clock-rates = <1536000>;
254				sound-name-prefix = "I2S4";
255				status = "disabled";
256			};
257
258			tegra_i2s5: i2s@2901400 {
259				compatible = "nvidia,tegra186-i2s",
260					     "nvidia,tegra210-i2s";
261				reg = <0x2901400 0x100>;
262				clocks = <&bpmp TEGRA186_CLK_I2S5>,
263					 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
264				clock-names = "i2s", "sync_input";
265				assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
266				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
267				assigned-clock-rates = <1536000>;
268				sound-name-prefix = "I2S5";
269				status = "disabled";
270			};
271
272			tegra_i2s6: i2s@2901500 {
273				compatible = "nvidia,tegra186-i2s",
274					     "nvidia,tegra210-i2s";
275				reg = <0x2901500 0x100>;
276				clocks = <&bpmp TEGRA186_CLK_I2S6>,
277					 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
278				clock-names = "i2s", "sync_input";
279				assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
280				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
281				assigned-clock-rates = <1536000>;
282				sound-name-prefix = "I2S6";
283				status = "disabled";
284			};
285
286			tegra_dmic1: dmic@2904000 {
287				compatible = "nvidia,tegra210-dmic";
288				reg = <0x2904000 0x100>;
289				clocks = <&bpmp TEGRA186_CLK_DMIC1>;
290				clock-names = "dmic";
291				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
292				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
293				assigned-clock-rates = <3072000>;
294				sound-name-prefix = "DMIC1";
295				status = "disabled";
296			};
297
298			tegra_dmic2: dmic@2904100 {
299				compatible = "nvidia,tegra210-dmic";
300				reg = <0x2904100 0x100>;
301				clocks = <&bpmp TEGRA186_CLK_DMIC2>;
302				clock-names = "dmic";
303				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
304				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
305				assigned-clock-rates = <3072000>;
306				sound-name-prefix = "DMIC2";
307				status = "disabled";
308			};
309
310			tegra_dmic3: dmic@2904200 {
311				compatible = "nvidia,tegra210-dmic";
312				reg = <0x2904200 0x100>;
313				clocks = <&bpmp TEGRA186_CLK_DMIC3>;
314				clock-names = "dmic";
315				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
316				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
317				assigned-clock-rates = <3072000>;
318				sound-name-prefix = "DMIC3";
319				status = "disabled";
320			};
321
322			tegra_dmic4: dmic@2904300 {
323				compatible = "nvidia,tegra210-dmic";
324				reg = <0x2904300 0x100>;
325				clocks = <&bpmp TEGRA186_CLK_DMIC4>;
326				clock-names = "dmic";
327				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
328				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
329				assigned-clock-rates = <3072000>;
330				sound-name-prefix = "DMIC4";
331				status = "disabled";
332			};
333
334			tegra_dspk1: dspk@2905000 {
335				compatible = "nvidia,tegra186-dspk";
336				reg = <0x2905000 0x100>;
337				clocks = <&bpmp TEGRA186_CLK_DSPK1>;
338				clock-names = "dspk";
339				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
340				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
341				assigned-clock-rates = <12288000>;
342				sound-name-prefix = "DSPK1";
343				status = "disabled";
344			};
345
346			tegra_dspk2: dspk@2905100 {
347				compatible = "nvidia,tegra186-dspk";
348				reg = <0x2905100 0x100>;
349				clocks = <&bpmp TEGRA186_CLK_DSPK2>;
350				clock-names = "dspk";
351				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
352				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
353				assigned-clock-rates = <12288000>;
354				sound-name-prefix = "DSPK2";
355				status = "disabled";
356			};
357		};
358	};
359
360	mc: memory-controller@2c00000 {
361		compatible = "nvidia,tegra186-mc";
362		reg = <0x0 0x02c00000 0x0 0xb0000>;
363		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
364		status = "disabled";
365
366		#interconnect-cells = <1>;
367		#address-cells = <2>;
368		#size-cells = <2>;
369
370		ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
371
372		/*
373		 * Memory clients have access to all 40 bits that the memory
374		 * controller can address.
375		 */
376		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
377
378		emc: external-memory-controller@2c60000 {
379			compatible = "nvidia,tegra186-emc";
380			reg = <0x0 0x02c60000 0x0 0x50000>;
381			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
382			clocks = <&bpmp TEGRA186_CLK_EMC>;
383			clock-names = "emc";
384
385			#interconnect-cells = <0>;
386
387			nvidia,bpmp = <&bpmp>;
388		};
389	};
390
391	uarta: serial@3100000 {
392		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
393		reg = <0x0 0x03100000 0x0 0x40>;
394		reg-shift = <2>;
395		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
396		clocks = <&bpmp TEGRA186_CLK_UARTA>;
397		clock-names = "serial";
398		resets = <&bpmp TEGRA186_RESET_UARTA>;
399		reset-names = "serial";
400		status = "disabled";
401	};
402
403	uartb: serial@3110000 {
404		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
405		reg = <0x0 0x03110000 0x0 0x40>;
406		reg-shift = <2>;
407		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
408		clocks = <&bpmp TEGRA186_CLK_UARTB>;
409		clock-names = "serial";
410		resets = <&bpmp TEGRA186_RESET_UARTB>;
411		reset-names = "serial";
412		status = "disabled";
413	};
414
415	uartd: serial@3130000 {
416		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
417		reg = <0x0 0x03130000 0x0 0x40>;
418		reg-shift = <2>;
419		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
420		clocks = <&bpmp TEGRA186_CLK_UARTD>;
421		clock-names = "serial";
422		resets = <&bpmp TEGRA186_RESET_UARTD>;
423		reset-names = "serial";
424		status = "disabled";
425	};
426
427	uarte: serial@3140000 {
428		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
429		reg = <0x0 0x03140000 0x0 0x40>;
430		reg-shift = <2>;
431		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
432		clocks = <&bpmp TEGRA186_CLK_UARTE>;
433		clock-names = "serial";
434		resets = <&bpmp TEGRA186_RESET_UARTE>;
435		reset-names = "serial";
436		status = "disabled";
437	};
438
439	uartf: serial@3150000 {
440		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
441		reg = <0x0 0x03150000 0x0 0x40>;
442		reg-shift = <2>;
443		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
444		clocks = <&bpmp TEGRA186_CLK_UARTF>;
445		clock-names = "serial";
446		resets = <&bpmp TEGRA186_RESET_UARTF>;
447		reset-names = "serial";
448		status = "disabled";
449	};
450
451	gen1_i2c: i2c@3160000 {
452		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
453		reg = <0x0 0x03160000 0x0 0x10000>;
454		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
455		#address-cells = <1>;
456		#size-cells = <0>;
457		clocks = <&bpmp TEGRA186_CLK_I2C1>;
458		clock-names = "div-clk";
459		resets = <&bpmp TEGRA186_RESET_I2C1>;
460		reset-names = "i2c";
461		status = "disabled";
462	};
463
464	cam_i2c: i2c@3180000 {
465		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
466		reg = <0x0 0x03180000 0x0 0x10000>;
467		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
468		#address-cells = <1>;
469		#size-cells = <0>;
470		clocks = <&bpmp TEGRA186_CLK_I2C3>;
471		clock-names = "div-clk";
472		resets = <&bpmp TEGRA186_RESET_I2C3>;
473		reset-names = "i2c";
474		status = "disabled";
475	};
476
477	/* shares pads with dpaux1 */
478	dp_aux_ch1_i2c: i2c@3190000 {
479		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
480		reg = <0x0 0x03190000 0x0 0x10000>;
481		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
482		#address-cells = <1>;
483		#size-cells = <0>;
484		clocks = <&bpmp TEGRA186_CLK_I2C4>;
485		clock-names = "div-clk";
486		resets = <&bpmp TEGRA186_RESET_I2C4>;
487		reset-names = "i2c";
488		pinctrl-names = "default", "idle";
489		pinctrl-0 = <&state_dpaux1_i2c>;
490		pinctrl-1 = <&state_dpaux1_off>;
491		status = "disabled";
492	};
493
494	/* controlled by BPMP, should not be enabled */
495	pwr_i2c: i2c@31a0000 {
496		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
497		reg = <0x0 0x031a0000 0x0 0x10000>;
498		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
499		#address-cells = <1>;
500		#size-cells = <0>;
501		clocks = <&bpmp TEGRA186_CLK_I2C5>;
502		clock-names = "div-clk";
503		resets = <&bpmp TEGRA186_RESET_I2C5>;
504		reset-names = "i2c";
505		status = "disabled";
506	};
507
508	/* shares pads with dpaux0 */
509	dp_aux_ch0_i2c: i2c@31b0000 {
510		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
511		reg = <0x0 0x031b0000 0x0 0x10000>;
512		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
513		#address-cells = <1>;
514		#size-cells = <0>;
515		clocks = <&bpmp TEGRA186_CLK_I2C6>;
516		clock-names = "div-clk";
517		resets = <&bpmp TEGRA186_RESET_I2C6>;
518		reset-names = "i2c";
519		pinctrl-names = "default", "idle";
520		pinctrl-0 = <&state_dpaux_i2c>;
521		pinctrl-1 = <&state_dpaux_off>;
522		status = "disabled";
523	};
524
525	gen7_i2c: i2c@31c0000 {
526		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
527		reg = <0x0 0x031c0000 0x0 0x10000>;
528		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
529		#address-cells = <1>;
530		#size-cells = <0>;
531		clocks = <&bpmp TEGRA186_CLK_I2C7>;
532		clock-names = "div-clk";
533		resets = <&bpmp TEGRA186_RESET_I2C7>;
534		reset-names = "i2c";
535		status = "disabled";
536	};
537
538	gen9_i2c: i2c@31e0000 {
539		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
540		reg = <0x0 0x031e0000 0x0 0x10000>;
541		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
542		#address-cells = <1>;
543		#size-cells = <0>;
544		clocks = <&bpmp TEGRA186_CLK_I2C9>;
545		clock-names = "div-clk";
546		resets = <&bpmp TEGRA186_RESET_I2C9>;
547		reset-names = "i2c";
548		status = "disabled";
549	};
550
551	sdmmc1: mmc@3400000 {
552		compatible = "nvidia,tegra186-sdhci";
553		reg = <0x0 0x03400000 0x0 0x10000>;
554		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
555		clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
556			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
557		clock-names = "sdhci", "tmclk";
558		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
559		reset-names = "sdhci";
560		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
561				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
562		interconnect-names = "dma-mem", "write";
563		iommus = <&smmu TEGRA186_SID_SDMMC1>;
564		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
565		pinctrl-0 = <&sdmmc1_3v3>;
566		pinctrl-1 = <&sdmmc1_1v8>;
567		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
568		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
569		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
570		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
571		nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
572		nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
573		nvidia,default-tap = <0x5>;
574		nvidia,default-trim = <0xb>;
575		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
576				  <&bpmp TEGRA186_CLK_PLLP_OUT0>;
577		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
578		status = "disabled";
579	};
580
581	sdmmc2: mmc@3420000 {
582		compatible = "nvidia,tegra186-sdhci";
583		reg = <0x0 0x03420000 0x0 0x10000>;
584		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
585		clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
586			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
587		clock-names = "sdhci", "tmclk";
588		resets = <&bpmp TEGRA186_RESET_SDMMC2>;
589		reset-names = "sdhci";
590		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
591				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
592		interconnect-names = "dma-mem", "write";
593		iommus = <&smmu TEGRA186_SID_SDMMC2>;
594		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
595		pinctrl-0 = <&sdmmc2_3v3>;
596		pinctrl-1 = <&sdmmc2_1v8>;
597		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
598		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
599		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
600		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
601		nvidia,default-tap = <0x5>;
602		nvidia,default-trim = <0xb>;
603		status = "disabled";
604	};
605
606	sdmmc3: mmc@3440000 {
607		compatible = "nvidia,tegra186-sdhci";
608		reg = <0x0 0x03440000 0x0 0x10000>;
609		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
610		clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
611			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
612		clock-names = "sdhci", "tmclk";
613		resets = <&bpmp TEGRA186_RESET_SDMMC3>;
614		reset-names = "sdhci";
615		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
616				<&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
617		interconnect-names = "dma-mem", "write";
618		iommus = <&smmu TEGRA186_SID_SDMMC3>;
619		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
620		pinctrl-0 = <&sdmmc3_3v3>;
621		pinctrl-1 = <&sdmmc3_1v8>;
622		nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
623		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
624		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
625		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
626		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
627		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
628		nvidia,default-tap = <0x5>;
629		nvidia,default-trim = <0xb>;
630		status = "disabled";
631	};
632
633	sdmmc4: mmc@3460000 {
634		compatible = "nvidia,tegra186-sdhci";
635		reg = <0x0 0x03460000 0x0 0x10000>;
636		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
637		clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
638			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
639		clock-names = "sdhci", "tmclk";
640		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
641				  <&bpmp TEGRA186_CLK_PLLC4_VCO>;
642		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
643		resets = <&bpmp TEGRA186_RESET_SDMMC4>;
644		reset-names = "sdhci";
645		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
646				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
647		interconnect-names = "dma-mem", "write";
648		iommus = <&smmu TEGRA186_SID_SDMMC4>;
649		nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
650		nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
651		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
652		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
653		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
654		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
655		nvidia,default-tap = <0x9>;
656		nvidia,default-trim = <0x5>;
657		nvidia,dqs-trim = <63>;
658		mmc-hs400-1_8v;
659		supports-cqe;
660		status = "disabled";
661	};
662
663	hda@3510000 {
664		compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
665		reg = <0x0 0x03510000 0x0 0x10000>;
666		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
667		clocks = <&bpmp TEGRA186_CLK_HDA>,
668			 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
669			 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
670		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
671		resets = <&bpmp TEGRA186_RESET_HDA>,
672			 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
673			 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
674		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
675		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
676		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
677				<&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
678		interconnect-names = "dma-mem", "write";
679		iommus = <&smmu TEGRA186_SID_HDA>;
680		status = "disabled";
681	};
682
683	padctl: padctl@3520000 {
684		compatible = "nvidia,tegra186-xusb-padctl";
685		reg = <0x0 0x03520000 0x0 0x1000>,
686		      <0x0 0x03540000 0x0 0x1000>;
687		reg-names = "padctl", "ao";
688		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
689
690		resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
691		reset-names = "padctl";
692
693		status = "disabled";
694
695		pads {
696			usb2 {
697				clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
698				clock-names = "trk";
699				status = "disabled";
700
701				lanes {
702					usb2-0 {
703						status = "disabled";
704						#phy-cells = <0>;
705					};
706
707					usb2-1 {
708						status = "disabled";
709						#phy-cells = <0>;
710					};
711
712					usb2-2 {
713						status = "disabled";
714						#phy-cells = <0>;
715					};
716				};
717			};
718
719			hsic {
720				clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
721				clock-names = "trk";
722				status = "disabled";
723
724				lanes {
725					hsic-0 {
726						status = "disabled";
727						#phy-cells = <0>;
728					};
729				};
730			};
731
732			usb3 {
733				status = "disabled";
734
735				lanes {
736					usb3-0 {
737						status = "disabled";
738						#phy-cells = <0>;
739					};
740
741					usb3-1 {
742						status = "disabled";
743						#phy-cells = <0>;
744					};
745
746					usb3-2 {
747						status = "disabled";
748						#phy-cells = <0>;
749					};
750				};
751			};
752		};
753
754		ports {
755			usb2-0 {
756				status = "disabled";
757			};
758
759			usb2-1 {
760				status = "disabled";
761			};
762
763			usb2-2 {
764				status = "disabled";
765			};
766
767			hsic-0 {
768				status = "disabled";
769			};
770
771			usb3-0 {
772				status = "disabled";
773			};
774
775			usb3-1 {
776				status = "disabled";
777			};
778
779			usb3-2 {
780				status = "disabled";
781			};
782		};
783	};
784
785	usb@3530000 {
786		compatible = "nvidia,tegra186-xusb";
787		reg = <0x0 0x03530000 0x0 0x8000>,
788		      <0x0 0x03538000 0x0 0x1000>;
789		reg-names = "hcd", "fpci";
790		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
791			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
792		clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
793			 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
794			 <&bpmp TEGRA186_CLK_XUSB_SS>,
795			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
796			 <&bpmp TEGRA186_CLK_CLK_M>,
797			 <&bpmp TEGRA186_CLK_XUSB_FS>,
798			 <&bpmp TEGRA186_CLK_PLLU>,
799			 <&bpmp TEGRA186_CLK_CLK_M>,
800			 <&bpmp TEGRA186_CLK_PLLE>;
801		clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
802			      "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
803			      "pll_u_480m", "clk_m", "pll_e";
804		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
805				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
806		power-domain-names = "xusb_host", "xusb_ss";
807		interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
808				<&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
809		interconnect-names = "dma-mem", "write";
810		iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
811		#address-cells = <1>;
812		#size-cells = <0>;
813		status = "disabled";
814
815		nvidia,xusb-padctl = <&padctl>;
816	};
817
818	usb@3550000 {
819		compatible = "nvidia,tegra186-xudc";
820		reg = <0x0 0x03550000 0x0 0x8000>,
821		      <0x0 0x03558000 0x0 0x1000>;
822		reg-names = "base", "fpci";
823		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
824		clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
825			 <&bpmp TEGRA186_CLK_XUSB_SS>,
826			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
827			 <&bpmp TEGRA186_CLK_XUSB_FS>;
828		clock-names = "dev", "ss", "ss_src", "fs_src";
829		iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
830		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
831				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
832		power-domain-names = "dev", "ss";
833		nvidia,xusb-padctl = <&padctl>;
834		status = "disabled";
835	};
836
837	fuse@3820000 {
838		compatible = "nvidia,tegra186-efuse";
839		reg = <0x0 0x03820000 0x0 0x10000>;
840		clocks = <&bpmp TEGRA186_CLK_FUSE>;
841		clock-names = "fuse";
842	};
843
844	gic: interrupt-controller@3881000 {
845		compatible = "arm,gic-400";
846		#interrupt-cells = <3>;
847		interrupt-controller;
848		reg = <0x0 0x03881000 0x0 0x1000>,
849		      <0x0 0x03882000 0x0 0x2000>,
850		      <0x0 0x03884000 0x0 0x2000>,
851		      <0x0 0x03886000 0x0 0x2000>;
852		interrupts = <GIC_PPI 9
853			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
854		interrupt-parent = <&gic>;
855	};
856
857	cec@3960000 {
858		compatible = "nvidia,tegra186-cec";
859		reg = <0x0 0x03960000 0x0 0x10000>;
860		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
861		clocks = <&bpmp TEGRA186_CLK_CEC>;
862		clock-names = "cec";
863		status = "disabled";
864	};
865
866	hsp_top0: hsp@3c00000 {
867		compatible = "nvidia,tegra186-hsp";
868		reg = <0x0 0x03c00000 0x0 0xa0000>;
869		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
870		interrupt-names = "doorbell";
871		#mbox-cells = <2>;
872		status = "disabled";
873	};
874
875	gen2_i2c: i2c@c240000 {
876		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
877		reg = <0x0 0x0c240000 0x0 0x10000>;
878		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
879		#address-cells = <1>;
880		#size-cells = <0>;
881		clocks = <&bpmp TEGRA186_CLK_I2C2>;
882		clock-names = "div-clk";
883		resets = <&bpmp TEGRA186_RESET_I2C2>;
884		reset-names = "i2c";
885		status = "disabled";
886	};
887
888	gen8_i2c: i2c@c250000 {
889		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
890		reg = <0x0 0x0c250000 0x0 0x10000>;
891		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
892		#address-cells = <1>;
893		#size-cells = <0>;
894		clocks = <&bpmp TEGRA186_CLK_I2C8>;
895		clock-names = "div-clk";
896		resets = <&bpmp TEGRA186_RESET_I2C8>;
897		reset-names = "i2c";
898		status = "disabled";
899	};
900
901	uartc: serial@c280000 {
902		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
903		reg = <0x0 0x0c280000 0x0 0x40>;
904		reg-shift = <2>;
905		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
906		clocks = <&bpmp TEGRA186_CLK_UARTC>;
907		clock-names = "serial";
908		resets = <&bpmp TEGRA186_RESET_UARTC>;
909		reset-names = "serial";
910		status = "disabled";
911	};
912
913	uartg: serial@c290000 {
914		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
915		reg = <0x0 0x0c290000 0x0 0x40>;
916		reg-shift = <2>;
917		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
918		clocks = <&bpmp TEGRA186_CLK_UARTG>;
919		clock-names = "serial";
920		resets = <&bpmp TEGRA186_RESET_UARTG>;
921		reset-names = "serial";
922		status = "disabled";
923	};
924
925	rtc: rtc@c2a0000 {
926		compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
927		reg = <0 0x0c2a0000 0 0x10000>;
928		interrupt-parent = <&pmc>;
929		interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
930		clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
931		clock-names = "rtc";
932		status = "disabled";
933	};
934
935	gpio_aon: gpio@c2f0000 {
936		compatible = "nvidia,tegra186-gpio-aon";
937		reg-names = "security", "gpio";
938		reg = <0x0 0xc2f0000 0x0 0x1000>,
939		      <0x0 0xc2f1000 0x0 0x1000>;
940		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
941		gpio-controller;
942		#gpio-cells = <2>;
943		interrupt-controller;
944		#interrupt-cells = <2>;
945	};
946
947	pmc: pmc@c360000 {
948		compatible = "nvidia,tegra186-pmc";
949		reg = <0 0x0c360000 0 0x10000>,
950		      <0 0x0c370000 0 0x10000>,
951		      <0 0x0c380000 0 0x10000>,
952		      <0 0x0c390000 0 0x10000>;
953		reg-names = "pmc", "wake", "aotag", "scratch";
954
955		#interrupt-cells = <2>;
956		interrupt-controller;
957
958		sdmmc1_3v3: sdmmc1-3v3 {
959			pins = "sdmmc1-hv";
960			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
961		};
962
963		sdmmc1_1v8: sdmmc1-1v8 {
964			pins = "sdmmc1-hv";
965			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
966		};
967
968		sdmmc2_3v3: sdmmc2-3v3 {
969			pins = "sdmmc2-hv";
970			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
971		};
972
973		sdmmc2_1v8: sdmmc2-1v8 {
974			pins = "sdmmc2-hv";
975			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
976		};
977
978		sdmmc3_3v3: sdmmc3-3v3 {
979			pins = "sdmmc3-hv";
980			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
981		};
982
983		sdmmc3_1v8: sdmmc3-1v8 {
984			pins = "sdmmc3-hv";
985			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
986		};
987	};
988
989	ccplex@e000000 {
990		compatible = "nvidia,tegra186-ccplex-cluster";
991		reg = <0x0 0x0e000000 0x0 0x3fffff>;
992
993		nvidia,bpmp = <&bpmp>;
994	};
995
996	pcie@10003000 {
997		compatible = "nvidia,tegra186-pcie";
998		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
999		device_type = "pci";
1000		reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1001		      <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1002		      <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1003		reg-names = "pads", "afi", "cs";
1004
1005		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1006			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1007		interrupt-names = "intr", "msi";
1008
1009		#interrupt-cells = <1>;
1010		interrupt-map-mask = <0 0 0 0>;
1011		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1012
1013		bus-range = <0x00 0xff>;
1014		#address-cells = <3>;
1015		#size-cells = <2>;
1016
1017		ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1018			 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1019			 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1020			 <0x01000000 0 0x0        0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1021			 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1022			 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1023
1024		clocks = <&bpmp TEGRA186_CLK_PCIE>,
1025			 <&bpmp TEGRA186_CLK_AFI>,
1026			 <&bpmp TEGRA186_CLK_PLLE>;
1027		clock-names = "pex", "afi", "pll_e";
1028
1029		resets = <&bpmp TEGRA186_RESET_PCIE>,
1030			 <&bpmp TEGRA186_RESET_AFI>,
1031			 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1032		reset-names = "pex", "afi", "pcie_x";
1033
1034		interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
1035				<&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
1036		interconnect-names = "dma-mem", "write";
1037
1038		iommus = <&smmu TEGRA186_SID_AFI>;
1039		iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1040		iommu-map-mask = <0x0>;
1041
1042		status = "disabled";
1043
1044		pci@1,0 {
1045			device_type = "pci";
1046			assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1047			reg = <0x000800 0 0 0 0>;
1048			status = "disabled";
1049
1050			#address-cells = <3>;
1051			#size-cells = <2>;
1052			ranges;
1053
1054			nvidia,num-lanes = <2>;
1055		};
1056
1057		pci@2,0 {
1058			device_type = "pci";
1059			assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1060			reg = <0x001000 0 0 0 0>;
1061			status = "disabled";
1062
1063			#address-cells = <3>;
1064			#size-cells = <2>;
1065			ranges;
1066
1067			nvidia,num-lanes = <1>;
1068		};
1069
1070		pci@3,0 {
1071			device_type = "pci";
1072			assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1073			reg = <0x001800 0 0 0 0>;
1074			status = "disabled";
1075
1076			#address-cells = <3>;
1077			#size-cells = <2>;
1078			ranges;
1079
1080			nvidia,num-lanes = <1>;
1081		};
1082	};
1083
1084	smmu: iommu@12000000 {
1085		compatible = "arm,mmu-500";
1086		reg = <0 0x12000000 0 0x800000>;
1087		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1088			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1089			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1090			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1091			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1092			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1093			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1094			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1095			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1096			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1097			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1098			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1099			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1100			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1101			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1102			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1103			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1104			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1105			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1106			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1107			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1108			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1109			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1110			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1111			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1112			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1113			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1114			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1115			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1116			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1117			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1118			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1119			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1120			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1121			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1122			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1123			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1124			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1125			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1126			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1127			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1128			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1129			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1130			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1131			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1132			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1133			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1134			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1135			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1136			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1137			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1138			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1139			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1140			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1141			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1142			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1143			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1144			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1145			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1146			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1147			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1148			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1149			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1150			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1151			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1152		stream-match-mask = <0x7f80>;
1153		#global-interrupts = <1>;
1154		#iommu-cells = <1>;
1155	};
1156
1157	host1x@13e00000 {
1158		compatible = "nvidia,tegra186-host1x";
1159		reg = <0x0 0x13e00000 0x0 0x10000>,
1160		      <0x0 0x13e10000 0x0 0x10000>;
1161		reg-names = "hypervisor", "vm";
1162		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1163		             <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1164		interrupt-names = "syncpt", "host1x";
1165		clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1166		clock-names = "host1x";
1167		resets = <&bpmp TEGRA186_RESET_HOST1X>;
1168		reset-names = "host1x";
1169
1170		#address-cells = <1>;
1171		#size-cells = <1>;
1172
1173		ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1174
1175		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
1176		interconnect-names = "dma-mem";
1177
1178		iommus = <&smmu TEGRA186_SID_HOST1X>;
1179
1180		dpaux1: dpaux@15040000 {
1181			compatible = "nvidia,tegra186-dpaux";
1182			reg = <0x15040000 0x10000>;
1183			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1184			clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1185				 <&bpmp TEGRA186_CLK_PLLDP>;
1186			clock-names = "dpaux", "parent";
1187			resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1188			reset-names = "dpaux";
1189			status = "disabled";
1190
1191			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1192
1193			state_dpaux1_aux: pinmux-aux {
1194				groups = "dpaux-io";
1195				function = "aux";
1196			};
1197
1198			state_dpaux1_i2c: pinmux-i2c {
1199				groups = "dpaux-io";
1200				function = "i2c";
1201			};
1202
1203			state_dpaux1_off: pinmux-off {
1204				groups = "dpaux-io";
1205				function = "off";
1206			};
1207
1208			i2c-bus {
1209				#address-cells = <1>;
1210				#size-cells = <0>;
1211			};
1212		};
1213
1214		display-hub@15200000 {
1215			compatible = "nvidia,tegra186-display";
1216			reg = <0x15200000 0x00040000>;
1217			resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1218				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1219				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1220				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1221				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1222				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1223				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1224			reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1225				      "wgrp3", "wgrp4", "wgrp5";
1226			clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1227				 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1228				 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1229			clock-names = "disp", "dsc", "hub";
1230			status = "disabled";
1231
1232			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1233
1234			#address-cells = <1>;
1235			#size-cells = <1>;
1236
1237			ranges = <0x15200000 0x15200000 0x40000>;
1238
1239			display@15200000 {
1240				compatible = "nvidia,tegra186-dc";
1241				reg = <0x15200000 0x10000>;
1242				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1243				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1244				clock-names = "dc";
1245				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1246				reset-names = "dc";
1247
1248				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1249				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1250						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1251				interconnect-names = "dma-mem", "read-1";
1252				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1253
1254				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1255				nvidia,head = <0>;
1256			};
1257
1258			display@15210000 {
1259				compatible = "nvidia,tegra186-dc";
1260				reg = <0x15210000 0x10000>;
1261				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1262				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1263				clock-names = "dc";
1264				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1265				reset-names = "dc";
1266
1267				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1268				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1269						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1270				interconnect-names = "dma-mem", "read-1";
1271				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1272
1273				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1274				nvidia,head = <1>;
1275			};
1276
1277			display@15220000 {
1278				compatible = "nvidia,tegra186-dc";
1279				reg = <0x15220000 0x10000>;
1280				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1281				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1282				clock-names = "dc";
1283				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1284				reset-names = "dc";
1285
1286				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1287				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1288						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1289				interconnect-names = "dma-mem", "read-1";
1290				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1291
1292				nvidia,outputs = <&sor0 &sor1>;
1293				nvidia,head = <2>;
1294			};
1295		};
1296
1297		dsia: dsi@15300000 {
1298			compatible = "nvidia,tegra186-dsi";
1299			reg = <0x15300000 0x10000>;
1300			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1301			clocks = <&bpmp TEGRA186_CLK_DSI>,
1302				 <&bpmp TEGRA186_CLK_DSIA_LP>,
1303				 <&bpmp TEGRA186_CLK_PLLD>;
1304			clock-names = "dsi", "lp", "parent";
1305			resets = <&bpmp TEGRA186_RESET_DSI>;
1306			reset-names = "dsi";
1307			status = "disabled";
1308
1309			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1310		};
1311
1312		vic@15340000 {
1313			compatible = "nvidia,tegra186-vic";
1314			reg = <0x15340000 0x40000>;
1315			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1316			clocks = <&bpmp TEGRA186_CLK_VIC>;
1317			clock-names = "vic";
1318			resets = <&bpmp TEGRA186_RESET_VIC>;
1319			reset-names = "vic";
1320
1321			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1322			interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
1323					<&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
1324			interconnect-names = "dma-mem", "write";
1325			iommus = <&smmu TEGRA186_SID_VIC>;
1326		};
1327
1328		dsib: dsi@15400000 {
1329			compatible = "nvidia,tegra186-dsi";
1330			reg = <0x15400000 0x10000>;
1331			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1332			clocks = <&bpmp TEGRA186_CLK_DSIB>,
1333				 <&bpmp TEGRA186_CLK_DSIB_LP>,
1334				 <&bpmp TEGRA186_CLK_PLLD>;
1335			clock-names = "dsi", "lp", "parent";
1336			resets = <&bpmp TEGRA186_RESET_DSIB>;
1337			reset-names = "dsi";
1338			status = "disabled";
1339
1340			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1341		};
1342
1343		sor0: sor@15540000 {
1344			compatible = "nvidia,tegra186-sor";
1345			reg = <0x15540000 0x10000>;
1346			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1347			clocks = <&bpmp TEGRA186_CLK_SOR0>,
1348				 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1349				 <&bpmp TEGRA186_CLK_PLLD2>,
1350				 <&bpmp TEGRA186_CLK_PLLDP>,
1351				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1352				 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1353			clock-names = "sor", "out", "parent", "dp", "safe",
1354				      "pad";
1355			resets = <&bpmp TEGRA186_RESET_SOR0>;
1356			reset-names = "sor";
1357			pinctrl-0 = <&state_dpaux_aux>;
1358			pinctrl-1 = <&state_dpaux_i2c>;
1359			pinctrl-2 = <&state_dpaux_off>;
1360			pinctrl-names = "aux", "i2c", "off";
1361			status = "disabled";
1362
1363			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1364			nvidia,interface = <0>;
1365		};
1366
1367		sor1: sor@15580000 {
1368			compatible = "nvidia,tegra186-sor";
1369			reg = <0x15580000 0x10000>;
1370			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1371			clocks = <&bpmp TEGRA186_CLK_SOR1>,
1372				 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1373				 <&bpmp TEGRA186_CLK_PLLD3>,
1374				 <&bpmp TEGRA186_CLK_PLLDP>,
1375				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1376				 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1377			clock-names = "sor", "out", "parent", "dp", "safe",
1378				      "pad";
1379			resets = <&bpmp TEGRA186_RESET_SOR1>;
1380			reset-names = "sor";
1381			pinctrl-0 = <&state_dpaux1_aux>;
1382			pinctrl-1 = <&state_dpaux1_i2c>;
1383			pinctrl-2 = <&state_dpaux1_off>;
1384			pinctrl-names = "aux", "i2c", "off";
1385			status = "disabled";
1386
1387			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1388			nvidia,interface = <1>;
1389		};
1390
1391		dpaux: dpaux@155c0000 {
1392			compatible = "nvidia,tegra186-dpaux";
1393			reg = <0x155c0000 0x10000>;
1394			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1395			clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1396				 <&bpmp TEGRA186_CLK_PLLDP>;
1397			clock-names = "dpaux", "parent";
1398			resets = <&bpmp TEGRA186_RESET_DPAUX>;
1399			reset-names = "dpaux";
1400			status = "disabled";
1401
1402			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1403
1404			state_dpaux_aux: pinmux-aux {
1405				groups = "dpaux-io";
1406				function = "aux";
1407			};
1408
1409			state_dpaux_i2c: pinmux-i2c {
1410				groups = "dpaux-io";
1411				function = "i2c";
1412			};
1413
1414			state_dpaux_off: pinmux-off {
1415				groups = "dpaux-io";
1416				function = "off";
1417			};
1418
1419			i2c-bus {
1420				#address-cells = <1>;
1421				#size-cells = <0>;
1422			};
1423		};
1424
1425		padctl@15880000 {
1426			compatible = "nvidia,tegra186-dsi-padctl";
1427			reg = <0x15880000 0x10000>;
1428			resets = <&bpmp TEGRA186_RESET_DSI>;
1429			reset-names = "dsi";
1430			status = "disabled";
1431		};
1432
1433		dsic: dsi@15900000 {
1434			compatible = "nvidia,tegra186-dsi";
1435			reg = <0x15900000 0x10000>;
1436			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1437			clocks = <&bpmp TEGRA186_CLK_DSIC>,
1438				 <&bpmp TEGRA186_CLK_DSIC_LP>,
1439				 <&bpmp TEGRA186_CLK_PLLD>;
1440			clock-names = "dsi", "lp", "parent";
1441			resets = <&bpmp TEGRA186_RESET_DSIC>;
1442			reset-names = "dsi";
1443			status = "disabled";
1444
1445			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1446		};
1447
1448		dsid: dsi@15940000 {
1449			compatible = "nvidia,tegra186-dsi";
1450			reg = <0x15940000 0x10000>;
1451			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1452			clocks = <&bpmp TEGRA186_CLK_DSID>,
1453				 <&bpmp TEGRA186_CLK_DSID_LP>,
1454				 <&bpmp TEGRA186_CLK_PLLD>;
1455			clock-names = "dsi", "lp", "parent";
1456			resets = <&bpmp TEGRA186_RESET_DSID>;
1457			reset-names = "dsi";
1458			status = "disabled";
1459
1460			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1461		};
1462	};
1463
1464	gpu@17000000 {
1465		compatible = "nvidia,gp10b";
1466		reg = <0x0 0x17000000 0x0 0x1000000>,
1467		      <0x0 0x18000000 0x0 0x1000000>;
1468		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1469			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1470		interrupt-names = "stall", "nonstall";
1471
1472		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1473			 <&bpmp TEGRA186_CLK_GPU>;
1474		clock-names = "gpu", "pwr";
1475		resets = <&bpmp TEGRA186_RESET_GPU>;
1476		reset-names = "gpu";
1477		status = "disabled";
1478
1479		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1480		interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
1481				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
1482				<&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
1483				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
1484		interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1485	};
1486
1487	sram@30000000 {
1488		compatible = "nvidia,tegra186-sysram", "mmio-sram";
1489		reg = <0x0 0x30000000 0x0 0x50000>;
1490		#address-cells = <1>;
1491		#size-cells = <1>;
1492		ranges = <0x0 0x0 0x30000000 0x50000>;
1493
1494		cpu_bpmp_tx: sram@4e000 {
1495			reg = <0x4e000 0x1000>;
1496			label = "cpu-bpmp-tx";
1497			pool;
1498		};
1499
1500		cpu_bpmp_rx: sram@4f000 {
1501			reg = <0x4f000 0x1000>;
1502			label = "cpu-bpmp-rx";
1503			pool;
1504		};
1505	};
1506
1507	sata@3507000 {
1508		compatible = "nvidia,tegra186-ahci";
1509		reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
1510		      <0x0 0x03500000 0x0 0x00007000>, /* SATA */
1511		      <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
1512		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1513
1514		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
1515		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,
1516				<&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;
1517		interconnect-names = "dma-mem", "write";
1518		iommus = <&smmu TEGRA186_SID_SATA>;
1519
1520		clocks = <&bpmp TEGRA186_CLK_SATA>,
1521			 <&bpmp TEGRA186_CLK_SATA_OOB>;
1522		clock-names = "sata", "sata-oob";
1523		assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
1524				  <&bpmp TEGRA186_CLK_SATA_OOB>;
1525		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
1526					 <&bpmp TEGRA186_CLK_PLLP>;
1527		assigned-clock-rates = <102000000>,
1528				       <204000000>;
1529		resets = <&bpmp TEGRA186_RESET_SATA>,
1530			<&bpmp TEGRA186_RESET_SATACOLD>;
1531		reset-names = "sata", "sata-cold";
1532		status = "disabled";
1533	};
1534
1535	bpmp: bpmp {
1536		compatible = "nvidia,tegra186-bpmp";
1537		interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
1538				<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
1539				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
1540				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
1541		interconnect-names = "read", "write", "dma-mem", "dma-write";
1542		iommus = <&smmu TEGRA186_SID_BPMP>;
1543		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1544				    TEGRA_HSP_DB_MASTER_BPMP>;
1545		shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1546		#clock-cells = <1>;
1547		#reset-cells = <1>;
1548		#power-domain-cells = <1>;
1549
1550		bpmp_i2c: i2c {
1551			compatible = "nvidia,tegra186-bpmp-i2c";
1552			nvidia,bpmp-bus-id = <5>;
1553			#address-cells = <1>;
1554			#size-cells = <0>;
1555			status = "disabled";
1556		};
1557
1558		bpmp_thermal: thermal {
1559			compatible = "nvidia,tegra186-bpmp-thermal";
1560			#thermal-sensor-cells = <1>;
1561		};
1562	};
1563
1564	cpus {
1565		#address-cells = <1>;
1566		#size-cells = <0>;
1567
1568		denver_0: cpu@0 {
1569			compatible = "nvidia,tegra186-denver";
1570			device_type = "cpu";
1571			i-cache-size = <0x20000>;
1572			i-cache-line-size = <64>;
1573			i-cache-sets = <512>;
1574			d-cache-size = <0x10000>;
1575			d-cache-line-size = <64>;
1576			d-cache-sets = <256>;
1577			next-level-cache = <&L2_DENVER>;
1578			reg = <0x000>;
1579		};
1580
1581		denver_1: cpu@1 {
1582			compatible = "nvidia,tegra186-denver";
1583			device_type = "cpu";
1584			i-cache-size = <0x20000>;
1585			i-cache-line-size = <64>;
1586			i-cache-sets = <512>;
1587			d-cache-size = <0x10000>;
1588			d-cache-line-size = <64>;
1589			d-cache-sets = <256>;
1590			next-level-cache = <&L2_DENVER>;
1591			reg = <0x001>;
1592		};
1593
1594		ca57_0: cpu@2 {
1595			compatible = "arm,cortex-a57";
1596			device_type = "cpu";
1597			i-cache-size = <0xC000>;
1598			i-cache-line-size = <64>;
1599			i-cache-sets = <256>;
1600			d-cache-size = <0x8000>;
1601			d-cache-line-size = <64>;
1602			d-cache-sets = <256>;
1603			next-level-cache = <&L2_A57>;
1604			reg = <0x100>;
1605		};
1606
1607		ca57_1: cpu@3 {
1608			compatible = "arm,cortex-a57";
1609			device_type = "cpu";
1610			i-cache-size = <0xC000>;
1611			i-cache-line-size = <64>;
1612			i-cache-sets = <256>;
1613			d-cache-size = <0x8000>;
1614			d-cache-line-size = <64>;
1615			d-cache-sets = <256>;
1616			next-level-cache = <&L2_A57>;
1617			reg = <0x101>;
1618		};
1619
1620		ca57_2: cpu@4 {
1621			compatible = "arm,cortex-a57";
1622			device_type = "cpu";
1623			i-cache-size = <0xC000>;
1624			i-cache-line-size = <64>;
1625			i-cache-sets = <256>;
1626			d-cache-size = <0x8000>;
1627			d-cache-line-size = <64>;
1628			d-cache-sets = <256>;
1629			next-level-cache = <&L2_A57>;
1630			reg = <0x102>;
1631		};
1632
1633		ca57_3: cpu@5 {
1634			compatible = "arm,cortex-a57";
1635			device_type = "cpu";
1636			i-cache-size = <0xC000>;
1637			i-cache-line-size = <64>;
1638			i-cache-sets = <256>;
1639			d-cache-size = <0x8000>;
1640			d-cache-line-size = <64>;
1641			d-cache-sets = <256>;
1642			next-level-cache = <&L2_A57>;
1643			reg = <0x103>;
1644		};
1645
1646		L2_DENVER: l2-cache0 {
1647			compatible = "cache";
1648			cache-unified;
1649			cache-level = <2>;
1650			cache-size = <0x200000>;
1651			cache-line-size = <64>;
1652			cache-sets = <2048>;
1653		};
1654
1655		L2_A57: l2-cache1 {
1656			compatible = "cache";
1657			cache-unified;
1658			cache-level = <2>;
1659			cache-size = <0x200000>;
1660			cache-line-size = <64>;
1661			cache-sets = <2048>;
1662		};
1663	};
1664
1665	pmu_denver {
1666		compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
1667		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1668			     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1669		interrupt-affinity = <&denver_0 &denver_1>;
1670	};
1671
1672	pmu_a57 {
1673		compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
1674		interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1675			     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1676			     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1677			     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1678		interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
1679	};
1680
1681	sound {
1682		status = "disabled";
1683
1684		clocks = <&bpmp TEGRA186_CLK_PLLA>,
1685			 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
1686		clock-names = "pll_a", "plla_out0";
1687		assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
1688				  <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
1689				  <&bpmp TEGRA186_CLK_AUD_MCLK>;
1690		assigned-clock-parents = <0>,
1691					 <&bpmp TEGRA186_CLK_PLLA>,
1692					 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
1693		/*
1694		 * PLLA supports dynamic ramp. Below initial rate is chosen
1695		 * for this to work and oscillate between base rates required
1696		 * for 8x and 11.025x sample rate streams.
1697		 */
1698		assigned-clock-rates = <258000000>;
1699
1700		iommus = <&smmu TEGRA186_SID_APE>;
1701	};
1702
1703	thermal-zones {
1704		a57 {
1705			polling-delay = <0>;
1706			polling-delay-passive = <1000>;
1707
1708			thermal-sensors =
1709				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
1710
1711			trips {
1712				critical {
1713					temperature = <101000>;
1714					hysteresis = <0>;
1715					type = "critical";
1716				};
1717			};
1718
1719			cooling-maps {
1720			};
1721		};
1722
1723		denver {
1724			polling-delay = <0>;
1725			polling-delay-passive = <1000>;
1726
1727			thermal-sensors =
1728				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
1729
1730			trips {
1731				critical {
1732					temperature = <101000>;
1733					hysteresis = <0>;
1734					type = "critical";
1735				};
1736			};
1737
1738			cooling-maps {
1739			};
1740		};
1741
1742		gpu {
1743			polling-delay = <0>;
1744			polling-delay-passive = <1000>;
1745
1746			thermal-sensors =
1747				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
1748
1749			trips {
1750				critical {
1751					temperature = <101000>;
1752					hysteresis = <0>;
1753					type = "critical";
1754				};
1755			};
1756
1757			cooling-maps {
1758			};
1759		};
1760
1761		pll {
1762			polling-delay = <0>;
1763			polling-delay-passive = <1000>;
1764
1765			thermal-sensors =
1766				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
1767
1768			trips {
1769				critical {
1770					temperature = <101000>;
1771					hysteresis = <0>;
1772					type = "critical";
1773				};
1774			};
1775
1776			cooling-maps {
1777			};
1778		};
1779
1780		always_on {
1781			polling-delay = <0>;
1782			polling-delay-passive = <1000>;
1783
1784			thermal-sensors =
1785				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
1786
1787			trips {
1788				critical {
1789					temperature = <101000>;
1790					hysteresis = <0>;
1791					type = "critical";
1792				};
1793			};
1794
1795			cooling-maps {
1796			};
1797		};
1798	};
1799
1800	timer {
1801		compatible = "arm,armv8-timer";
1802		interrupts = <GIC_PPI 13
1803				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1804			     <GIC_PPI 14
1805				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1806			     <GIC_PPI 11
1807				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1808			     <GIC_PPI 10
1809				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1810		interrupt-parent = <&gic>;
1811		always-on;
1812	};
1813};
1814