1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 aconnect@2900000 { 77 compatible = "nvidia,tegra186-aconnect", 78 "nvidia,tegra210-aconnect"; 79 clocks = <&bpmp TEGRA186_CLK_APE>, 80 <&bpmp TEGRA186_CLK_APB2APE>; 81 clock-names = "ape", "apb2ape"; 82 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges = <0x02900000 0x0 0x02900000 0x200000>; 86 status = "disabled"; 87 88 adma: dma-controller@2930000 { 89 compatible = "nvidia,tegra186-adma"; 90 reg = <0x02930000 0x20000>; 91 interrupt-parent = <&agic>; 92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 124 #dma-cells = <1>; 125 clocks = <&bpmp TEGRA186_CLK_AHUB>; 126 clock-names = "d_audio"; 127 status = "disabled"; 128 }; 129 130 agic: interrupt-controller@2a40000 { 131 compatible = "nvidia,tegra186-agic", 132 "nvidia,tegra210-agic"; 133 #interrupt-cells = <3>; 134 interrupt-controller; 135 reg = <0x02a41000 0x1000>, 136 <0x02a42000 0x2000>; 137 interrupts = <GIC_SPI 145 138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA186_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 144 tegra_ahub: ahub@2900800 { 145 compatible = "nvidia,tegra186-ahub"; 146 reg = <0x02900800 0x800>; 147 clocks = <&bpmp TEGRA186_CLK_AHUB>; 148 clock-names = "ahub"; 149 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 150 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 ranges = <0x02900800 0x02900800 0x11800>; 154 status = "disabled"; 155 156 tegra_admaif: admaif@290f000 { 157 compatible = "nvidia,tegra186-admaif"; 158 reg = <0x0290f000 0x1000>; 159 dmas = <&adma 1>, <&adma 1>, 160 <&adma 2>, <&adma 2>, 161 <&adma 3>, <&adma 3>, 162 <&adma 4>, <&adma 4>, 163 <&adma 5>, <&adma 5>, 164 <&adma 6>, <&adma 6>, 165 <&adma 7>, <&adma 7>, 166 <&adma 8>, <&adma 8>, 167 <&adma 9>, <&adma 9>, 168 <&adma 10>, <&adma 10>, 169 <&adma 11>, <&adma 11>, 170 <&adma 12>, <&adma 12>, 171 <&adma 13>, <&adma 13>, 172 <&adma 14>, <&adma 14>, 173 <&adma 15>, <&adma 15>, 174 <&adma 16>, <&adma 16>, 175 <&adma 17>, <&adma 17>, 176 <&adma 18>, <&adma 18>, 177 <&adma 19>, <&adma 19>, 178 <&adma 20>, <&adma 20>; 179 dma-names = "rx1", "tx1", 180 "rx2", "tx2", 181 "rx3", "tx3", 182 "rx4", "tx4", 183 "rx5", "tx5", 184 "rx6", "tx6", 185 "rx7", "tx7", 186 "rx8", "tx8", 187 "rx9", "tx9", 188 "rx10", "tx10", 189 "rx11", "tx11", 190 "rx12", "tx12", 191 "rx13", "tx13", 192 "rx14", "tx14", 193 "rx15", "tx15", 194 "rx16", "tx16", 195 "rx17", "tx17", 196 "rx18", "tx18", 197 "rx19", "tx19", 198 "rx20", "tx20"; 199 status = "disabled"; 200 }; 201 202 tegra_i2s1: i2s@2901000 { 203 compatible = "nvidia,tegra186-i2s", 204 "nvidia,tegra210-i2s"; 205 reg = <0x2901000 0x100>; 206 clocks = <&bpmp TEGRA186_CLK_I2S1>, 207 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 208 clock-names = "i2s", "sync_input"; 209 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 210 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 211 assigned-clock-rates = <1536000>; 212 sound-name-prefix = "I2S1"; 213 status = "disabled"; 214 }; 215 216 tegra_i2s2: i2s@2901100 { 217 compatible = "nvidia,tegra186-i2s", 218 "nvidia,tegra210-i2s"; 219 reg = <0x2901100 0x100>; 220 clocks = <&bpmp TEGRA186_CLK_I2S2>, 221 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 222 clock-names = "i2s", "sync_input"; 223 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 224 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 225 assigned-clock-rates = <1536000>; 226 sound-name-prefix = "I2S2"; 227 status = "disabled"; 228 }; 229 230 tegra_i2s3: i2s@2901200 { 231 compatible = "nvidia,tegra186-i2s", 232 "nvidia,tegra210-i2s"; 233 reg = <0x2901200 0x100>; 234 clocks = <&bpmp TEGRA186_CLK_I2S3>, 235 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 236 clock-names = "i2s", "sync_input"; 237 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 238 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 239 assigned-clock-rates = <1536000>; 240 sound-name-prefix = "I2S3"; 241 status = "disabled"; 242 }; 243 244 tegra_i2s4: i2s@2901300 { 245 compatible = "nvidia,tegra186-i2s", 246 "nvidia,tegra210-i2s"; 247 reg = <0x2901300 0x100>; 248 clocks = <&bpmp TEGRA186_CLK_I2S4>, 249 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 250 clock-names = "i2s", "sync_input"; 251 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253 assigned-clock-rates = <1536000>; 254 sound-name-prefix = "I2S4"; 255 status = "disabled"; 256 }; 257 258 tegra_i2s5: i2s@2901400 { 259 compatible = "nvidia,tegra186-i2s", 260 "nvidia,tegra210-i2s"; 261 reg = <0x2901400 0x100>; 262 clocks = <&bpmp TEGRA186_CLK_I2S5>, 263 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 264 clock-names = "i2s", "sync_input"; 265 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267 assigned-clock-rates = <1536000>; 268 sound-name-prefix = "I2S5"; 269 status = "disabled"; 270 }; 271 272 tegra_i2s6: i2s@2901500 { 273 compatible = "nvidia,tegra186-i2s", 274 "nvidia,tegra210-i2s"; 275 reg = <0x2901500 0x100>; 276 clocks = <&bpmp TEGRA186_CLK_I2S6>, 277 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 278 clock-names = "i2s", "sync_input"; 279 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281 assigned-clock-rates = <1536000>; 282 sound-name-prefix = "I2S6"; 283 status = "disabled"; 284 }; 285 286 tegra_dmic1: dmic@2904000 { 287 compatible = "nvidia,tegra210-dmic"; 288 reg = <0x2904000 0x100>; 289 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 290 clock-names = "dmic"; 291 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 292 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 293 assigned-clock-rates = <3072000>; 294 sound-name-prefix = "DMIC1"; 295 status = "disabled"; 296 }; 297 298 tegra_dmic2: dmic@2904100 { 299 compatible = "nvidia,tegra210-dmic"; 300 reg = <0x2904100 0x100>; 301 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 302 clock-names = "dmic"; 303 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 304 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 305 assigned-clock-rates = <3072000>; 306 sound-name-prefix = "DMIC2"; 307 status = "disabled"; 308 }; 309 310 tegra_dmic3: dmic@2904200 { 311 compatible = "nvidia,tegra210-dmic"; 312 reg = <0x2904200 0x100>; 313 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 314 clock-names = "dmic"; 315 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 316 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 317 assigned-clock-rates = <3072000>; 318 sound-name-prefix = "DMIC3"; 319 status = "disabled"; 320 }; 321 322 tegra_dmic4: dmic@2904300 { 323 compatible = "nvidia,tegra210-dmic"; 324 reg = <0x2904300 0x100>; 325 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 326 clock-names = "dmic"; 327 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 328 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 329 assigned-clock-rates = <3072000>; 330 sound-name-prefix = "DMIC4"; 331 status = "disabled"; 332 }; 333 334 tegra_dspk1: dspk@2905000 { 335 compatible = "nvidia,tegra186-dspk"; 336 reg = <0x2905000 0x100>; 337 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 338 clock-names = "dspk"; 339 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 340 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 341 assigned-clock-rates = <12288000>; 342 sound-name-prefix = "DSPK1"; 343 status = "disabled"; 344 }; 345 346 tegra_dspk2: dspk@2905100 { 347 compatible = "nvidia,tegra186-dspk"; 348 reg = <0x2905100 0x100>; 349 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 350 clock-names = "dspk"; 351 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 352 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 353 assigned-clock-rates = <12288000>; 354 sound-name-prefix = "DSPK2"; 355 status = "disabled"; 356 }; 357 }; 358 }; 359 360 mc: memory-controller@2c00000 { 361 compatible = "nvidia,tegra186-mc"; 362 reg = <0x0 0x02c00000 0x0 0xb0000>; 363 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 364 status = "disabled"; 365 366 #interconnect-cells = <1>; 367 #address-cells = <2>; 368 #size-cells = <2>; 369 370 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 371 372 /* 373 * Memory clients have access to all 40 bits that the memory 374 * controller can address. 375 */ 376 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 377 378 emc: external-memory-controller@2c60000 { 379 compatible = "nvidia,tegra186-emc"; 380 reg = <0x0 0x02c60000 0x0 0x50000>; 381 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&bpmp TEGRA186_CLK_EMC>; 383 clock-names = "emc"; 384 385 #interconnect-cells = <0>; 386 387 nvidia,bpmp = <&bpmp>; 388 }; 389 }; 390 391 uarta: serial@3100000 { 392 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 393 reg = <0x0 0x03100000 0x0 0x40>; 394 reg-shift = <2>; 395 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&bpmp TEGRA186_CLK_UARTA>; 397 clock-names = "serial"; 398 resets = <&bpmp TEGRA186_RESET_UARTA>; 399 reset-names = "serial"; 400 status = "disabled"; 401 }; 402 403 uartb: serial@3110000 { 404 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 405 reg = <0x0 0x03110000 0x0 0x40>; 406 reg-shift = <2>; 407 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&bpmp TEGRA186_CLK_UARTB>; 409 clock-names = "serial"; 410 resets = <&bpmp TEGRA186_RESET_UARTB>; 411 reset-names = "serial"; 412 status = "disabled"; 413 }; 414 415 uartd: serial@3130000 { 416 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 417 reg = <0x0 0x03130000 0x0 0x40>; 418 reg-shift = <2>; 419 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&bpmp TEGRA186_CLK_UARTD>; 421 clock-names = "serial"; 422 resets = <&bpmp TEGRA186_RESET_UARTD>; 423 reset-names = "serial"; 424 status = "disabled"; 425 }; 426 427 uarte: serial@3140000 { 428 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 429 reg = <0x0 0x03140000 0x0 0x40>; 430 reg-shift = <2>; 431 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&bpmp TEGRA186_CLK_UARTE>; 433 clock-names = "serial"; 434 resets = <&bpmp TEGRA186_RESET_UARTE>; 435 reset-names = "serial"; 436 status = "disabled"; 437 }; 438 439 uartf: serial@3150000 { 440 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 441 reg = <0x0 0x03150000 0x0 0x40>; 442 reg-shift = <2>; 443 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&bpmp TEGRA186_CLK_UARTF>; 445 clock-names = "serial"; 446 resets = <&bpmp TEGRA186_RESET_UARTF>; 447 reset-names = "serial"; 448 status = "disabled"; 449 }; 450 451 gen1_i2c: i2c@3160000 { 452 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 453 reg = <0x0 0x03160000 0x0 0x10000>; 454 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 clocks = <&bpmp TEGRA186_CLK_I2C1>; 458 clock-names = "div-clk"; 459 resets = <&bpmp TEGRA186_RESET_I2C1>; 460 reset-names = "i2c"; 461 status = "disabled"; 462 }; 463 464 cam_i2c: i2c@3180000 { 465 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 466 reg = <0x0 0x03180000 0x0 0x10000>; 467 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 clocks = <&bpmp TEGRA186_CLK_I2C3>; 471 clock-names = "div-clk"; 472 resets = <&bpmp TEGRA186_RESET_I2C3>; 473 reset-names = "i2c"; 474 status = "disabled"; 475 }; 476 477 /* shares pads with dpaux1 */ 478 dp_aux_ch1_i2c: i2c@3190000 { 479 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 480 reg = <0x0 0x03190000 0x0 0x10000>; 481 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 clocks = <&bpmp TEGRA186_CLK_I2C4>; 485 clock-names = "div-clk"; 486 resets = <&bpmp TEGRA186_RESET_I2C4>; 487 reset-names = "i2c"; 488 pinctrl-names = "default", "idle"; 489 pinctrl-0 = <&state_dpaux1_i2c>; 490 pinctrl-1 = <&state_dpaux1_off>; 491 status = "disabled"; 492 }; 493 494 /* controlled by BPMP, should not be enabled */ 495 pwr_i2c: i2c@31a0000 { 496 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 497 reg = <0x0 0x031a0000 0x0 0x10000>; 498 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 clocks = <&bpmp TEGRA186_CLK_I2C5>; 502 clock-names = "div-clk"; 503 resets = <&bpmp TEGRA186_RESET_I2C5>; 504 reset-names = "i2c"; 505 status = "disabled"; 506 }; 507 508 /* shares pads with dpaux0 */ 509 dp_aux_ch0_i2c: i2c@31b0000 { 510 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 511 reg = <0x0 0x031b0000 0x0 0x10000>; 512 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 clocks = <&bpmp TEGRA186_CLK_I2C6>; 516 clock-names = "div-clk"; 517 resets = <&bpmp TEGRA186_RESET_I2C6>; 518 reset-names = "i2c"; 519 pinctrl-names = "default", "idle"; 520 pinctrl-0 = <&state_dpaux_i2c>; 521 pinctrl-1 = <&state_dpaux_off>; 522 status = "disabled"; 523 }; 524 525 gen7_i2c: i2c@31c0000 { 526 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 527 reg = <0x0 0x031c0000 0x0 0x10000>; 528 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 clocks = <&bpmp TEGRA186_CLK_I2C7>; 532 clock-names = "div-clk"; 533 resets = <&bpmp TEGRA186_RESET_I2C7>; 534 reset-names = "i2c"; 535 status = "disabled"; 536 }; 537 538 gen9_i2c: i2c@31e0000 { 539 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 540 reg = <0x0 0x031e0000 0x0 0x10000>; 541 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 clocks = <&bpmp TEGRA186_CLK_I2C9>; 545 clock-names = "div-clk"; 546 resets = <&bpmp TEGRA186_RESET_I2C9>; 547 reset-names = "i2c"; 548 status = "disabled"; 549 }; 550 551 pwm1: pwm@3280000 { 552 compatible = "nvidia,tegra186-pwm"; 553 reg = <0x0 0x3280000 0x0 0x10000>; 554 clocks = <&bpmp TEGRA186_CLK_PWM1>; 555 clock-names = "pwm"; 556 resets = <&bpmp TEGRA186_RESET_PWM1>; 557 reset-names = "pwm"; 558 status = "disabled"; 559 #pwm-cells = <2>; 560 }; 561 562 pwm2: pwm@3290000 { 563 compatible = "nvidia,tegra186-pwm"; 564 reg = <0x0 0x3290000 0x0 0x10000>; 565 clocks = <&bpmp TEGRA186_CLK_PWM2>; 566 clock-names = "pwm"; 567 resets = <&bpmp TEGRA186_RESET_PWM2>; 568 reset-names = "pwm"; 569 status = "disabled"; 570 #pwm-cells = <2>; 571 }; 572 573 pwm3: pwm@32a0000 { 574 compatible = "nvidia,tegra186-pwm"; 575 reg = <0x0 0x32a0000 0x0 0x10000>; 576 clocks = <&bpmp TEGRA186_CLK_PWM3>; 577 clock-names = "pwm"; 578 resets = <&bpmp TEGRA186_RESET_PWM3>; 579 reset-names = "pwm"; 580 status = "disabled"; 581 #pwm-cells = <2>; 582 }; 583 584 pwm5: pwm@32c0000 { 585 compatible = "nvidia,tegra186-pwm"; 586 reg = <0x0 0x32c0000 0x0 0x10000>; 587 clocks = <&bpmp TEGRA186_CLK_PWM5>; 588 clock-names = "pwm"; 589 resets = <&bpmp TEGRA186_RESET_PWM5>; 590 reset-names = "pwm"; 591 status = "disabled"; 592 #pwm-cells = <2>; 593 }; 594 595 pwm6: pwm@32d0000 { 596 compatible = "nvidia,tegra186-pwm"; 597 reg = <0x0 0x32d0000 0x0 0x10000>; 598 clocks = <&bpmp TEGRA186_CLK_PWM6>; 599 clock-names = "pwm"; 600 resets = <&bpmp TEGRA186_RESET_PWM6>; 601 reset-names = "pwm"; 602 status = "disabled"; 603 #pwm-cells = <2>; 604 }; 605 606 pwm7: pwm@32e0000 { 607 compatible = "nvidia,tegra186-pwm"; 608 reg = <0x0 0x32e0000 0x0 0x10000>; 609 clocks = <&bpmp TEGRA186_CLK_PWM7>; 610 clock-names = "pwm"; 611 resets = <&bpmp TEGRA186_RESET_PWM7>; 612 reset-names = "pwm"; 613 status = "disabled"; 614 #pwm-cells = <2>; 615 }; 616 617 pwm8: pwm@32f0000 { 618 compatible = "nvidia,tegra186-pwm"; 619 reg = <0x0 0x32f0000 0x0 0x10000>; 620 clocks = <&bpmp TEGRA186_CLK_PWM8>; 621 clock-names = "pwm"; 622 resets = <&bpmp TEGRA186_RESET_PWM8>; 623 reset-names = "pwm"; 624 status = "disabled"; 625 #pwm-cells = <2>; 626 }; 627 628 sdmmc1: mmc@3400000 { 629 compatible = "nvidia,tegra186-sdhci"; 630 reg = <0x0 0x03400000 0x0 0x10000>; 631 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 633 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 634 clock-names = "sdhci", "tmclk"; 635 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 636 reset-names = "sdhci"; 637 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 638 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 639 interconnect-names = "dma-mem", "write"; 640 iommus = <&smmu TEGRA186_SID_SDMMC1>; 641 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 642 pinctrl-0 = <&sdmmc1_3v3>; 643 pinctrl-1 = <&sdmmc1_1v8>; 644 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 645 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 646 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 647 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 648 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 649 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 650 nvidia,default-tap = <0x5>; 651 nvidia,default-trim = <0xb>; 652 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 653 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 654 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 655 status = "disabled"; 656 }; 657 658 sdmmc2: mmc@3420000 { 659 compatible = "nvidia,tegra186-sdhci"; 660 reg = <0x0 0x03420000 0x0 0x10000>; 661 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 663 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 664 clock-names = "sdhci", "tmclk"; 665 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 666 reset-names = "sdhci"; 667 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 668 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 669 interconnect-names = "dma-mem", "write"; 670 iommus = <&smmu TEGRA186_SID_SDMMC2>; 671 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 672 pinctrl-0 = <&sdmmc2_3v3>; 673 pinctrl-1 = <&sdmmc2_1v8>; 674 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 675 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 676 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 677 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 678 nvidia,default-tap = <0x5>; 679 nvidia,default-trim = <0xb>; 680 status = "disabled"; 681 }; 682 683 sdmmc3: mmc@3440000 { 684 compatible = "nvidia,tegra186-sdhci"; 685 reg = <0x0 0x03440000 0x0 0x10000>; 686 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 688 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 689 clock-names = "sdhci", "tmclk"; 690 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 691 reset-names = "sdhci"; 692 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 693 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 694 interconnect-names = "dma-mem", "write"; 695 iommus = <&smmu TEGRA186_SID_SDMMC3>; 696 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 697 pinctrl-0 = <&sdmmc3_3v3>; 698 pinctrl-1 = <&sdmmc3_1v8>; 699 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 700 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 701 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 702 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 703 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 704 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 705 nvidia,default-tap = <0x5>; 706 nvidia,default-trim = <0xb>; 707 status = "disabled"; 708 }; 709 710 sdmmc4: mmc@3460000 { 711 compatible = "nvidia,tegra186-sdhci"; 712 reg = <0x0 0x03460000 0x0 0x10000>; 713 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 715 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 716 clock-names = "sdhci", "tmclk"; 717 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 718 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 719 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 720 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 721 reset-names = "sdhci"; 722 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 723 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 724 interconnect-names = "dma-mem", "write"; 725 iommus = <&smmu TEGRA186_SID_SDMMC4>; 726 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 727 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 728 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 729 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 730 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 731 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 732 nvidia,default-tap = <0x9>; 733 nvidia,default-trim = <0x5>; 734 nvidia,dqs-trim = <63>; 735 mmc-hs400-1_8v; 736 supports-cqe; 737 status = "disabled"; 738 }; 739 740 hda@3510000 { 741 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 742 reg = <0x0 0x03510000 0x0 0x10000>; 743 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&bpmp TEGRA186_CLK_HDA>, 745 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 746 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 747 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 748 resets = <&bpmp TEGRA186_RESET_HDA>, 749 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 750 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 751 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 752 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 753 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 754 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 755 interconnect-names = "dma-mem", "write"; 756 iommus = <&smmu TEGRA186_SID_HDA>; 757 status = "disabled"; 758 }; 759 760 padctl: padctl@3520000 { 761 compatible = "nvidia,tegra186-xusb-padctl"; 762 reg = <0x0 0x03520000 0x0 0x1000>, 763 <0x0 0x03540000 0x0 0x1000>; 764 reg-names = "padctl", "ao"; 765 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 766 767 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 768 reset-names = "padctl"; 769 770 status = "disabled"; 771 772 pads { 773 usb2 { 774 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 775 clock-names = "trk"; 776 status = "disabled"; 777 778 lanes { 779 usb2-0 { 780 status = "disabled"; 781 #phy-cells = <0>; 782 }; 783 784 usb2-1 { 785 status = "disabled"; 786 #phy-cells = <0>; 787 }; 788 789 usb2-2 { 790 status = "disabled"; 791 #phy-cells = <0>; 792 }; 793 }; 794 }; 795 796 hsic { 797 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 798 clock-names = "trk"; 799 status = "disabled"; 800 801 lanes { 802 hsic-0 { 803 status = "disabled"; 804 #phy-cells = <0>; 805 }; 806 }; 807 }; 808 809 usb3 { 810 status = "disabled"; 811 812 lanes { 813 usb3-0 { 814 status = "disabled"; 815 #phy-cells = <0>; 816 }; 817 818 usb3-1 { 819 status = "disabled"; 820 #phy-cells = <0>; 821 }; 822 823 usb3-2 { 824 status = "disabled"; 825 #phy-cells = <0>; 826 }; 827 }; 828 }; 829 }; 830 831 ports { 832 usb2-0 { 833 status = "disabled"; 834 }; 835 836 usb2-1 { 837 status = "disabled"; 838 }; 839 840 usb2-2 { 841 status = "disabled"; 842 }; 843 844 hsic-0 { 845 status = "disabled"; 846 }; 847 848 usb3-0 { 849 status = "disabled"; 850 }; 851 852 usb3-1 { 853 status = "disabled"; 854 }; 855 856 usb3-2 { 857 status = "disabled"; 858 }; 859 }; 860 }; 861 862 usb@3530000 { 863 compatible = "nvidia,tegra186-xusb"; 864 reg = <0x0 0x03530000 0x0 0x8000>, 865 <0x0 0x03538000 0x0 0x1000>; 866 reg-names = "hcd", "fpci"; 867 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 870 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 871 <&bpmp TEGRA186_CLK_XUSB_SS>, 872 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 873 <&bpmp TEGRA186_CLK_CLK_M>, 874 <&bpmp TEGRA186_CLK_XUSB_FS>, 875 <&bpmp TEGRA186_CLK_PLLU>, 876 <&bpmp TEGRA186_CLK_CLK_M>, 877 <&bpmp TEGRA186_CLK_PLLE>; 878 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 879 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 880 "pll_u_480m", "clk_m", "pll_e"; 881 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 882 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 883 power-domain-names = "xusb_host", "xusb_ss"; 884 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 885 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 886 interconnect-names = "dma-mem", "write"; 887 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 status = "disabled"; 891 892 nvidia,xusb-padctl = <&padctl>; 893 }; 894 895 usb@3550000 { 896 compatible = "nvidia,tegra186-xudc"; 897 reg = <0x0 0x03550000 0x0 0x8000>, 898 <0x0 0x03558000 0x0 0x1000>; 899 reg-names = "base", "fpci"; 900 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 902 <&bpmp TEGRA186_CLK_XUSB_SS>, 903 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 904 <&bpmp TEGRA186_CLK_XUSB_FS>; 905 clock-names = "dev", "ss", "ss_src", "fs_src"; 906 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 907 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 908 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 909 power-domain-names = "dev", "ss"; 910 nvidia,xusb-padctl = <&padctl>; 911 status = "disabled"; 912 }; 913 914 fuse@3820000 { 915 compatible = "nvidia,tegra186-efuse"; 916 reg = <0x0 0x03820000 0x0 0x10000>; 917 clocks = <&bpmp TEGRA186_CLK_FUSE>; 918 clock-names = "fuse"; 919 }; 920 921 gic: interrupt-controller@3881000 { 922 compatible = "arm,gic-400"; 923 #interrupt-cells = <3>; 924 interrupt-controller; 925 reg = <0x0 0x03881000 0x0 0x1000>, 926 <0x0 0x03882000 0x0 0x2000>, 927 <0x0 0x03884000 0x0 0x2000>, 928 <0x0 0x03886000 0x0 0x2000>; 929 interrupts = <GIC_PPI 9 930 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 931 interrupt-parent = <&gic>; 932 }; 933 934 cec@3960000 { 935 compatible = "nvidia,tegra186-cec"; 936 reg = <0x0 0x03960000 0x0 0x10000>; 937 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&bpmp TEGRA186_CLK_CEC>; 939 clock-names = "cec"; 940 status = "disabled"; 941 }; 942 943 hsp_top0: hsp@3c00000 { 944 compatible = "nvidia,tegra186-hsp"; 945 reg = <0x0 0x03c00000 0x0 0xa0000>; 946 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 947 interrupt-names = "doorbell"; 948 #mbox-cells = <2>; 949 status = "disabled"; 950 }; 951 952 gen2_i2c: i2c@c240000 { 953 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 954 reg = <0x0 0x0c240000 0x0 0x10000>; 955 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 clocks = <&bpmp TEGRA186_CLK_I2C2>; 959 clock-names = "div-clk"; 960 resets = <&bpmp TEGRA186_RESET_I2C2>; 961 reset-names = "i2c"; 962 status = "disabled"; 963 }; 964 965 gen8_i2c: i2c@c250000 { 966 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 967 reg = <0x0 0x0c250000 0x0 0x10000>; 968 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 clocks = <&bpmp TEGRA186_CLK_I2C8>; 972 clock-names = "div-clk"; 973 resets = <&bpmp TEGRA186_RESET_I2C8>; 974 reset-names = "i2c"; 975 status = "disabled"; 976 }; 977 978 uartc: serial@c280000 { 979 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 980 reg = <0x0 0x0c280000 0x0 0x40>; 981 reg-shift = <2>; 982 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&bpmp TEGRA186_CLK_UARTC>; 984 clock-names = "serial"; 985 resets = <&bpmp TEGRA186_RESET_UARTC>; 986 reset-names = "serial"; 987 status = "disabled"; 988 }; 989 990 uartg: serial@c290000 { 991 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 992 reg = <0x0 0x0c290000 0x0 0x40>; 993 reg-shift = <2>; 994 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&bpmp TEGRA186_CLK_UARTG>; 996 clock-names = "serial"; 997 resets = <&bpmp TEGRA186_RESET_UARTG>; 998 reset-names = "serial"; 999 status = "disabled"; 1000 }; 1001 1002 rtc: rtc@c2a0000 { 1003 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1004 reg = <0 0x0c2a0000 0 0x10000>; 1005 interrupt-parent = <&pmc>; 1006 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1008 clock-names = "rtc"; 1009 status = "disabled"; 1010 }; 1011 1012 gpio_aon: gpio@c2f0000 { 1013 compatible = "nvidia,tegra186-gpio-aon"; 1014 reg-names = "security", "gpio"; 1015 reg = <0x0 0xc2f0000 0x0 0x1000>, 1016 <0x0 0xc2f1000 0x0 0x1000>; 1017 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1018 gpio-controller; 1019 #gpio-cells = <2>; 1020 interrupt-controller; 1021 #interrupt-cells = <2>; 1022 }; 1023 1024 pwm4: pwm@c340000 { 1025 compatible = "nvidia,tegra186-pwm"; 1026 reg = <0x0 0xc340000 0x0 0x10000>; 1027 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1028 clock-names = "pwm"; 1029 resets = <&bpmp TEGRA186_RESET_PWM4>; 1030 reset-names = "pwm"; 1031 status = "disabled"; 1032 #pwm-cells = <2>; 1033 }; 1034 1035 pmc: pmc@c360000 { 1036 compatible = "nvidia,tegra186-pmc"; 1037 reg = <0 0x0c360000 0 0x10000>, 1038 <0 0x0c370000 0 0x10000>, 1039 <0 0x0c380000 0 0x10000>, 1040 <0 0x0c390000 0 0x10000>; 1041 reg-names = "pmc", "wake", "aotag", "scratch"; 1042 1043 #interrupt-cells = <2>; 1044 interrupt-controller; 1045 1046 sdmmc1_3v3: sdmmc1-3v3 { 1047 pins = "sdmmc1-hv"; 1048 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1049 }; 1050 1051 sdmmc1_1v8: sdmmc1-1v8 { 1052 pins = "sdmmc1-hv"; 1053 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1054 }; 1055 1056 sdmmc2_3v3: sdmmc2-3v3 { 1057 pins = "sdmmc2-hv"; 1058 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1059 }; 1060 1061 sdmmc2_1v8: sdmmc2-1v8 { 1062 pins = "sdmmc2-hv"; 1063 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1064 }; 1065 1066 sdmmc3_3v3: sdmmc3-3v3 { 1067 pins = "sdmmc3-hv"; 1068 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1069 }; 1070 1071 sdmmc3_1v8: sdmmc3-1v8 { 1072 pins = "sdmmc3-hv"; 1073 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1074 }; 1075 }; 1076 1077 ccplex@e000000 { 1078 compatible = "nvidia,tegra186-ccplex-cluster"; 1079 reg = <0x0 0x0e000000 0x0 0x3fffff>; 1080 1081 nvidia,bpmp = <&bpmp>; 1082 }; 1083 1084 pcie@10003000 { 1085 compatible = "nvidia,tegra186-pcie"; 1086 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1087 device_type = "pci"; 1088 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1089 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1090 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1091 reg-names = "pads", "afi", "cs"; 1092 1093 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1094 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1095 interrupt-names = "intr", "msi"; 1096 1097 #interrupt-cells = <1>; 1098 interrupt-map-mask = <0 0 0 0>; 1099 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1100 1101 bus-range = <0x00 0xff>; 1102 #address-cells = <3>; 1103 #size-cells = <2>; 1104 1105 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1106 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1107 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1108 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1109 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1110 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1111 1112 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1113 <&bpmp TEGRA186_CLK_AFI>, 1114 <&bpmp TEGRA186_CLK_PLLE>; 1115 clock-names = "pex", "afi", "pll_e"; 1116 1117 resets = <&bpmp TEGRA186_RESET_PCIE>, 1118 <&bpmp TEGRA186_RESET_AFI>, 1119 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1120 reset-names = "pex", "afi", "pcie_x"; 1121 1122 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1123 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1124 interconnect-names = "dma-mem", "write"; 1125 1126 iommus = <&smmu TEGRA186_SID_AFI>; 1127 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1128 iommu-map-mask = <0x0>; 1129 1130 status = "disabled"; 1131 1132 pci@1,0 { 1133 device_type = "pci"; 1134 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1135 reg = <0x000800 0 0 0 0>; 1136 status = "disabled"; 1137 1138 #address-cells = <3>; 1139 #size-cells = <2>; 1140 ranges; 1141 1142 nvidia,num-lanes = <2>; 1143 }; 1144 1145 pci@2,0 { 1146 device_type = "pci"; 1147 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1148 reg = <0x001000 0 0 0 0>; 1149 status = "disabled"; 1150 1151 #address-cells = <3>; 1152 #size-cells = <2>; 1153 ranges; 1154 1155 nvidia,num-lanes = <1>; 1156 }; 1157 1158 pci@3,0 { 1159 device_type = "pci"; 1160 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1161 reg = <0x001800 0 0 0 0>; 1162 status = "disabled"; 1163 1164 #address-cells = <3>; 1165 #size-cells = <2>; 1166 ranges; 1167 1168 nvidia,num-lanes = <1>; 1169 }; 1170 }; 1171 1172 smmu: iommu@12000000 { 1173 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1174 reg = <0 0x12000000 0 0x800000>; 1175 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1240 stream-match-mask = <0x7f80>; 1241 #global-interrupts = <1>; 1242 #iommu-cells = <1>; 1243 1244 nvidia,memory-controller = <&mc>; 1245 }; 1246 1247 host1x@13e00000 { 1248 compatible = "nvidia,tegra186-host1x"; 1249 reg = <0x0 0x13e00000 0x0 0x10000>, 1250 <0x0 0x13e10000 0x0 0x10000>; 1251 reg-names = "hypervisor", "vm"; 1252 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1254 interrupt-names = "syncpt", "host1x"; 1255 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1256 clock-names = "host1x"; 1257 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1258 reset-names = "host1x"; 1259 1260 #address-cells = <1>; 1261 #size-cells = <1>; 1262 1263 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1264 1265 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1266 interconnect-names = "dma-mem"; 1267 1268 iommus = <&smmu TEGRA186_SID_HOST1X>; 1269 1270 dpaux1: dpaux@15040000 { 1271 compatible = "nvidia,tegra186-dpaux"; 1272 reg = <0x15040000 0x10000>; 1273 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1275 <&bpmp TEGRA186_CLK_PLLDP>; 1276 clock-names = "dpaux", "parent"; 1277 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1278 reset-names = "dpaux"; 1279 status = "disabled"; 1280 1281 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1282 1283 state_dpaux1_aux: pinmux-aux { 1284 groups = "dpaux-io"; 1285 function = "aux"; 1286 }; 1287 1288 state_dpaux1_i2c: pinmux-i2c { 1289 groups = "dpaux-io"; 1290 function = "i2c"; 1291 }; 1292 1293 state_dpaux1_off: pinmux-off { 1294 groups = "dpaux-io"; 1295 function = "off"; 1296 }; 1297 1298 i2c-bus { 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 }; 1302 }; 1303 1304 display-hub@15200000 { 1305 compatible = "nvidia,tegra186-display"; 1306 reg = <0x15200000 0x00040000>; 1307 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1308 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1309 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1310 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1311 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1312 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1313 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1314 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1315 "wgrp3", "wgrp4", "wgrp5"; 1316 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1317 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1318 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1319 clock-names = "disp", "dsc", "hub"; 1320 status = "disabled"; 1321 1322 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1323 1324 #address-cells = <1>; 1325 #size-cells = <1>; 1326 1327 ranges = <0x15200000 0x15200000 0x40000>; 1328 1329 display@15200000 { 1330 compatible = "nvidia,tegra186-dc"; 1331 reg = <0x15200000 0x10000>; 1332 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1333 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1334 clock-names = "dc"; 1335 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1336 reset-names = "dc"; 1337 1338 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1339 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1340 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1341 interconnect-names = "dma-mem", "read-1"; 1342 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1343 1344 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1345 nvidia,head = <0>; 1346 }; 1347 1348 display@15210000 { 1349 compatible = "nvidia,tegra186-dc"; 1350 reg = <0x15210000 0x10000>; 1351 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1352 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1353 clock-names = "dc"; 1354 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1355 reset-names = "dc"; 1356 1357 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1358 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1359 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1360 interconnect-names = "dma-mem", "read-1"; 1361 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1362 1363 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1364 nvidia,head = <1>; 1365 }; 1366 1367 display@15220000 { 1368 compatible = "nvidia,tegra186-dc"; 1369 reg = <0x15220000 0x10000>; 1370 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1371 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1372 clock-names = "dc"; 1373 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1374 reset-names = "dc"; 1375 1376 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1377 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1378 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1379 interconnect-names = "dma-mem", "read-1"; 1380 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1381 1382 nvidia,outputs = <&sor0 &sor1>; 1383 nvidia,head = <2>; 1384 }; 1385 }; 1386 1387 dsia: dsi@15300000 { 1388 compatible = "nvidia,tegra186-dsi"; 1389 reg = <0x15300000 0x10000>; 1390 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1391 clocks = <&bpmp TEGRA186_CLK_DSI>, 1392 <&bpmp TEGRA186_CLK_DSIA_LP>, 1393 <&bpmp TEGRA186_CLK_PLLD>; 1394 clock-names = "dsi", "lp", "parent"; 1395 resets = <&bpmp TEGRA186_RESET_DSI>; 1396 reset-names = "dsi"; 1397 status = "disabled"; 1398 1399 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1400 }; 1401 1402 vic@15340000 { 1403 compatible = "nvidia,tegra186-vic"; 1404 reg = <0x15340000 0x40000>; 1405 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1406 clocks = <&bpmp TEGRA186_CLK_VIC>; 1407 clock-names = "vic"; 1408 resets = <&bpmp TEGRA186_RESET_VIC>; 1409 reset-names = "vic"; 1410 1411 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1412 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1413 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1414 interconnect-names = "dma-mem", "write"; 1415 iommus = <&smmu TEGRA186_SID_VIC>; 1416 }; 1417 1418 dsib: dsi@15400000 { 1419 compatible = "nvidia,tegra186-dsi"; 1420 reg = <0x15400000 0x10000>; 1421 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1422 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1423 <&bpmp TEGRA186_CLK_DSIB_LP>, 1424 <&bpmp TEGRA186_CLK_PLLD>; 1425 clock-names = "dsi", "lp", "parent"; 1426 resets = <&bpmp TEGRA186_RESET_DSIB>; 1427 reset-names = "dsi"; 1428 status = "disabled"; 1429 1430 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1431 }; 1432 1433 sor0: sor@15540000 { 1434 compatible = "nvidia,tegra186-sor"; 1435 reg = <0x15540000 0x10000>; 1436 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1437 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1438 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1439 <&bpmp TEGRA186_CLK_PLLD2>, 1440 <&bpmp TEGRA186_CLK_PLLDP>, 1441 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1442 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1443 clock-names = "sor", "out", "parent", "dp", "safe", 1444 "pad"; 1445 resets = <&bpmp TEGRA186_RESET_SOR0>; 1446 reset-names = "sor"; 1447 pinctrl-0 = <&state_dpaux_aux>; 1448 pinctrl-1 = <&state_dpaux_i2c>; 1449 pinctrl-2 = <&state_dpaux_off>; 1450 pinctrl-names = "aux", "i2c", "off"; 1451 status = "disabled"; 1452 1453 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1454 nvidia,interface = <0>; 1455 }; 1456 1457 sor1: sor@15580000 { 1458 compatible = "nvidia,tegra186-sor"; 1459 reg = <0x15580000 0x10000>; 1460 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1461 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1462 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1463 <&bpmp TEGRA186_CLK_PLLD3>, 1464 <&bpmp TEGRA186_CLK_PLLDP>, 1465 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1466 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1467 clock-names = "sor", "out", "parent", "dp", "safe", 1468 "pad"; 1469 resets = <&bpmp TEGRA186_RESET_SOR1>; 1470 reset-names = "sor"; 1471 pinctrl-0 = <&state_dpaux1_aux>; 1472 pinctrl-1 = <&state_dpaux1_i2c>; 1473 pinctrl-2 = <&state_dpaux1_off>; 1474 pinctrl-names = "aux", "i2c", "off"; 1475 status = "disabled"; 1476 1477 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1478 nvidia,interface = <1>; 1479 }; 1480 1481 dpaux: dpaux@155c0000 { 1482 compatible = "nvidia,tegra186-dpaux"; 1483 reg = <0x155c0000 0x10000>; 1484 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1485 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1486 <&bpmp TEGRA186_CLK_PLLDP>; 1487 clock-names = "dpaux", "parent"; 1488 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1489 reset-names = "dpaux"; 1490 status = "disabled"; 1491 1492 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1493 1494 state_dpaux_aux: pinmux-aux { 1495 groups = "dpaux-io"; 1496 function = "aux"; 1497 }; 1498 1499 state_dpaux_i2c: pinmux-i2c { 1500 groups = "dpaux-io"; 1501 function = "i2c"; 1502 }; 1503 1504 state_dpaux_off: pinmux-off { 1505 groups = "dpaux-io"; 1506 function = "off"; 1507 }; 1508 1509 i2c-bus { 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 }; 1513 }; 1514 1515 padctl@15880000 { 1516 compatible = "nvidia,tegra186-dsi-padctl"; 1517 reg = <0x15880000 0x10000>; 1518 resets = <&bpmp TEGRA186_RESET_DSI>; 1519 reset-names = "dsi"; 1520 status = "disabled"; 1521 }; 1522 1523 dsic: dsi@15900000 { 1524 compatible = "nvidia,tegra186-dsi"; 1525 reg = <0x15900000 0x10000>; 1526 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1527 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1528 <&bpmp TEGRA186_CLK_DSIC_LP>, 1529 <&bpmp TEGRA186_CLK_PLLD>; 1530 clock-names = "dsi", "lp", "parent"; 1531 resets = <&bpmp TEGRA186_RESET_DSIC>; 1532 reset-names = "dsi"; 1533 status = "disabled"; 1534 1535 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1536 }; 1537 1538 dsid: dsi@15940000 { 1539 compatible = "nvidia,tegra186-dsi"; 1540 reg = <0x15940000 0x10000>; 1541 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1542 clocks = <&bpmp TEGRA186_CLK_DSID>, 1543 <&bpmp TEGRA186_CLK_DSID_LP>, 1544 <&bpmp TEGRA186_CLK_PLLD>; 1545 clock-names = "dsi", "lp", "parent"; 1546 resets = <&bpmp TEGRA186_RESET_DSID>; 1547 reset-names = "dsi"; 1548 status = "disabled"; 1549 1550 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1551 }; 1552 }; 1553 1554 gpu@17000000 { 1555 compatible = "nvidia,gp10b"; 1556 reg = <0x0 0x17000000 0x0 0x1000000>, 1557 <0x0 0x18000000 0x0 0x1000000>; 1558 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1560 interrupt-names = "stall", "nonstall"; 1561 1562 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1563 <&bpmp TEGRA186_CLK_GPU>; 1564 clock-names = "gpu", "pwr"; 1565 resets = <&bpmp TEGRA186_RESET_GPU>; 1566 reset-names = "gpu"; 1567 status = "disabled"; 1568 1569 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1570 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1571 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1572 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1573 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1574 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1575 }; 1576 1577 sram@30000000 { 1578 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1579 reg = <0x0 0x30000000 0x0 0x50000>; 1580 #address-cells = <1>; 1581 #size-cells = <1>; 1582 ranges = <0x0 0x0 0x30000000 0x50000>; 1583 1584 cpu_bpmp_tx: sram@4e000 { 1585 reg = <0x4e000 0x1000>; 1586 label = "cpu-bpmp-tx"; 1587 pool; 1588 }; 1589 1590 cpu_bpmp_rx: sram@4f000 { 1591 reg = <0x4f000 0x1000>; 1592 label = "cpu-bpmp-rx"; 1593 pool; 1594 }; 1595 }; 1596 1597 sata@3507000 { 1598 compatible = "nvidia,tegra186-ahci"; 1599 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1600 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1601 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1602 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1603 1604 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1605 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1606 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1607 interconnect-names = "dma-mem", "write"; 1608 iommus = <&smmu TEGRA186_SID_SATA>; 1609 1610 clocks = <&bpmp TEGRA186_CLK_SATA>, 1611 <&bpmp TEGRA186_CLK_SATA_OOB>; 1612 clock-names = "sata", "sata-oob"; 1613 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1614 <&bpmp TEGRA186_CLK_SATA_OOB>; 1615 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1616 <&bpmp TEGRA186_CLK_PLLP>; 1617 assigned-clock-rates = <102000000>, 1618 <204000000>; 1619 resets = <&bpmp TEGRA186_RESET_SATA>, 1620 <&bpmp TEGRA186_RESET_SATACOLD>; 1621 reset-names = "sata", "sata-cold"; 1622 status = "disabled"; 1623 }; 1624 1625 bpmp: bpmp { 1626 compatible = "nvidia,tegra186-bpmp"; 1627 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1628 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1629 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1630 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1631 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1632 iommus = <&smmu TEGRA186_SID_BPMP>; 1633 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1634 TEGRA_HSP_DB_MASTER_BPMP>; 1635 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1636 #clock-cells = <1>; 1637 #reset-cells = <1>; 1638 #power-domain-cells = <1>; 1639 1640 bpmp_i2c: i2c { 1641 compatible = "nvidia,tegra186-bpmp-i2c"; 1642 nvidia,bpmp-bus-id = <5>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 status = "disabled"; 1646 }; 1647 1648 bpmp_thermal: thermal { 1649 compatible = "nvidia,tegra186-bpmp-thermal"; 1650 #thermal-sensor-cells = <1>; 1651 }; 1652 }; 1653 1654 cpus { 1655 #address-cells = <1>; 1656 #size-cells = <0>; 1657 1658 denver_0: cpu@0 { 1659 compatible = "nvidia,tegra186-denver"; 1660 device_type = "cpu"; 1661 i-cache-size = <0x20000>; 1662 i-cache-line-size = <64>; 1663 i-cache-sets = <512>; 1664 d-cache-size = <0x10000>; 1665 d-cache-line-size = <64>; 1666 d-cache-sets = <256>; 1667 next-level-cache = <&L2_DENVER>; 1668 reg = <0x000>; 1669 }; 1670 1671 denver_1: cpu@1 { 1672 compatible = "nvidia,tegra186-denver"; 1673 device_type = "cpu"; 1674 i-cache-size = <0x20000>; 1675 i-cache-line-size = <64>; 1676 i-cache-sets = <512>; 1677 d-cache-size = <0x10000>; 1678 d-cache-line-size = <64>; 1679 d-cache-sets = <256>; 1680 next-level-cache = <&L2_DENVER>; 1681 reg = <0x001>; 1682 }; 1683 1684 ca57_0: cpu@2 { 1685 compatible = "arm,cortex-a57"; 1686 device_type = "cpu"; 1687 i-cache-size = <0xC000>; 1688 i-cache-line-size = <64>; 1689 i-cache-sets = <256>; 1690 d-cache-size = <0x8000>; 1691 d-cache-line-size = <64>; 1692 d-cache-sets = <256>; 1693 next-level-cache = <&L2_A57>; 1694 reg = <0x100>; 1695 }; 1696 1697 ca57_1: cpu@3 { 1698 compatible = "arm,cortex-a57"; 1699 device_type = "cpu"; 1700 i-cache-size = <0xC000>; 1701 i-cache-line-size = <64>; 1702 i-cache-sets = <256>; 1703 d-cache-size = <0x8000>; 1704 d-cache-line-size = <64>; 1705 d-cache-sets = <256>; 1706 next-level-cache = <&L2_A57>; 1707 reg = <0x101>; 1708 }; 1709 1710 ca57_2: cpu@4 { 1711 compatible = "arm,cortex-a57"; 1712 device_type = "cpu"; 1713 i-cache-size = <0xC000>; 1714 i-cache-line-size = <64>; 1715 i-cache-sets = <256>; 1716 d-cache-size = <0x8000>; 1717 d-cache-line-size = <64>; 1718 d-cache-sets = <256>; 1719 next-level-cache = <&L2_A57>; 1720 reg = <0x102>; 1721 }; 1722 1723 ca57_3: cpu@5 { 1724 compatible = "arm,cortex-a57"; 1725 device_type = "cpu"; 1726 i-cache-size = <0xC000>; 1727 i-cache-line-size = <64>; 1728 i-cache-sets = <256>; 1729 d-cache-size = <0x8000>; 1730 d-cache-line-size = <64>; 1731 d-cache-sets = <256>; 1732 next-level-cache = <&L2_A57>; 1733 reg = <0x103>; 1734 }; 1735 1736 L2_DENVER: l2-cache0 { 1737 compatible = "cache"; 1738 cache-unified; 1739 cache-level = <2>; 1740 cache-size = <0x200000>; 1741 cache-line-size = <64>; 1742 cache-sets = <2048>; 1743 }; 1744 1745 L2_A57: l2-cache1 { 1746 compatible = "cache"; 1747 cache-unified; 1748 cache-level = <2>; 1749 cache-size = <0x200000>; 1750 cache-line-size = <64>; 1751 cache-sets = <2048>; 1752 }; 1753 }; 1754 1755 pmu_denver { 1756 compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3"; 1757 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1759 interrupt-affinity = <&denver_0 &denver_1>; 1760 }; 1761 1762 pmu_a57 { 1763 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; 1764 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1768 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 1769 }; 1770 1771 sound { 1772 status = "disabled"; 1773 1774 clocks = <&bpmp TEGRA186_CLK_PLLA>, 1775 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 1776 clock-names = "pll_a", "plla_out0"; 1777 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 1778 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 1779 <&bpmp TEGRA186_CLK_AUD_MCLK>; 1780 assigned-clock-parents = <0>, 1781 <&bpmp TEGRA186_CLK_PLLA>, 1782 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 1783 /* 1784 * PLLA supports dynamic ramp. Below initial rate is chosen 1785 * for this to work and oscillate between base rates required 1786 * for 8x and 11.025x sample rate streams. 1787 */ 1788 assigned-clock-rates = <258000000>; 1789 1790 iommus = <&smmu TEGRA186_SID_APE>; 1791 }; 1792 1793 thermal-zones { 1794 a57 { 1795 polling-delay = <0>; 1796 polling-delay-passive = <1000>; 1797 1798 thermal-sensors = 1799 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1800 1801 trips { 1802 critical { 1803 temperature = <101000>; 1804 hysteresis = <0>; 1805 type = "critical"; 1806 }; 1807 }; 1808 1809 cooling-maps { 1810 }; 1811 }; 1812 1813 denver { 1814 polling-delay = <0>; 1815 polling-delay-passive = <1000>; 1816 1817 thermal-sensors = 1818 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1819 1820 trips { 1821 critical { 1822 temperature = <101000>; 1823 hysteresis = <0>; 1824 type = "critical"; 1825 }; 1826 }; 1827 1828 cooling-maps { 1829 }; 1830 }; 1831 1832 gpu { 1833 polling-delay = <0>; 1834 polling-delay-passive = <1000>; 1835 1836 thermal-sensors = 1837 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1838 1839 trips { 1840 critical { 1841 temperature = <101000>; 1842 hysteresis = <0>; 1843 type = "critical"; 1844 }; 1845 }; 1846 1847 cooling-maps { 1848 }; 1849 }; 1850 1851 pll { 1852 polling-delay = <0>; 1853 polling-delay-passive = <1000>; 1854 1855 thermal-sensors = 1856 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1857 1858 trips { 1859 critical { 1860 temperature = <101000>; 1861 hysteresis = <0>; 1862 type = "critical"; 1863 }; 1864 }; 1865 1866 cooling-maps { 1867 }; 1868 }; 1869 1870 always_on { 1871 polling-delay = <0>; 1872 polling-delay-passive = <1000>; 1873 1874 thermal-sensors = 1875 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1876 1877 trips { 1878 critical { 1879 temperature = <101000>; 1880 hysteresis = <0>; 1881 type = "critical"; 1882 }; 1883 }; 1884 1885 cooling-maps { 1886 }; 1887 }; 1888 }; 1889 1890 timer { 1891 compatible = "arm,armv8-timer"; 1892 interrupts = <GIC_PPI 13 1893 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1894 <GIC_PPI 14 1895 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1896 <GIC_PPI 11 1897 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1898 <GIC_PPI 10 1899 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1900 interrupt-parent = <&gic>; 1901 always-on; 1902 }; 1903}; 1904