1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra186-clock.h>
3#include <dt-bindings/gpio/tegra186-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/memory/tegra186-mc.h>
7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8#include <dt-bindings/power/tegra186-powergate.h>
9#include <dt-bindings/reset/tegra186-reset.h>
10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
11
12/ {
13	compatible = "nvidia,tegra186";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	misc@100000 {
19		compatible = "nvidia,tegra186-misc";
20		reg = <0x0 0x00100000 0x0 0xf000>,
21		      <0x0 0x0010f000 0x0 0x1000>;
22	};
23
24	gpio: gpio@2200000 {
25		compatible = "nvidia,tegra186-gpio";
26		reg-names = "security", "gpio";
27		reg = <0x0 0x2200000 0x0 0x10000>,
28		      <0x0 0x2210000 0x0 0x10000>;
29		interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
30			     <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
31			     <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
33			     <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
34			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35		#interrupt-cells = <2>;
36		interrupt-controller;
37		#gpio-cells = <2>;
38		gpio-controller;
39	};
40
41	ethernet@2490000 {
42		compatible = "nvidia,tegra186-eqos",
43			     "snps,dwc-qos-ethernet-4.10";
44		reg = <0x0 0x02490000 0x0 0x10000>;
45		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56			 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57			 <&bpmp TEGRA186_CLK_EQOS_RX>,
58			 <&bpmp TEGRA186_CLK_EQOS_TX>,
59			 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61		resets = <&bpmp TEGRA186_RESET_EQOS>;
62		reset-names = "eqos";
63		interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
64				<&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
65		interconnect-names = "dma-mem", "write";
66		iommus = <&smmu TEGRA186_SID_EQOS>;
67		status = "disabled";
68
69		snps,write-requests = <1>;
70		snps,read-requests = <3>;
71		snps,burst-map = <0x7>;
72		snps,txpbl = <32>;
73		snps,rxpbl = <8>;
74	};
75
76	aconnect@2900000 {
77		compatible = "nvidia,tegra186-aconnect",
78			     "nvidia,tegra210-aconnect";
79		clocks = <&bpmp TEGRA186_CLK_APE>,
80			 <&bpmp TEGRA186_CLK_APB2APE>;
81		clock-names = "ape", "apb2ape";
82		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
83		#address-cells = <1>;
84		#size-cells = <1>;
85		ranges = <0x02900000 0x0 0x02900000 0x200000>;
86		status = "disabled";
87
88		adma: dma-controller@2930000 {
89			compatible = "nvidia,tegra186-adma";
90			reg = <0x02930000 0x20000>;
91			interrupt-parent = <&agic>;
92			interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
93				      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
94				      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
95				      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
96				      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
97				      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
98				      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
99				      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
100				      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
101				      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
102				      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
103				      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
104				      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
105				      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
106				      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
107				      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
108				      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
109				      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
110				      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
111				      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
112				      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
113				      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
114				      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
115				      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
116				      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
117				      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
118				      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
119				      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
120				      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
121				      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
122				      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
123				      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
124			#dma-cells = <1>;
125			clocks = <&bpmp TEGRA186_CLK_AHUB>;
126			clock-names = "d_audio";
127			status = "disabled";
128		};
129
130		agic: interrupt-controller@2a40000 {
131			compatible = "nvidia,tegra186-agic",
132				     "nvidia,tegra210-agic";
133			#interrupt-cells = <3>;
134			interrupt-controller;
135			reg = <0x02a41000 0x1000>,
136			      <0x02a42000 0x2000>;
137			interrupts = <GIC_SPI 145
138				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
139			clocks = <&bpmp TEGRA186_CLK_APE>;
140			clock-names = "clk";
141			status = "disabled";
142		};
143
144		tegra_ahub: ahub@2900800 {
145			compatible = "nvidia,tegra186-ahub";
146			reg = <0x02900800 0x800>;
147			clocks = <&bpmp TEGRA186_CLK_AHUB>;
148			clock-names = "ahub";
149			assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
150			assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
151			#address-cells = <1>;
152			#size-cells = <1>;
153			ranges = <0x02900800 0x02900800 0x11800>;
154			status = "disabled";
155
156			tegra_admaif: admaif@290f000 {
157				compatible = "nvidia,tegra186-admaif";
158				reg = <0x0290f000 0x1000>;
159				dmas = <&adma 1>, <&adma 1>,
160				       <&adma 2>, <&adma 2>,
161				       <&adma 3>, <&adma 3>,
162				       <&adma 4>, <&adma 4>,
163				       <&adma 5>, <&adma 5>,
164				       <&adma 6>, <&adma 6>,
165				       <&adma 7>, <&adma 7>,
166				       <&adma 8>, <&adma 8>,
167				       <&adma 9>, <&adma 9>,
168				       <&adma 10>, <&adma 10>,
169				       <&adma 11>, <&adma 11>,
170				       <&adma 12>, <&adma 12>,
171				       <&adma 13>, <&adma 13>,
172				       <&adma 14>, <&adma 14>,
173				       <&adma 15>, <&adma 15>,
174				       <&adma 16>, <&adma 16>,
175				       <&adma 17>, <&adma 17>,
176				       <&adma 18>, <&adma 18>,
177				       <&adma 19>, <&adma 19>,
178				       <&adma 20>, <&adma 20>;
179				dma-names = "rx1", "tx1",
180					    "rx2", "tx2",
181					    "rx3", "tx3",
182					    "rx4", "tx4",
183					    "rx5", "tx5",
184					    "rx6", "tx6",
185					    "rx7", "tx7",
186					    "rx8", "tx8",
187					    "rx9", "tx9",
188					    "rx10", "tx10",
189					    "rx11", "tx11",
190					    "rx12", "tx12",
191					    "rx13", "tx13",
192					    "rx14", "tx14",
193					    "rx15", "tx15",
194					    "rx16", "tx16",
195					    "rx17", "tx17",
196					    "rx18", "tx18",
197					    "rx19", "tx19",
198					    "rx20", "tx20";
199				status = "disabled";
200			};
201
202			tegra_i2s1: i2s@2901000 {
203				compatible = "nvidia,tegra186-i2s",
204					     "nvidia,tegra210-i2s";
205				reg = <0x2901000 0x100>;
206				clocks = <&bpmp TEGRA186_CLK_I2S1>,
207					 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
208				clock-names = "i2s", "sync_input";
209				assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
210				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
211				assigned-clock-rates = <1536000>;
212				sound-name-prefix = "I2S1";
213				status = "disabled";
214			};
215
216			tegra_i2s2: i2s@2901100 {
217				compatible = "nvidia,tegra186-i2s",
218					     "nvidia,tegra210-i2s";
219				reg = <0x2901100 0x100>;
220				clocks = <&bpmp TEGRA186_CLK_I2S2>,
221					 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
222				clock-names = "i2s", "sync_input";
223				assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
224				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
225				assigned-clock-rates = <1536000>;
226				sound-name-prefix = "I2S2";
227				status = "disabled";
228			};
229
230			tegra_i2s3: i2s@2901200 {
231				compatible = "nvidia,tegra186-i2s",
232					     "nvidia,tegra210-i2s";
233				reg = <0x2901200 0x100>;
234				clocks = <&bpmp TEGRA186_CLK_I2S3>,
235					 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
236				clock-names = "i2s", "sync_input";
237				assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
238				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
239				assigned-clock-rates = <1536000>;
240				sound-name-prefix = "I2S3";
241				status = "disabled";
242			};
243
244			tegra_i2s4: i2s@2901300 {
245				compatible = "nvidia,tegra186-i2s",
246					     "nvidia,tegra210-i2s";
247				reg = <0x2901300 0x100>;
248				clocks = <&bpmp TEGRA186_CLK_I2S4>,
249					 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
250				clock-names = "i2s", "sync_input";
251				assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
252				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
253				assigned-clock-rates = <1536000>;
254				sound-name-prefix = "I2S4";
255				status = "disabled";
256			};
257
258			tegra_i2s5: i2s@2901400 {
259				compatible = "nvidia,tegra186-i2s",
260					     "nvidia,tegra210-i2s";
261				reg = <0x2901400 0x100>;
262				clocks = <&bpmp TEGRA186_CLK_I2S5>,
263					 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
264				clock-names = "i2s", "sync_input";
265				assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
266				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
267				assigned-clock-rates = <1536000>;
268				sound-name-prefix = "I2S5";
269				status = "disabled";
270			};
271
272			tegra_i2s6: i2s@2901500 {
273				compatible = "nvidia,tegra186-i2s",
274					     "nvidia,tegra210-i2s";
275				reg = <0x2901500 0x100>;
276				clocks = <&bpmp TEGRA186_CLK_I2S6>,
277					 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
278				clock-names = "i2s", "sync_input";
279				assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
280				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
281				assigned-clock-rates = <1536000>;
282				sound-name-prefix = "I2S6";
283				status = "disabled";
284			};
285
286			tegra_dmic1: dmic@2904000 {
287				compatible = "nvidia,tegra210-dmic";
288				reg = <0x2904000 0x100>;
289				clocks = <&bpmp TEGRA186_CLK_DMIC1>;
290				clock-names = "dmic";
291				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
292				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
293				assigned-clock-rates = <3072000>;
294				sound-name-prefix = "DMIC1";
295				status = "disabled";
296			};
297
298			tegra_dmic2: dmic@2904100 {
299				compatible = "nvidia,tegra210-dmic";
300				reg = <0x2904100 0x100>;
301				clocks = <&bpmp TEGRA186_CLK_DMIC2>;
302				clock-names = "dmic";
303				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
304				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
305				assigned-clock-rates = <3072000>;
306				sound-name-prefix = "DMIC2";
307				status = "disabled";
308			};
309
310			tegra_dmic3: dmic@2904200 {
311				compatible = "nvidia,tegra210-dmic";
312				reg = <0x2904200 0x100>;
313				clocks = <&bpmp TEGRA186_CLK_DMIC3>;
314				clock-names = "dmic";
315				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
316				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
317				assigned-clock-rates = <3072000>;
318				sound-name-prefix = "DMIC3";
319				status = "disabled";
320			};
321
322			tegra_dmic4: dmic@2904300 {
323				compatible = "nvidia,tegra210-dmic";
324				reg = <0x2904300 0x100>;
325				clocks = <&bpmp TEGRA186_CLK_DMIC4>;
326				clock-names = "dmic";
327				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
328				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
329				assigned-clock-rates = <3072000>;
330				sound-name-prefix = "DMIC4";
331				status = "disabled";
332			};
333
334			tegra_dspk1: dspk@2905000 {
335				compatible = "nvidia,tegra186-dspk";
336				reg = <0x2905000 0x100>;
337				clocks = <&bpmp TEGRA186_CLK_DSPK1>;
338				clock-names = "dspk";
339				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
340				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
341				assigned-clock-rates = <12288000>;
342				sound-name-prefix = "DSPK1";
343				status = "disabled";
344			};
345
346			tegra_dspk2: dspk@2905100 {
347				compatible = "nvidia,tegra186-dspk";
348				reg = <0x2905100 0x100>;
349				clocks = <&bpmp TEGRA186_CLK_DSPK2>;
350				clock-names = "dspk";
351				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
352				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
353				assigned-clock-rates = <12288000>;
354				sound-name-prefix = "DSPK2";
355				status = "disabled";
356			};
357
358			tegra_sfc1: sfc@2902000 {
359				compatible = "nvidia,tegra186-sfc",
360					     "nvidia,tegra210-sfc";
361				reg = <0x2902000 0x200>;
362				sound-name-prefix = "SFC1";
363				status = "disabled";
364			};
365
366			tegra_sfc2: sfc@2902200 {
367				compatible = "nvidia,tegra186-sfc",
368					     "nvidia,tegra210-sfc";
369				reg = <0x2902200 0x200>;
370				sound-name-prefix = "SFC2";
371				status = "disabled";
372			};
373
374			tegra_sfc3: sfc@2902400 {
375				compatible = "nvidia,tegra186-sfc",
376					     "nvidia,tegra210-sfc";
377				reg = <0x2902400 0x200>;
378				sound-name-prefix = "SFC3";
379				status = "disabled";
380			};
381
382			tegra_sfc4: sfc@2902600 {
383				compatible = "nvidia,tegra186-sfc",
384					     "nvidia,tegra210-sfc";
385				reg = <0x2902600 0x200>;
386				sound-name-prefix = "SFC4";
387				status = "disabled";
388			};
389
390			tegra_mvc1: mvc@290a000 {
391				compatible = "nvidia,tegra186-mvc",
392					     "nvidia,tegra210-mvc";
393				reg = <0x290a000 0x200>;
394				sound-name-prefix = "MVC1";
395				status = "disabled";
396			};
397
398			tegra_mvc2: mvc@290a200 {
399				compatible = "nvidia,tegra186-mvc",
400					     "nvidia,tegra210-mvc";
401				reg = <0x290a200 0x200>;
402				sound-name-prefix = "MVC2";
403				status = "disabled";
404			};
405
406			tegra_amx1: amx@2903000 {
407				compatible = "nvidia,tegra186-amx",
408					     "nvidia,tegra210-amx";
409				reg = <0x2903000 0x100>;
410				sound-name-prefix = "AMX1";
411				status = "disabled";
412			};
413
414			tegra_amx2: amx@2903100 {
415				compatible = "nvidia,tegra186-amx",
416					     "nvidia,tegra210-amx";
417				reg = <0x2903100 0x100>;
418				sound-name-prefix = "AMX2";
419				status = "disabled";
420			};
421
422			tegra_amx3: amx@2903200 {
423				compatible = "nvidia,tegra186-amx",
424					     "nvidia,tegra210-amx";
425				reg = <0x2903200 0x100>;
426				sound-name-prefix = "AMX3";
427				status = "disabled";
428			};
429
430			tegra_amx4: amx@2903300 {
431				compatible = "nvidia,tegra186-amx",
432					     "nvidia,tegra210-amx";
433				reg = <0x2903300 0x100>;
434				sound-name-prefix = "AMX4";
435				status = "disabled";
436			};
437
438			tegra_adx1: adx@2903800 {
439				compatible = "nvidia,tegra186-adx",
440					     "nvidia,tegra210-adx";
441				reg = <0x2903800 0x100>;
442				sound-name-prefix = "ADX1";
443				status = "disabled";
444			};
445
446			tegra_adx2: adx@2903900 {
447				compatible = "nvidia,tegra186-adx",
448					     "nvidia,tegra210-adx";
449				reg = <0x2903900 0x100>;
450				sound-name-prefix = "ADX2";
451				status = "disabled";
452			};
453
454			tegra_adx3: adx@2903a00 {
455				compatible = "nvidia,tegra186-adx",
456					     "nvidia,tegra210-adx";
457				reg = <0x2903a00 0x100>;
458				sound-name-prefix = "ADX3";
459				status = "disabled";
460			};
461
462			tegra_adx4: adx@2903b00 {
463				compatible = "nvidia,tegra186-adx",
464					     "nvidia,tegra210-adx";
465				reg = <0x2903b00 0x100>;
466				sound-name-prefix = "ADX4";
467				status = "disabled";
468			};
469
470			tegra_amixer: amixer@290bb00 {
471				compatible = "nvidia,tegra186-amixer",
472					     "nvidia,tegra210-amixer";
473				reg = <0x290bb00 0x800>;
474				sound-name-prefix = "MIXER1";
475				status = "disabled";
476			};
477		};
478	};
479
480	mc: memory-controller@2c00000 {
481		compatible = "nvidia,tegra186-mc";
482		reg = <0x0 0x02c00000 0x0 0xb0000>;
483		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
484		status = "disabled";
485
486		#interconnect-cells = <1>;
487		#address-cells = <2>;
488		#size-cells = <2>;
489
490		ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
491
492		/*
493		 * Memory clients have access to all 40 bits that the memory
494		 * controller can address.
495		 */
496		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
497
498		emc: external-memory-controller@2c60000 {
499			compatible = "nvidia,tegra186-emc";
500			reg = <0x0 0x02c60000 0x0 0x50000>;
501			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
502			clocks = <&bpmp TEGRA186_CLK_EMC>;
503			clock-names = "emc";
504
505			#interconnect-cells = <0>;
506
507			nvidia,bpmp = <&bpmp>;
508		};
509	};
510
511	uarta: serial@3100000 {
512		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
513		reg = <0x0 0x03100000 0x0 0x40>;
514		reg-shift = <2>;
515		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
516		clocks = <&bpmp TEGRA186_CLK_UARTA>;
517		clock-names = "serial";
518		resets = <&bpmp TEGRA186_RESET_UARTA>;
519		reset-names = "serial";
520		status = "disabled";
521	};
522
523	uartb: serial@3110000 {
524		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
525		reg = <0x0 0x03110000 0x0 0x40>;
526		reg-shift = <2>;
527		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
528		clocks = <&bpmp TEGRA186_CLK_UARTB>;
529		clock-names = "serial";
530		resets = <&bpmp TEGRA186_RESET_UARTB>;
531		reset-names = "serial";
532		status = "disabled";
533	};
534
535	uartd: serial@3130000 {
536		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
537		reg = <0x0 0x03130000 0x0 0x40>;
538		reg-shift = <2>;
539		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
540		clocks = <&bpmp TEGRA186_CLK_UARTD>;
541		clock-names = "serial";
542		resets = <&bpmp TEGRA186_RESET_UARTD>;
543		reset-names = "serial";
544		status = "disabled";
545	};
546
547	uarte: serial@3140000 {
548		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
549		reg = <0x0 0x03140000 0x0 0x40>;
550		reg-shift = <2>;
551		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
552		clocks = <&bpmp TEGRA186_CLK_UARTE>;
553		clock-names = "serial";
554		resets = <&bpmp TEGRA186_RESET_UARTE>;
555		reset-names = "serial";
556		status = "disabled";
557	};
558
559	uartf: serial@3150000 {
560		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
561		reg = <0x0 0x03150000 0x0 0x40>;
562		reg-shift = <2>;
563		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
564		clocks = <&bpmp TEGRA186_CLK_UARTF>;
565		clock-names = "serial";
566		resets = <&bpmp TEGRA186_RESET_UARTF>;
567		reset-names = "serial";
568		status = "disabled";
569	};
570
571	gen1_i2c: i2c@3160000 {
572		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
573		reg = <0x0 0x03160000 0x0 0x10000>;
574		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
575		#address-cells = <1>;
576		#size-cells = <0>;
577		clocks = <&bpmp TEGRA186_CLK_I2C1>;
578		clock-names = "div-clk";
579		resets = <&bpmp TEGRA186_RESET_I2C1>;
580		reset-names = "i2c";
581		status = "disabled";
582	};
583
584	cam_i2c: i2c@3180000 {
585		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
586		reg = <0x0 0x03180000 0x0 0x10000>;
587		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
588		#address-cells = <1>;
589		#size-cells = <0>;
590		clocks = <&bpmp TEGRA186_CLK_I2C3>;
591		clock-names = "div-clk";
592		resets = <&bpmp TEGRA186_RESET_I2C3>;
593		reset-names = "i2c";
594		status = "disabled";
595	};
596
597	/* shares pads with dpaux1 */
598	dp_aux_ch1_i2c: i2c@3190000 {
599		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
600		reg = <0x0 0x03190000 0x0 0x10000>;
601		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
602		#address-cells = <1>;
603		#size-cells = <0>;
604		clocks = <&bpmp TEGRA186_CLK_I2C4>;
605		clock-names = "div-clk";
606		resets = <&bpmp TEGRA186_RESET_I2C4>;
607		reset-names = "i2c";
608		pinctrl-names = "default", "idle";
609		pinctrl-0 = <&state_dpaux1_i2c>;
610		pinctrl-1 = <&state_dpaux1_off>;
611		status = "disabled";
612	};
613
614	/* controlled by BPMP, should not be enabled */
615	pwr_i2c: i2c@31a0000 {
616		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
617		reg = <0x0 0x031a0000 0x0 0x10000>;
618		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
619		#address-cells = <1>;
620		#size-cells = <0>;
621		clocks = <&bpmp TEGRA186_CLK_I2C5>;
622		clock-names = "div-clk";
623		resets = <&bpmp TEGRA186_RESET_I2C5>;
624		reset-names = "i2c";
625		status = "disabled";
626	};
627
628	/* shares pads with dpaux0 */
629	dp_aux_ch0_i2c: i2c@31b0000 {
630		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
631		reg = <0x0 0x031b0000 0x0 0x10000>;
632		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
633		#address-cells = <1>;
634		#size-cells = <0>;
635		clocks = <&bpmp TEGRA186_CLK_I2C6>;
636		clock-names = "div-clk";
637		resets = <&bpmp TEGRA186_RESET_I2C6>;
638		reset-names = "i2c";
639		pinctrl-names = "default", "idle";
640		pinctrl-0 = <&state_dpaux_i2c>;
641		pinctrl-1 = <&state_dpaux_off>;
642		status = "disabled";
643	};
644
645	gen7_i2c: i2c@31c0000 {
646		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
647		reg = <0x0 0x031c0000 0x0 0x10000>;
648		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
649		#address-cells = <1>;
650		#size-cells = <0>;
651		clocks = <&bpmp TEGRA186_CLK_I2C7>;
652		clock-names = "div-clk";
653		resets = <&bpmp TEGRA186_RESET_I2C7>;
654		reset-names = "i2c";
655		status = "disabled";
656	};
657
658	gen9_i2c: i2c@31e0000 {
659		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
660		reg = <0x0 0x031e0000 0x0 0x10000>;
661		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
662		#address-cells = <1>;
663		#size-cells = <0>;
664		clocks = <&bpmp TEGRA186_CLK_I2C9>;
665		clock-names = "div-clk";
666		resets = <&bpmp TEGRA186_RESET_I2C9>;
667		reset-names = "i2c";
668		status = "disabled";
669	};
670
671	pwm1: pwm@3280000 {
672		compatible = "nvidia,tegra186-pwm";
673		reg = <0x0 0x3280000 0x0 0x10000>;
674		clocks = <&bpmp TEGRA186_CLK_PWM1>;
675		clock-names = "pwm";
676		resets = <&bpmp TEGRA186_RESET_PWM1>;
677		reset-names = "pwm";
678		status = "disabled";
679		#pwm-cells = <2>;
680	};
681
682	pwm2: pwm@3290000 {
683		compatible = "nvidia,tegra186-pwm";
684		reg = <0x0 0x3290000 0x0 0x10000>;
685		clocks = <&bpmp TEGRA186_CLK_PWM2>;
686		clock-names = "pwm";
687		resets = <&bpmp TEGRA186_RESET_PWM2>;
688		reset-names = "pwm";
689		status = "disabled";
690		#pwm-cells = <2>;
691	};
692
693	pwm3: pwm@32a0000 {
694		compatible = "nvidia,tegra186-pwm";
695		reg = <0x0 0x32a0000 0x0 0x10000>;
696		clocks = <&bpmp TEGRA186_CLK_PWM3>;
697		clock-names = "pwm";
698		resets = <&bpmp TEGRA186_RESET_PWM3>;
699		reset-names = "pwm";
700		status = "disabled";
701		#pwm-cells = <2>;
702	};
703
704	pwm5: pwm@32c0000 {
705		compatible = "nvidia,tegra186-pwm";
706		reg = <0x0 0x32c0000 0x0 0x10000>;
707		clocks = <&bpmp TEGRA186_CLK_PWM5>;
708		clock-names = "pwm";
709		resets = <&bpmp TEGRA186_RESET_PWM5>;
710		reset-names = "pwm";
711		status = "disabled";
712		#pwm-cells = <2>;
713	};
714
715	pwm6: pwm@32d0000 {
716		compatible = "nvidia,tegra186-pwm";
717		reg = <0x0 0x32d0000 0x0 0x10000>;
718		clocks = <&bpmp TEGRA186_CLK_PWM6>;
719		clock-names = "pwm";
720		resets = <&bpmp TEGRA186_RESET_PWM6>;
721		reset-names = "pwm";
722		status = "disabled";
723		#pwm-cells = <2>;
724	};
725
726	pwm7: pwm@32e0000 {
727		compatible = "nvidia,tegra186-pwm";
728		reg = <0x0 0x32e0000 0x0 0x10000>;
729		clocks = <&bpmp TEGRA186_CLK_PWM7>;
730		clock-names = "pwm";
731		resets = <&bpmp TEGRA186_RESET_PWM7>;
732		reset-names = "pwm";
733		status = "disabled";
734		#pwm-cells = <2>;
735	};
736
737	pwm8: pwm@32f0000 {
738		compatible = "nvidia,tegra186-pwm";
739		reg = <0x0 0x32f0000 0x0 0x10000>;
740		clocks = <&bpmp TEGRA186_CLK_PWM8>;
741		clock-names = "pwm";
742		resets = <&bpmp TEGRA186_RESET_PWM8>;
743		reset-names = "pwm";
744		status = "disabled";
745		#pwm-cells = <2>;
746	};
747
748	sdmmc1: mmc@3400000 {
749		compatible = "nvidia,tegra186-sdhci";
750		reg = <0x0 0x03400000 0x0 0x10000>;
751		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
752		clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
753			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
754		clock-names = "sdhci", "tmclk";
755		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
756		reset-names = "sdhci";
757		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
758				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
759		interconnect-names = "dma-mem", "write";
760		iommus = <&smmu TEGRA186_SID_SDMMC1>;
761		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
762		pinctrl-0 = <&sdmmc1_3v3>;
763		pinctrl-1 = <&sdmmc1_1v8>;
764		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
765		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
766		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
767		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
768		nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
769		nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
770		nvidia,default-tap = <0x5>;
771		nvidia,default-trim = <0xb>;
772		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
773				  <&bpmp TEGRA186_CLK_PLLP_OUT0>;
774		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
775		status = "disabled";
776	};
777
778	sdmmc2: mmc@3420000 {
779		compatible = "nvidia,tegra186-sdhci";
780		reg = <0x0 0x03420000 0x0 0x10000>;
781		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
782		clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
783			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
784		clock-names = "sdhci", "tmclk";
785		resets = <&bpmp TEGRA186_RESET_SDMMC2>;
786		reset-names = "sdhci";
787		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
788				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
789		interconnect-names = "dma-mem", "write";
790		iommus = <&smmu TEGRA186_SID_SDMMC2>;
791		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
792		pinctrl-0 = <&sdmmc2_3v3>;
793		pinctrl-1 = <&sdmmc2_1v8>;
794		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
795		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
796		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
797		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
798		nvidia,default-tap = <0x5>;
799		nvidia,default-trim = <0xb>;
800		status = "disabled";
801	};
802
803	sdmmc3: mmc@3440000 {
804		compatible = "nvidia,tegra186-sdhci";
805		reg = <0x0 0x03440000 0x0 0x10000>;
806		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
807		clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
808			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
809		clock-names = "sdhci", "tmclk";
810		resets = <&bpmp TEGRA186_RESET_SDMMC3>;
811		reset-names = "sdhci";
812		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
813				<&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
814		interconnect-names = "dma-mem", "write";
815		iommus = <&smmu TEGRA186_SID_SDMMC3>;
816		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
817		pinctrl-0 = <&sdmmc3_3v3>;
818		pinctrl-1 = <&sdmmc3_1v8>;
819		nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
820		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
821		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
822		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
823		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
824		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
825		nvidia,default-tap = <0x5>;
826		nvidia,default-trim = <0xb>;
827		status = "disabled";
828	};
829
830	sdmmc4: mmc@3460000 {
831		compatible = "nvidia,tegra186-sdhci";
832		reg = <0x0 0x03460000 0x0 0x10000>;
833		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
834		clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
835			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
836		clock-names = "sdhci", "tmclk";
837		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
838				  <&bpmp TEGRA186_CLK_PLLC4_VCO>;
839		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
840		resets = <&bpmp TEGRA186_RESET_SDMMC4>;
841		reset-names = "sdhci";
842		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
843				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
844		interconnect-names = "dma-mem", "write";
845		iommus = <&smmu TEGRA186_SID_SDMMC4>;
846		nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
847		nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
848		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
849		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
850		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
851		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
852		nvidia,default-tap = <0x9>;
853		nvidia,default-trim = <0x5>;
854		nvidia,dqs-trim = <63>;
855		mmc-hs400-1_8v;
856		supports-cqe;
857		status = "disabled";
858	};
859
860	hda@3510000 {
861		compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
862		reg = <0x0 0x03510000 0x0 0x10000>;
863		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
864		clocks = <&bpmp TEGRA186_CLK_HDA>,
865			 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
866			 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
867		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
868		resets = <&bpmp TEGRA186_RESET_HDA>,
869			 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
870			 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
871		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
872		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
873		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
874				<&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
875		interconnect-names = "dma-mem", "write";
876		iommus = <&smmu TEGRA186_SID_HDA>;
877		status = "disabled";
878	};
879
880	padctl: padctl@3520000 {
881		compatible = "nvidia,tegra186-xusb-padctl";
882		reg = <0x0 0x03520000 0x0 0x1000>,
883		      <0x0 0x03540000 0x0 0x1000>;
884		reg-names = "padctl", "ao";
885		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
886
887		resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
888		reset-names = "padctl";
889
890		status = "disabled";
891
892		pads {
893			usb2 {
894				clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
895				clock-names = "trk";
896				status = "disabled";
897
898				lanes {
899					usb2-0 {
900						status = "disabled";
901						#phy-cells = <0>;
902					};
903
904					usb2-1 {
905						status = "disabled";
906						#phy-cells = <0>;
907					};
908
909					usb2-2 {
910						status = "disabled";
911						#phy-cells = <0>;
912					};
913				};
914			};
915
916			hsic {
917				clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
918				clock-names = "trk";
919				status = "disabled";
920
921				lanes {
922					hsic-0 {
923						status = "disabled";
924						#phy-cells = <0>;
925					};
926				};
927			};
928
929			usb3 {
930				status = "disabled";
931
932				lanes {
933					usb3-0 {
934						status = "disabled";
935						#phy-cells = <0>;
936					};
937
938					usb3-1 {
939						status = "disabled";
940						#phy-cells = <0>;
941					};
942
943					usb3-2 {
944						status = "disabled";
945						#phy-cells = <0>;
946					};
947				};
948			};
949		};
950
951		ports {
952			usb2-0 {
953				status = "disabled";
954			};
955
956			usb2-1 {
957				status = "disabled";
958			};
959
960			usb2-2 {
961				status = "disabled";
962			};
963
964			hsic-0 {
965				status = "disabled";
966			};
967
968			usb3-0 {
969				status = "disabled";
970			};
971
972			usb3-1 {
973				status = "disabled";
974			};
975
976			usb3-2 {
977				status = "disabled";
978			};
979		};
980	};
981
982	usb@3530000 {
983		compatible = "nvidia,tegra186-xusb";
984		reg = <0x0 0x03530000 0x0 0x8000>,
985		      <0x0 0x03538000 0x0 0x1000>;
986		reg-names = "hcd", "fpci";
987		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
988			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
989		clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
990			 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
991			 <&bpmp TEGRA186_CLK_XUSB_SS>,
992			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
993			 <&bpmp TEGRA186_CLK_CLK_M>,
994			 <&bpmp TEGRA186_CLK_XUSB_FS>,
995			 <&bpmp TEGRA186_CLK_PLLU>,
996			 <&bpmp TEGRA186_CLK_CLK_M>,
997			 <&bpmp TEGRA186_CLK_PLLE>;
998		clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
999			      "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
1000			      "pll_u_480m", "clk_m", "pll_e";
1001		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1002				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1003		power-domain-names = "xusb_host", "xusb_ss";
1004		interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1005				<&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1006		interconnect-names = "dma-mem", "write";
1007		iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
1008		#address-cells = <1>;
1009		#size-cells = <0>;
1010		status = "disabled";
1011
1012		nvidia,xusb-padctl = <&padctl>;
1013	};
1014
1015	usb@3550000 {
1016		compatible = "nvidia,tegra186-xudc";
1017		reg = <0x0 0x03550000 0x0 0x8000>,
1018		      <0x0 0x03558000 0x0 0x1000>;
1019		reg-names = "base", "fpci";
1020		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1021		clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
1022			 <&bpmp TEGRA186_CLK_XUSB_SS>,
1023			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1024			 <&bpmp TEGRA186_CLK_XUSB_FS>;
1025		clock-names = "dev", "ss", "ss_src", "fs_src";
1026		interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>,
1027				<&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>;
1028		interconnect-names = "dma-mem", "write";
1029		iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
1030		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1031				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1032		power-domain-names = "dev", "ss";
1033		nvidia,xusb-padctl = <&padctl>;
1034		status = "disabled";
1035	};
1036
1037	fuse@3820000 {
1038		compatible = "nvidia,tegra186-efuse";
1039		reg = <0x0 0x03820000 0x0 0x10000>;
1040		clocks = <&bpmp TEGRA186_CLK_FUSE>;
1041		clock-names = "fuse";
1042	};
1043
1044	gic: interrupt-controller@3881000 {
1045		compatible = "arm,gic-400";
1046		#interrupt-cells = <3>;
1047		interrupt-controller;
1048		reg = <0x0 0x03881000 0x0 0x1000>,
1049		      <0x0 0x03882000 0x0 0x2000>,
1050		      <0x0 0x03884000 0x0 0x2000>,
1051		      <0x0 0x03886000 0x0 0x2000>;
1052		interrupts = <GIC_PPI 9
1053			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1054		interrupt-parent = <&gic>;
1055	};
1056
1057	cec@3960000 {
1058		compatible = "nvidia,tegra186-cec";
1059		reg = <0x0 0x03960000 0x0 0x10000>;
1060		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1061		clocks = <&bpmp TEGRA186_CLK_CEC>;
1062		clock-names = "cec";
1063		status = "disabled";
1064	};
1065
1066	hsp_top0: hsp@3c00000 {
1067		compatible = "nvidia,tegra186-hsp";
1068		reg = <0x0 0x03c00000 0x0 0xa0000>;
1069		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1070		interrupt-names = "doorbell";
1071		#mbox-cells = <2>;
1072		status = "disabled";
1073	};
1074
1075	gen2_i2c: i2c@c240000 {
1076		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
1077		reg = <0x0 0x0c240000 0x0 0x10000>;
1078		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1079		#address-cells = <1>;
1080		#size-cells = <0>;
1081		clocks = <&bpmp TEGRA186_CLK_I2C2>;
1082		clock-names = "div-clk";
1083		resets = <&bpmp TEGRA186_RESET_I2C2>;
1084		reset-names = "i2c";
1085		status = "disabled";
1086	};
1087
1088	gen8_i2c: i2c@c250000 {
1089		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
1090		reg = <0x0 0x0c250000 0x0 0x10000>;
1091		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1092		#address-cells = <1>;
1093		#size-cells = <0>;
1094		clocks = <&bpmp TEGRA186_CLK_I2C8>;
1095		clock-names = "div-clk";
1096		resets = <&bpmp TEGRA186_RESET_I2C8>;
1097		reset-names = "i2c";
1098		status = "disabled";
1099	};
1100
1101	uartc: serial@c280000 {
1102		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1103		reg = <0x0 0x0c280000 0x0 0x40>;
1104		reg-shift = <2>;
1105		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1106		clocks = <&bpmp TEGRA186_CLK_UARTC>;
1107		clock-names = "serial";
1108		resets = <&bpmp TEGRA186_RESET_UARTC>;
1109		reset-names = "serial";
1110		status = "disabled";
1111	};
1112
1113	uartg: serial@c290000 {
1114		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1115		reg = <0x0 0x0c290000 0x0 0x40>;
1116		reg-shift = <2>;
1117		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1118		clocks = <&bpmp TEGRA186_CLK_UARTG>;
1119		clock-names = "serial";
1120		resets = <&bpmp TEGRA186_RESET_UARTG>;
1121		reset-names = "serial";
1122		status = "disabled";
1123	};
1124
1125	rtc: rtc@c2a0000 {
1126		compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1127		reg = <0 0x0c2a0000 0 0x10000>;
1128		interrupt-parent = <&pmc>;
1129		interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1130		clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1131		clock-names = "rtc";
1132		status = "disabled";
1133	};
1134
1135	gpio_aon: gpio@c2f0000 {
1136		compatible = "nvidia,tegra186-gpio-aon";
1137		reg-names = "security", "gpio";
1138		reg = <0x0 0xc2f0000 0x0 0x1000>,
1139		      <0x0 0xc2f1000 0x0 0x1000>;
1140		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1141		gpio-controller;
1142		#gpio-cells = <2>;
1143		interrupt-controller;
1144		#interrupt-cells = <2>;
1145	};
1146
1147	pwm4: pwm@c340000 {
1148		compatible = "nvidia,tegra186-pwm";
1149		reg = <0x0 0xc340000 0x0 0x10000>;
1150		clocks = <&bpmp TEGRA186_CLK_PWM4>;
1151		clock-names = "pwm";
1152		resets = <&bpmp TEGRA186_RESET_PWM4>;
1153		reset-names = "pwm";
1154		status = "disabled";
1155		#pwm-cells = <2>;
1156	};
1157
1158	pmc: pmc@c360000 {
1159		compatible = "nvidia,tegra186-pmc";
1160		reg = <0 0x0c360000 0 0x10000>,
1161		      <0 0x0c370000 0 0x10000>,
1162		      <0 0x0c380000 0 0x10000>,
1163		      <0 0x0c390000 0 0x10000>;
1164		reg-names = "pmc", "wake", "aotag", "scratch";
1165
1166		#interrupt-cells = <2>;
1167		interrupt-controller;
1168
1169		sdmmc1_3v3: sdmmc1-3v3 {
1170			pins = "sdmmc1-hv";
1171			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1172		};
1173
1174		sdmmc1_1v8: sdmmc1-1v8 {
1175			pins = "sdmmc1-hv";
1176			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1177		};
1178
1179		sdmmc2_3v3: sdmmc2-3v3 {
1180			pins = "sdmmc2-hv";
1181			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1182		};
1183
1184		sdmmc2_1v8: sdmmc2-1v8 {
1185			pins = "sdmmc2-hv";
1186			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1187		};
1188
1189		sdmmc3_3v3: sdmmc3-3v3 {
1190			pins = "sdmmc3-hv";
1191			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1192		};
1193
1194		sdmmc3_1v8: sdmmc3-1v8 {
1195			pins = "sdmmc3-hv";
1196			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1197		};
1198	};
1199
1200	ccplex@e000000 {
1201		compatible = "nvidia,tegra186-ccplex-cluster";
1202		reg = <0x0 0x0e000000 0x0 0x3fffff>;
1203
1204		nvidia,bpmp = <&bpmp>;
1205	};
1206
1207	pcie@10003000 {
1208		compatible = "nvidia,tegra186-pcie";
1209		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1210		device_type = "pci";
1211		reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1212		      <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1213		      <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1214		reg-names = "pads", "afi", "cs";
1215
1216		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1217			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1218		interrupt-names = "intr", "msi";
1219
1220		#interrupt-cells = <1>;
1221		interrupt-map-mask = <0 0 0 0>;
1222		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1223
1224		bus-range = <0x00 0xff>;
1225		#address-cells = <3>;
1226		#size-cells = <2>;
1227
1228		ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1229			 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1230			 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1231			 <0x01000000 0 0x0        0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1232			 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1233			 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1234
1235		clocks = <&bpmp TEGRA186_CLK_PCIE>,
1236			 <&bpmp TEGRA186_CLK_AFI>,
1237			 <&bpmp TEGRA186_CLK_PLLE>;
1238		clock-names = "pex", "afi", "pll_e";
1239
1240		resets = <&bpmp TEGRA186_RESET_PCIE>,
1241			 <&bpmp TEGRA186_RESET_AFI>,
1242			 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1243		reset-names = "pex", "afi", "pcie_x";
1244
1245		interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
1246				<&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
1247		interconnect-names = "dma-mem", "write";
1248
1249		iommus = <&smmu TEGRA186_SID_AFI>;
1250		iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1251		iommu-map-mask = <0x0>;
1252
1253		status = "disabled";
1254
1255		pci@1,0 {
1256			device_type = "pci";
1257			assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1258			reg = <0x000800 0 0 0 0>;
1259			status = "disabled";
1260
1261			#address-cells = <3>;
1262			#size-cells = <2>;
1263			ranges;
1264
1265			nvidia,num-lanes = <2>;
1266		};
1267
1268		pci@2,0 {
1269			device_type = "pci";
1270			assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1271			reg = <0x001000 0 0 0 0>;
1272			status = "disabled";
1273
1274			#address-cells = <3>;
1275			#size-cells = <2>;
1276			ranges;
1277
1278			nvidia,num-lanes = <1>;
1279		};
1280
1281		pci@3,0 {
1282			device_type = "pci";
1283			assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1284			reg = <0x001800 0 0 0 0>;
1285			status = "disabled";
1286
1287			#address-cells = <3>;
1288			#size-cells = <2>;
1289			ranges;
1290
1291			nvidia,num-lanes = <1>;
1292		};
1293	};
1294
1295	smmu: iommu@12000000 {
1296		compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
1297		reg = <0 0x12000000 0 0x800000>;
1298		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1299			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1300			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1301			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1302			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1303			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1304			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1305			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1306			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1307			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1308			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1309			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1310			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1311			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1312			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1313			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1314			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1315			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1316			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1317			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1318			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1319			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1320			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1321			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1322			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1323			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1324			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1325			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1326			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1327			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1328			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1329			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1330			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1331			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1332			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1333			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1334			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1335			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1336			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1337			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1338			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1339			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1340			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1341			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1342			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1343			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1344			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1345			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1346			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1347			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1348			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1349			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1350			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1351			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1352			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1353			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1354			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1355			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1356			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1357			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1358			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1359			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1360			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1361			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1362			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1363		stream-match-mask = <0x7f80>;
1364		#global-interrupts = <1>;
1365		#iommu-cells = <1>;
1366
1367		nvidia,memory-controller = <&mc>;
1368	};
1369
1370	host1x@13e00000 {
1371		compatible = "nvidia,tegra186-host1x";
1372		reg = <0x0 0x13e00000 0x0 0x10000>,
1373		      <0x0 0x13e10000 0x0 0x10000>;
1374		reg-names = "hypervisor", "vm";
1375		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1376		             <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1377		interrupt-names = "syncpt", "host1x";
1378		clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1379		clock-names = "host1x";
1380		resets = <&bpmp TEGRA186_RESET_HOST1X>;
1381		reset-names = "host1x";
1382
1383		#address-cells = <1>;
1384		#size-cells = <1>;
1385
1386		ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1387
1388		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
1389		interconnect-names = "dma-mem";
1390
1391		iommus = <&smmu TEGRA186_SID_HOST1X>;
1392
1393		dpaux1: dpaux@15040000 {
1394			compatible = "nvidia,tegra186-dpaux";
1395			reg = <0x15040000 0x10000>;
1396			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1397			clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1398				 <&bpmp TEGRA186_CLK_PLLDP>;
1399			clock-names = "dpaux", "parent";
1400			resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1401			reset-names = "dpaux";
1402			status = "disabled";
1403
1404			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1405
1406			state_dpaux1_aux: pinmux-aux {
1407				groups = "dpaux-io";
1408				function = "aux";
1409			};
1410
1411			state_dpaux1_i2c: pinmux-i2c {
1412				groups = "dpaux-io";
1413				function = "i2c";
1414			};
1415
1416			state_dpaux1_off: pinmux-off {
1417				groups = "dpaux-io";
1418				function = "off";
1419			};
1420
1421			i2c-bus {
1422				#address-cells = <1>;
1423				#size-cells = <0>;
1424			};
1425		};
1426
1427		display-hub@15200000 {
1428			compatible = "nvidia,tegra186-display";
1429			reg = <0x15200000 0x00040000>;
1430			resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1431				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1432				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1433				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1434				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1435				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1436				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1437			reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1438				      "wgrp3", "wgrp4", "wgrp5";
1439			clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1440				 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1441				 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1442			clock-names = "disp", "dsc", "hub";
1443			status = "disabled";
1444
1445			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1446
1447			#address-cells = <1>;
1448			#size-cells = <1>;
1449
1450			ranges = <0x15200000 0x15200000 0x40000>;
1451
1452			display@15200000 {
1453				compatible = "nvidia,tegra186-dc";
1454				reg = <0x15200000 0x10000>;
1455				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1456				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1457				clock-names = "dc";
1458				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1459				reset-names = "dc";
1460
1461				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1462				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1463						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1464				interconnect-names = "dma-mem", "read-1";
1465				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1466
1467				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1468				nvidia,head = <0>;
1469			};
1470
1471			display@15210000 {
1472				compatible = "nvidia,tegra186-dc";
1473				reg = <0x15210000 0x10000>;
1474				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1475				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1476				clock-names = "dc";
1477				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1478				reset-names = "dc";
1479
1480				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1481				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1482						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1483				interconnect-names = "dma-mem", "read-1";
1484				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1485
1486				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1487				nvidia,head = <1>;
1488			};
1489
1490			display@15220000 {
1491				compatible = "nvidia,tegra186-dc";
1492				reg = <0x15220000 0x10000>;
1493				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1494				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1495				clock-names = "dc";
1496				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1497				reset-names = "dc";
1498
1499				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1500				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1501						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1502				interconnect-names = "dma-mem", "read-1";
1503				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1504
1505				nvidia,outputs = <&sor0 &sor1>;
1506				nvidia,head = <2>;
1507			};
1508		};
1509
1510		dsia: dsi@15300000 {
1511			compatible = "nvidia,tegra186-dsi";
1512			reg = <0x15300000 0x10000>;
1513			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1514			clocks = <&bpmp TEGRA186_CLK_DSI>,
1515				 <&bpmp TEGRA186_CLK_DSIA_LP>,
1516				 <&bpmp TEGRA186_CLK_PLLD>;
1517			clock-names = "dsi", "lp", "parent";
1518			resets = <&bpmp TEGRA186_RESET_DSI>;
1519			reset-names = "dsi";
1520			status = "disabled";
1521
1522			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1523		};
1524
1525		vic@15340000 {
1526			compatible = "nvidia,tegra186-vic";
1527			reg = <0x15340000 0x40000>;
1528			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1529			clocks = <&bpmp TEGRA186_CLK_VIC>;
1530			clock-names = "vic";
1531			resets = <&bpmp TEGRA186_RESET_VIC>;
1532			reset-names = "vic";
1533
1534			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1535			interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
1536					<&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
1537			interconnect-names = "dma-mem", "write";
1538			iommus = <&smmu TEGRA186_SID_VIC>;
1539		};
1540
1541		dsib: dsi@15400000 {
1542			compatible = "nvidia,tegra186-dsi";
1543			reg = <0x15400000 0x10000>;
1544			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1545			clocks = <&bpmp TEGRA186_CLK_DSIB>,
1546				 <&bpmp TEGRA186_CLK_DSIB_LP>,
1547				 <&bpmp TEGRA186_CLK_PLLD>;
1548			clock-names = "dsi", "lp", "parent";
1549			resets = <&bpmp TEGRA186_RESET_DSIB>;
1550			reset-names = "dsi";
1551			status = "disabled";
1552
1553			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1554		};
1555
1556		nvdec@15480000 {
1557			compatible = "nvidia,tegra186-nvdec";
1558			reg = <0x15480000 0x40000>;
1559			clocks = <&bpmp TEGRA186_CLK_NVDEC>;
1560			clock-names = "nvdec";
1561			resets = <&bpmp TEGRA186_RESET_NVDEC>;
1562			reset-names = "nvdec";
1563
1564			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1565			interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
1566					<&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
1567					<&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
1568			interconnect-names = "dma-mem", "read-1", "write";
1569			iommus = <&smmu TEGRA186_SID_NVDEC>;
1570		};
1571
1572		sor0: sor@15540000 {
1573			compatible = "nvidia,tegra186-sor";
1574			reg = <0x15540000 0x10000>;
1575			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1576			clocks = <&bpmp TEGRA186_CLK_SOR0>,
1577				 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1578				 <&bpmp TEGRA186_CLK_PLLD2>,
1579				 <&bpmp TEGRA186_CLK_PLLDP>,
1580				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1581				 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1582			clock-names = "sor", "out", "parent", "dp", "safe",
1583				      "pad";
1584			resets = <&bpmp TEGRA186_RESET_SOR0>;
1585			reset-names = "sor";
1586			pinctrl-0 = <&state_dpaux_aux>;
1587			pinctrl-1 = <&state_dpaux_i2c>;
1588			pinctrl-2 = <&state_dpaux_off>;
1589			pinctrl-names = "aux", "i2c", "off";
1590			status = "disabled";
1591
1592			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1593			nvidia,interface = <0>;
1594		};
1595
1596		sor1: sor@15580000 {
1597			compatible = "nvidia,tegra186-sor";
1598			reg = <0x15580000 0x10000>;
1599			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1600			clocks = <&bpmp TEGRA186_CLK_SOR1>,
1601				 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1602				 <&bpmp TEGRA186_CLK_PLLD3>,
1603				 <&bpmp TEGRA186_CLK_PLLDP>,
1604				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1605				 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1606			clock-names = "sor", "out", "parent", "dp", "safe",
1607				      "pad";
1608			resets = <&bpmp TEGRA186_RESET_SOR1>;
1609			reset-names = "sor";
1610			pinctrl-0 = <&state_dpaux1_aux>;
1611			pinctrl-1 = <&state_dpaux1_i2c>;
1612			pinctrl-2 = <&state_dpaux1_off>;
1613			pinctrl-names = "aux", "i2c", "off";
1614			status = "disabled";
1615
1616			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1617			nvidia,interface = <1>;
1618		};
1619
1620		dpaux: dpaux@155c0000 {
1621			compatible = "nvidia,tegra186-dpaux";
1622			reg = <0x155c0000 0x10000>;
1623			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1624			clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1625				 <&bpmp TEGRA186_CLK_PLLDP>;
1626			clock-names = "dpaux", "parent";
1627			resets = <&bpmp TEGRA186_RESET_DPAUX>;
1628			reset-names = "dpaux";
1629			status = "disabled";
1630
1631			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1632
1633			state_dpaux_aux: pinmux-aux {
1634				groups = "dpaux-io";
1635				function = "aux";
1636			};
1637
1638			state_dpaux_i2c: pinmux-i2c {
1639				groups = "dpaux-io";
1640				function = "i2c";
1641			};
1642
1643			state_dpaux_off: pinmux-off {
1644				groups = "dpaux-io";
1645				function = "off";
1646			};
1647
1648			i2c-bus {
1649				#address-cells = <1>;
1650				#size-cells = <0>;
1651			};
1652		};
1653
1654		padctl@15880000 {
1655			compatible = "nvidia,tegra186-dsi-padctl";
1656			reg = <0x15880000 0x10000>;
1657			resets = <&bpmp TEGRA186_RESET_DSI>;
1658			reset-names = "dsi";
1659			status = "disabled";
1660		};
1661
1662		dsic: dsi@15900000 {
1663			compatible = "nvidia,tegra186-dsi";
1664			reg = <0x15900000 0x10000>;
1665			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1666			clocks = <&bpmp TEGRA186_CLK_DSIC>,
1667				 <&bpmp TEGRA186_CLK_DSIC_LP>,
1668				 <&bpmp TEGRA186_CLK_PLLD>;
1669			clock-names = "dsi", "lp", "parent";
1670			resets = <&bpmp TEGRA186_RESET_DSIC>;
1671			reset-names = "dsi";
1672			status = "disabled";
1673
1674			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1675		};
1676
1677		dsid: dsi@15940000 {
1678			compatible = "nvidia,tegra186-dsi";
1679			reg = <0x15940000 0x10000>;
1680			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1681			clocks = <&bpmp TEGRA186_CLK_DSID>,
1682				 <&bpmp TEGRA186_CLK_DSID_LP>,
1683				 <&bpmp TEGRA186_CLK_PLLD>;
1684			clock-names = "dsi", "lp", "parent";
1685			resets = <&bpmp TEGRA186_RESET_DSID>;
1686			reset-names = "dsi";
1687			status = "disabled";
1688
1689			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1690		};
1691	};
1692
1693	gpu@17000000 {
1694		compatible = "nvidia,gp10b";
1695		reg = <0x0 0x17000000 0x0 0x1000000>,
1696		      <0x0 0x18000000 0x0 0x1000000>;
1697		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1698			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1699		interrupt-names = "stall", "nonstall";
1700
1701		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1702			 <&bpmp TEGRA186_CLK_GPU>;
1703		clock-names = "gpu", "pwr";
1704		resets = <&bpmp TEGRA186_RESET_GPU>;
1705		reset-names = "gpu";
1706		status = "disabled";
1707
1708		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1709		interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
1710				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
1711				<&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
1712				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
1713		interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1714	};
1715
1716	sram@30000000 {
1717		compatible = "nvidia,tegra186-sysram", "mmio-sram";
1718		reg = <0x0 0x30000000 0x0 0x50000>;
1719		#address-cells = <1>;
1720		#size-cells = <1>;
1721		ranges = <0x0 0x0 0x30000000 0x50000>;
1722
1723		cpu_bpmp_tx: sram@4e000 {
1724			reg = <0x4e000 0x1000>;
1725			label = "cpu-bpmp-tx";
1726			pool;
1727		};
1728
1729		cpu_bpmp_rx: sram@4f000 {
1730			reg = <0x4f000 0x1000>;
1731			label = "cpu-bpmp-rx";
1732			pool;
1733		};
1734	};
1735
1736	sata@3507000 {
1737		compatible = "nvidia,tegra186-ahci";
1738		reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
1739		      <0x0 0x03500000 0x0 0x00007000>, /* SATA */
1740		      <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
1741		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1742
1743		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
1744		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,
1745				<&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;
1746		interconnect-names = "dma-mem", "write";
1747		iommus = <&smmu TEGRA186_SID_SATA>;
1748
1749		clocks = <&bpmp TEGRA186_CLK_SATA>,
1750			 <&bpmp TEGRA186_CLK_SATA_OOB>;
1751		clock-names = "sata", "sata-oob";
1752		assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
1753				  <&bpmp TEGRA186_CLK_SATA_OOB>;
1754		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
1755					 <&bpmp TEGRA186_CLK_PLLP>;
1756		assigned-clock-rates = <102000000>,
1757				       <204000000>;
1758		resets = <&bpmp TEGRA186_RESET_SATA>,
1759			<&bpmp TEGRA186_RESET_SATACOLD>;
1760		reset-names = "sata", "sata-cold";
1761		status = "disabled";
1762	};
1763
1764	bpmp: bpmp {
1765		compatible = "nvidia,tegra186-bpmp";
1766		interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
1767				<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
1768				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
1769				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
1770		interconnect-names = "read", "write", "dma-mem", "dma-write";
1771		iommus = <&smmu TEGRA186_SID_BPMP>;
1772		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1773				    TEGRA_HSP_DB_MASTER_BPMP>;
1774		shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1775		#clock-cells = <1>;
1776		#reset-cells = <1>;
1777		#power-domain-cells = <1>;
1778
1779		bpmp_i2c: i2c {
1780			compatible = "nvidia,tegra186-bpmp-i2c";
1781			nvidia,bpmp-bus-id = <5>;
1782			#address-cells = <1>;
1783			#size-cells = <0>;
1784			status = "disabled";
1785		};
1786
1787		bpmp_thermal: thermal {
1788			compatible = "nvidia,tegra186-bpmp-thermal";
1789			#thermal-sensor-cells = <1>;
1790		};
1791	};
1792
1793	cpus {
1794		#address-cells = <1>;
1795		#size-cells = <0>;
1796
1797		denver_0: cpu@0 {
1798			compatible = "nvidia,tegra186-denver";
1799			device_type = "cpu";
1800			i-cache-size = <0x20000>;
1801			i-cache-line-size = <64>;
1802			i-cache-sets = <512>;
1803			d-cache-size = <0x10000>;
1804			d-cache-line-size = <64>;
1805			d-cache-sets = <256>;
1806			next-level-cache = <&L2_DENVER>;
1807			reg = <0x000>;
1808		};
1809
1810		denver_1: cpu@1 {
1811			compatible = "nvidia,tegra186-denver";
1812			device_type = "cpu";
1813			i-cache-size = <0x20000>;
1814			i-cache-line-size = <64>;
1815			i-cache-sets = <512>;
1816			d-cache-size = <0x10000>;
1817			d-cache-line-size = <64>;
1818			d-cache-sets = <256>;
1819			next-level-cache = <&L2_DENVER>;
1820			reg = <0x001>;
1821		};
1822
1823		ca57_0: cpu@2 {
1824			compatible = "arm,cortex-a57";
1825			device_type = "cpu";
1826			i-cache-size = <0xC000>;
1827			i-cache-line-size = <64>;
1828			i-cache-sets = <256>;
1829			d-cache-size = <0x8000>;
1830			d-cache-line-size = <64>;
1831			d-cache-sets = <256>;
1832			next-level-cache = <&L2_A57>;
1833			reg = <0x100>;
1834		};
1835
1836		ca57_1: cpu@3 {
1837			compatible = "arm,cortex-a57";
1838			device_type = "cpu";
1839			i-cache-size = <0xC000>;
1840			i-cache-line-size = <64>;
1841			i-cache-sets = <256>;
1842			d-cache-size = <0x8000>;
1843			d-cache-line-size = <64>;
1844			d-cache-sets = <256>;
1845			next-level-cache = <&L2_A57>;
1846			reg = <0x101>;
1847		};
1848
1849		ca57_2: cpu@4 {
1850			compatible = "arm,cortex-a57";
1851			device_type = "cpu";
1852			i-cache-size = <0xC000>;
1853			i-cache-line-size = <64>;
1854			i-cache-sets = <256>;
1855			d-cache-size = <0x8000>;
1856			d-cache-line-size = <64>;
1857			d-cache-sets = <256>;
1858			next-level-cache = <&L2_A57>;
1859			reg = <0x102>;
1860		};
1861
1862		ca57_3: cpu@5 {
1863			compatible = "arm,cortex-a57";
1864			device_type = "cpu";
1865			i-cache-size = <0xC000>;
1866			i-cache-line-size = <64>;
1867			i-cache-sets = <256>;
1868			d-cache-size = <0x8000>;
1869			d-cache-line-size = <64>;
1870			d-cache-sets = <256>;
1871			next-level-cache = <&L2_A57>;
1872			reg = <0x103>;
1873		};
1874
1875		L2_DENVER: l2-cache0 {
1876			compatible = "cache";
1877			cache-unified;
1878			cache-level = <2>;
1879			cache-size = <0x200000>;
1880			cache-line-size = <64>;
1881			cache-sets = <2048>;
1882		};
1883
1884		L2_A57: l2-cache1 {
1885			compatible = "cache";
1886			cache-unified;
1887			cache-level = <2>;
1888			cache-size = <0x200000>;
1889			cache-line-size = <64>;
1890			cache-sets = <2048>;
1891		};
1892	};
1893
1894	pmu_denver {
1895		compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
1896		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1897			     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1898		interrupt-affinity = <&denver_0 &denver_1>;
1899	};
1900
1901	pmu_a57 {
1902		compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
1903		interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1904			     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1905			     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1906			     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1907		interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
1908	};
1909
1910	sound {
1911		status = "disabled";
1912
1913		clocks = <&bpmp TEGRA186_CLK_PLLA>,
1914			 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
1915		clock-names = "pll_a", "plla_out0";
1916		assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
1917				  <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
1918				  <&bpmp TEGRA186_CLK_AUD_MCLK>;
1919		assigned-clock-parents = <0>,
1920					 <&bpmp TEGRA186_CLK_PLLA>,
1921					 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
1922		/*
1923		 * PLLA supports dynamic ramp. Below initial rate is chosen
1924		 * for this to work and oscillate between base rates required
1925		 * for 8x and 11.025x sample rate streams.
1926		 */
1927		assigned-clock-rates = <258000000>;
1928
1929		iommus = <&smmu TEGRA186_SID_APE>;
1930	};
1931
1932	thermal-zones {
1933		a57 {
1934			polling-delay = <0>;
1935			polling-delay-passive = <1000>;
1936
1937			thermal-sensors =
1938				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
1939
1940			trips {
1941				critical {
1942					temperature = <101000>;
1943					hysteresis = <0>;
1944					type = "critical";
1945				};
1946			};
1947
1948			cooling-maps {
1949			};
1950		};
1951
1952		denver {
1953			polling-delay = <0>;
1954			polling-delay-passive = <1000>;
1955
1956			thermal-sensors =
1957				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
1958
1959			trips {
1960				critical {
1961					temperature = <101000>;
1962					hysteresis = <0>;
1963					type = "critical";
1964				};
1965			};
1966
1967			cooling-maps {
1968			};
1969		};
1970
1971		gpu {
1972			polling-delay = <0>;
1973			polling-delay-passive = <1000>;
1974
1975			thermal-sensors =
1976				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
1977
1978			trips {
1979				critical {
1980					temperature = <101000>;
1981					hysteresis = <0>;
1982					type = "critical";
1983				};
1984			};
1985
1986			cooling-maps {
1987			};
1988		};
1989
1990		pll {
1991			polling-delay = <0>;
1992			polling-delay-passive = <1000>;
1993
1994			thermal-sensors =
1995				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
1996
1997			trips {
1998				critical {
1999					temperature = <101000>;
2000					hysteresis = <0>;
2001					type = "critical";
2002				};
2003			};
2004
2005			cooling-maps {
2006			};
2007		};
2008
2009		always_on {
2010			polling-delay = <0>;
2011			polling-delay-passive = <1000>;
2012
2013			thermal-sensors =
2014				<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2015
2016			trips {
2017				critical {
2018					temperature = <101000>;
2019					hysteresis = <0>;
2020					type = "critical";
2021				};
2022			};
2023
2024			cooling-maps {
2025			};
2026		};
2027	};
2028
2029	timer {
2030		compatible = "arm,armv8-timer";
2031		interrupts = <GIC_PPI 13
2032				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2033			     <GIC_PPI 14
2034				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2035			     <GIC_PPI 11
2036				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2037			     <GIC_PPI 10
2038				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2039		interrupt-parent = <&gic>;
2040		always-on;
2041	};
2042};
2043