1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 gpcdma: dma-controller@2600000 { 77 compatible = "nvidia,tegra186-gpcdma"; 78 reg = <0x0 0x2600000 0x0 0x210000>; 79 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80 reset-names = "gpcdma"; 81 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 113 #dma-cells = <1>; 114 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 115 dma-coherent; 116 dma-channel-mask = <0xfffffffe>; 117 status = "okay"; 118 }; 119 120 aconnect@2900000 { 121 compatible = "nvidia,tegra186-aconnect", 122 "nvidia,tegra210-aconnect"; 123 clocks = <&bpmp TEGRA186_CLK_APE>, 124 <&bpmp TEGRA186_CLK_APB2APE>; 125 clock-names = "ape", "apb2ape"; 126 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 127 #address-cells = <1>; 128 #size-cells = <1>; 129 ranges = <0x02900000 0x0 0x02900000 0x200000>; 130 status = "disabled"; 131 132 tegra_ahub: ahub@2900800 { 133 compatible = "nvidia,tegra186-ahub"; 134 reg = <0x02900800 0x800>; 135 clocks = <&bpmp TEGRA186_CLK_AHUB>; 136 clock-names = "ahub"; 137 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 ranges = <0x02900800 0x02900800 0x11800>; 142 status = "disabled"; 143 144 tegra_i2s1: i2s@2901000 { 145 compatible = "nvidia,tegra186-i2s", 146 "nvidia,tegra210-i2s"; 147 reg = <0x2901000 0x100>; 148 clocks = <&bpmp TEGRA186_CLK_I2S1>, 149 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 150 clock-names = "i2s", "sync_input"; 151 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 152 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 153 assigned-clock-rates = <1536000>; 154 sound-name-prefix = "I2S1"; 155 status = "disabled"; 156 }; 157 158 tegra_i2s2: i2s@2901100 { 159 compatible = "nvidia,tegra186-i2s", 160 "nvidia,tegra210-i2s"; 161 reg = <0x2901100 0x100>; 162 clocks = <&bpmp TEGRA186_CLK_I2S2>, 163 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 164 clock-names = "i2s", "sync_input"; 165 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 166 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 167 assigned-clock-rates = <1536000>; 168 sound-name-prefix = "I2S2"; 169 status = "disabled"; 170 }; 171 172 tegra_i2s3: i2s@2901200 { 173 compatible = "nvidia,tegra186-i2s", 174 "nvidia,tegra210-i2s"; 175 reg = <0x2901200 0x100>; 176 clocks = <&bpmp TEGRA186_CLK_I2S3>, 177 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 178 clock-names = "i2s", "sync_input"; 179 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 180 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 181 assigned-clock-rates = <1536000>; 182 sound-name-prefix = "I2S3"; 183 status = "disabled"; 184 }; 185 186 tegra_i2s4: i2s@2901300 { 187 compatible = "nvidia,tegra186-i2s", 188 "nvidia,tegra210-i2s"; 189 reg = <0x2901300 0x100>; 190 clocks = <&bpmp TEGRA186_CLK_I2S4>, 191 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 192 clock-names = "i2s", "sync_input"; 193 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 194 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 195 assigned-clock-rates = <1536000>; 196 sound-name-prefix = "I2S4"; 197 status = "disabled"; 198 }; 199 200 tegra_i2s5: i2s@2901400 { 201 compatible = "nvidia,tegra186-i2s", 202 "nvidia,tegra210-i2s"; 203 reg = <0x2901400 0x100>; 204 clocks = <&bpmp TEGRA186_CLK_I2S5>, 205 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 206 clock-names = "i2s", "sync_input"; 207 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 208 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 209 assigned-clock-rates = <1536000>; 210 sound-name-prefix = "I2S5"; 211 status = "disabled"; 212 }; 213 214 tegra_i2s6: i2s@2901500 { 215 compatible = "nvidia,tegra186-i2s", 216 "nvidia,tegra210-i2s"; 217 reg = <0x2901500 0x100>; 218 clocks = <&bpmp TEGRA186_CLK_I2S6>, 219 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 220 clock-names = "i2s", "sync_input"; 221 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 222 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 223 assigned-clock-rates = <1536000>; 224 sound-name-prefix = "I2S6"; 225 status = "disabled"; 226 }; 227 228 tegra_sfc1: sfc@2902000 { 229 compatible = "nvidia,tegra186-sfc", 230 "nvidia,tegra210-sfc"; 231 reg = <0x2902000 0x200>; 232 sound-name-prefix = "SFC1"; 233 status = "disabled"; 234 }; 235 236 tegra_sfc2: sfc@2902200 { 237 compatible = "nvidia,tegra186-sfc", 238 "nvidia,tegra210-sfc"; 239 reg = <0x2902200 0x200>; 240 sound-name-prefix = "SFC2"; 241 status = "disabled"; 242 }; 243 244 tegra_sfc3: sfc@2902400 { 245 compatible = "nvidia,tegra186-sfc", 246 "nvidia,tegra210-sfc"; 247 reg = <0x2902400 0x200>; 248 sound-name-prefix = "SFC3"; 249 status = "disabled"; 250 }; 251 252 tegra_sfc4: sfc@2902600 { 253 compatible = "nvidia,tegra186-sfc", 254 "nvidia,tegra210-sfc"; 255 reg = <0x2902600 0x200>; 256 sound-name-prefix = "SFC4"; 257 status = "disabled"; 258 }; 259 260 tegra_amx1: amx@2903000 { 261 compatible = "nvidia,tegra186-amx", 262 "nvidia,tegra210-amx"; 263 reg = <0x2903000 0x100>; 264 sound-name-prefix = "AMX1"; 265 status = "disabled"; 266 }; 267 268 tegra_amx2: amx@2903100 { 269 compatible = "nvidia,tegra186-amx", 270 "nvidia,tegra210-amx"; 271 reg = <0x2903100 0x100>; 272 sound-name-prefix = "AMX2"; 273 status = "disabled"; 274 }; 275 276 tegra_amx3: amx@2903200 { 277 compatible = "nvidia,tegra186-amx", 278 "nvidia,tegra210-amx"; 279 reg = <0x2903200 0x100>; 280 sound-name-prefix = "AMX3"; 281 status = "disabled"; 282 }; 283 284 tegra_amx4: amx@2903300 { 285 compatible = "nvidia,tegra186-amx", 286 "nvidia,tegra210-amx"; 287 reg = <0x2903300 0x100>; 288 sound-name-prefix = "AMX4"; 289 status = "disabled"; 290 }; 291 292 tegra_adx1: adx@2903800 { 293 compatible = "nvidia,tegra186-adx", 294 "nvidia,tegra210-adx"; 295 reg = <0x2903800 0x100>; 296 sound-name-prefix = "ADX1"; 297 status = "disabled"; 298 }; 299 300 tegra_adx2: adx@2903900 { 301 compatible = "nvidia,tegra186-adx", 302 "nvidia,tegra210-adx"; 303 reg = <0x2903900 0x100>; 304 sound-name-prefix = "ADX2"; 305 status = "disabled"; 306 }; 307 308 tegra_adx3: adx@2903a00 { 309 compatible = "nvidia,tegra186-adx", 310 "nvidia,tegra210-adx"; 311 reg = <0x2903a00 0x100>; 312 sound-name-prefix = "ADX3"; 313 status = "disabled"; 314 }; 315 316 tegra_adx4: adx@2903b00 { 317 compatible = "nvidia,tegra186-adx", 318 "nvidia,tegra210-adx"; 319 reg = <0x2903b00 0x100>; 320 sound-name-prefix = "ADX4"; 321 status = "disabled"; 322 }; 323 324 tegra_dmic1: dmic@2904000 { 325 compatible = "nvidia,tegra210-dmic"; 326 reg = <0x2904000 0x100>; 327 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 328 clock-names = "dmic"; 329 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 330 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 331 assigned-clock-rates = <3072000>; 332 sound-name-prefix = "DMIC1"; 333 status = "disabled"; 334 }; 335 336 tegra_dmic2: dmic@2904100 { 337 compatible = "nvidia,tegra210-dmic"; 338 reg = <0x2904100 0x100>; 339 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 340 clock-names = "dmic"; 341 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 342 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 343 assigned-clock-rates = <3072000>; 344 sound-name-prefix = "DMIC2"; 345 status = "disabled"; 346 }; 347 348 tegra_dmic3: dmic@2904200 { 349 compatible = "nvidia,tegra210-dmic"; 350 reg = <0x2904200 0x100>; 351 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 352 clock-names = "dmic"; 353 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 354 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 355 assigned-clock-rates = <3072000>; 356 sound-name-prefix = "DMIC3"; 357 status = "disabled"; 358 }; 359 360 tegra_dmic4: dmic@2904300 { 361 compatible = "nvidia,tegra210-dmic"; 362 reg = <0x2904300 0x100>; 363 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 364 clock-names = "dmic"; 365 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 366 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 367 assigned-clock-rates = <3072000>; 368 sound-name-prefix = "DMIC4"; 369 status = "disabled"; 370 }; 371 372 tegra_dspk1: dspk@2905000 { 373 compatible = "nvidia,tegra186-dspk"; 374 reg = <0x2905000 0x100>; 375 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 376 clock-names = "dspk"; 377 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 378 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 379 assigned-clock-rates = <12288000>; 380 sound-name-prefix = "DSPK1"; 381 status = "disabled"; 382 }; 383 384 tegra_dspk2: dspk@2905100 { 385 compatible = "nvidia,tegra186-dspk"; 386 reg = <0x2905100 0x100>; 387 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 388 clock-names = "dspk"; 389 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 390 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 391 assigned-clock-rates = <12288000>; 392 sound-name-prefix = "DSPK2"; 393 status = "disabled"; 394 }; 395 396 tegra_ope1: processing-engine@2908000 { 397 compatible = "nvidia,tegra186-ope", 398 "nvidia,tegra210-ope"; 399 reg = <0x2908000 0x100>; 400 #address-cells = <1>; 401 #size-cells = <1>; 402 ranges; 403 sound-name-prefix = "OPE1"; 404 status = "disabled"; 405 406 equalizer@2908100 { 407 compatible = "nvidia,tegra186-peq", 408 "nvidia,tegra210-peq"; 409 reg = <0x2908100 0x100>; 410 }; 411 412 dynamic-range-compressor@2908200 { 413 compatible = "nvidia,tegra186-mbdrc", 414 "nvidia,tegra210-mbdrc"; 415 reg = <0x2908200 0x200>; 416 }; 417 }; 418 419 tegra_mvc1: mvc@290a000 { 420 compatible = "nvidia,tegra186-mvc", 421 "nvidia,tegra210-mvc"; 422 reg = <0x290a000 0x200>; 423 sound-name-prefix = "MVC1"; 424 status = "disabled"; 425 }; 426 427 tegra_mvc2: mvc@290a200 { 428 compatible = "nvidia,tegra186-mvc", 429 "nvidia,tegra210-mvc"; 430 reg = <0x290a200 0x200>; 431 sound-name-prefix = "MVC2"; 432 status = "disabled"; 433 }; 434 435 tegra_amixer: amixer@290bb00 { 436 compatible = "nvidia,tegra186-amixer", 437 "nvidia,tegra210-amixer"; 438 reg = <0x290bb00 0x800>; 439 sound-name-prefix = "MIXER1"; 440 status = "disabled"; 441 }; 442 443 tegra_admaif: admaif@290f000 { 444 compatible = "nvidia,tegra186-admaif"; 445 reg = <0x0290f000 0x1000>; 446 dmas = <&adma 1>, <&adma 1>, 447 <&adma 2>, <&adma 2>, 448 <&adma 3>, <&adma 3>, 449 <&adma 4>, <&adma 4>, 450 <&adma 5>, <&adma 5>, 451 <&adma 6>, <&adma 6>, 452 <&adma 7>, <&adma 7>, 453 <&adma 8>, <&adma 8>, 454 <&adma 9>, <&adma 9>, 455 <&adma 10>, <&adma 10>, 456 <&adma 11>, <&adma 11>, 457 <&adma 12>, <&adma 12>, 458 <&adma 13>, <&adma 13>, 459 <&adma 14>, <&adma 14>, 460 <&adma 15>, <&adma 15>, 461 <&adma 16>, <&adma 16>, 462 <&adma 17>, <&adma 17>, 463 <&adma 18>, <&adma 18>, 464 <&adma 19>, <&adma 19>, 465 <&adma 20>, <&adma 20>; 466 dma-names = "rx1", "tx1", 467 "rx2", "tx2", 468 "rx3", "tx3", 469 "rx4", "tx4", 470 "rx5", "tx5", 471 "rx6", "tx6", 472 "rx7", "tx7", 473 "rx8", "tx8", 474 "rx9", "tx9", 475 "rx10", "tx10", 476 "rx11", "tx11", 477 "rx12", "tx12", 478 "rx13", "tx13", 479 "rx14", "tx14", 480 "rx15", "tx15", 481 "rx16", "tx16", 482 "rx17", "tx17", 483 "rx18", "tx18", 484 "rx19", "tx19", 485 "rx20", "tx20"; 486 status = "disabled"; 487 }; 488 489 tegra_asrc: asrc@2910000 { 490 compatible = "nvidia,tegra186-asrc"; 491 reg = <0x2910000 0x2000>; 492 sound-name-prefix = "ASRC1"; 493 status = "disabled"; 494 }; 495 }; 496 497 adma: dma-controller@2930000 { 498 compatible = "nvidia,tegra186-adma"; 499 reg = <0x02930000 0x20000>; 500 interrupt-parent = <&agic>; 501 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 533 #dma-cells = <1>; 534 clocks = <&bpmp TEGRA186_CLK_AHUB>; 535 clock-names = "d_audio"; 536 status = "disabled"; 537 }; 538 539 agic: interrupt-controller@2a40000 { 540 compatible = "nvidia,tegra186-agic", 541 "nvidia,tegra210-agic"; 542 #interrupt-cells = <3>; 543 interrupt-controller; 544 reg = <0x02a41000 0x1000>, 545 <0x02a42000 0x2000>; 546 interrupts = <GIC_SPI 145 547 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 548 clocks = <&bpmp TEGRA186_CLK_APE>; 549 clock-names = "clk"; 550 status = "disabled"; 551 }; 552 }; 553 554 mc: memory-controller@2c00000 { 555 compatible = "nvidia,tegra186-mc"; 556 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 557 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 558 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 559 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 560 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 561 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 562 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 563 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 564 status = "disabled"; 565 566 #interconnect-cells = <1>; 567 #address-cells = <2>; 568 #size-cells = <2>; 569 570 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 571 572 /* 573 * Memory clients have access to all 40 bits that the memory 574 * controller can address. 575 */ 576 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 577 578 emc: external-memory-controller@2c60000 { 579 compatible = "nvidia,tegra186-emc"; 580 reg = <0x0 0x02c60000 0x0 0x50000>; 581 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&bpmp TEGRA186_CLK_EMC>; 583 clock-names = "emc"; 584 585 #interconnect-cells = <0>; 586 587 nvidia,bpmp = <&bpmp>; 588 }; 589 }; 590 591 timer@3010000 { 592 compatible = "nvidia,tegra186-timer"; 593 reg = <0x0 0x03010000 0x0 0x000e0000>; 594 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 604 status = "okay"; 605 }; 606 607 uarta: serial@3100000 { 608 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 609 reg = <0x0 0x03100000 0x0 0x40>; 610 reg-shift = <2>; 611 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&bpmp TEGRA186_CLK_UARTA>; 613 clock-names = "serial"; 614 resets = <&bpmp TEGRA186_RESET_UARTA>; 615 reset-names = "serial"; 616 status = "disabled"; 617 }; 618 619 uartb: serial@3110000 { 620 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 621 reg = <0x0 0x03110000 0x0 0x40>; 622 reg-shift = <2>; 623 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&bpmp TEGRA186_CLK_UARTB>; 625 clock-names = "serial"; 626 resets = <&bpmp TEGRA186_RESET_UARTB>; 627 reset-names = "serial"; 628 status = "disabled"; 629 }; 630 631 uartd: serial@3130000 { 632 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 633 reg = <0x0 0x03130000 0x0 0x40>; 634 reg-shift = <2>; 635 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&bpmp TEGRA186_CLK_UARTD>; 637 clock-names = "serial"; 638 resets = <&bpmp TEGRA186_RESET_UARTD>; 639 reset-names = "serial"; 640 status = "disabled"; 641 }; 642 643 uarte: serial@3140000 { 644 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 645 reg = <0x0 0x03140000 0x0 0x40>; 646 reg-shift = <2>; 647 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&bpmp TEGRA186_CLK_UARTE>; 649 clock-names = "serial"; 650 resets = <&bpmp TEGRA186_RESET_UARTE>; 651 reset-names = "serial"; 652 status = "disabled"; 653 }; 654 655 uartf: serial@3150000 { 656 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 657 reg = <0x0 0x03150000 0x0 0x40>; 658 reg-shift = <2>; 659 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&bpmp TEGRA186_CLK_UARTF>; 661 clock-names = "serial"; 662 resets = <&bpmp TEGRA186_RESET_UARTF>; 663 reset-names = "serial"; 664 status = "disabled"; 665 }; 666 667 gen1_i2c: i2c@3160000 { 668 compatible = "nvidia,tegra186-i2c"; 669 reg = <0x0 0x03160000 0x0 0x10000>; 670 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 clocks = <&bpmp TEGRA186_CLK_I2C1>; 674 clock-names = "div-clk"; 675 resets = <&bpmp TEGRA186_RESET_I2C1>; 676 reset-names = "i2c"; 677 dmas = <&gpcdma 21>, <&gpcdma 21>; 678 dma-names = "rx", "tx"; 679 status = "disabled"; 680 }; 681 682 cam_i2c: i2c@3180000 { 683 compatible = "nvidia,tegra186-i2c"; 684 reg = <0x0 0x03180000 0x0 0x10000>; 685 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 clocks = <&bpmp TEGRA186_CLK_I2C3>; 689 clock-names = "div-clk"; 690 resets = <&bpmp TEGRA186_RESET_I2C3>; 691 reset-names = "i2c"; 692 dmas = <&gpcdma 23>, <&gpcdma 23>; 693 dma-names = "rx", "tx"; 694 status = "disabled"; 695 }; 696 697 /* shares pads with dpaux1 */ 698 dp_aux_ch1_i2c: i2c@3190000 { 699 compatible = "nvidia,tegra186-i2c"; 700 reg = <0x0 0x03190000 0x0 0x10000>; 701 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 clocks = <&bpmp TEGRA186_CLK_I2C4>; 705 clock-names = "div-clk"; 706 resets = <&bpmp TEGRA186_RESET_I2C4>; 707 reset-names = "i2c"; 708 pinctrl-names = "default", "idle"; 709 pinctrl-0 = <&state_dpaux1_i2c>; 710 pinctrl-1 = <&state_dpaux1_off>; 711 dmas = <&gpcdma 26>, <&gpcdma 26>; 712 dma-names = "rx", "tx"; 713 status = "disabled"; 714 }; 715 716 /* controlled by BPMP, should not be enabled */ 717 pwr_i2c: i2c@31a0000 { 718 compatible = "nvidia,tegra186-i2c"; 719 reg = <0x0 0x031a0000 0x0 0x10000>; 720 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 clocks = <&bpmp TEGRA186_CLK_I2C5>; 724 clock-names = "div-clk"; 725 resets = <&bpmp TEGRA186_RESET_I2C5>; 726 reset-names = "i2c"; 727 status = "disabled"; 728 }; 729 730 /* shares pads with dpaux0 */ 731 dp_aux_ch0_i2c: i2c@31b0000 { 732 compatible = "nvidia,tegra186-i2c"; 733 reg = <0x0 0x031b0000 0x0 0x10000>; 734 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 clocks = <&bpmp TEGRA186_CLK_I2C6>; 738 clock-names = "div-clk"; 739 resets = <&bpmp TEGRA186_RESET_I2C6>; 740 reset-names = "i2c"; 741 pinctrl-names = "default", "idle"; 742 pinctrl-0 = <&state_dpaux_i2c>; 743 pinctrl-1 = <&state_dpaux_off>; 744 dmas = <&gpcdma 30>, <&gpcdma 30>; 745 dma-names = "rx", "tx"; 746 status = "disabled"; 747 }; 748 749 gen7_i2c: i2c@31c0000 { 750 compatible = "nvidia,tegra186-i2c"; 751 reg = <0x0 0x031c0000 0x0 0x10000>; 752 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 clocks = <&bpmp TEGRA186_CLK_I2C7>; 756 clock-names = "div-clk"; 757 resets = <&bpmp TEGRA186_RESET_I2C7>; 758 reset-names = "i2c"; 759 dmas = <&gpcdma 27>, <&gpcdma 27>; 760 dma-names = "rx", "tx"; 761 status = "disabled"; 762 }; 763 764 gen9_i2c: i2c@31e0000 { 765 compatible = "nvidia,tegra186-i2c"; 766 reg = <0x0 0x031e0000 0x0 0x10000>; 767 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 clocks = <&bpmp TEGRA186_CLK_I2C9>; 771 clock-names = "div-clk"; 772 resets = <&bpmp TEGRA186_RESET_I2C9>; 773 reset-names = "i2c"; 774 dmas = <&gpcdma 31>, <&gpcdma 31>; 775 dma-names = "rx", "tx"; 776 status = "disabled"; 777 }; 778 779 pwm1: pwm@3280000 { 780 compatible = "nvidia,tegra186-pwm"; 781 reg = <0x0 0x3280000 0x0 0x10000>; 782 clocks = <&bpmp TEGRA186_CLK_PWM1>; 783 resets = <&bpmp TEGRA186_RESET_PWM1>; 784 reset-names = "pwm"; 785 status = "disabled"; 786 #pwm-cells = <2>; 787 }; 788 789 pwm2: pwm@3290000 { 790 compatible = "nvidia,tegra186-pwm"; 791 reg = <0x0 0x3290000 0x0 0x10000>; 792 clocks = <&bpmp TEGRA186_CLK_PWM2>; 793 resets = <&bpmp TEGRA186_RESET_PWM2>; 794 reset-names = "pwm"; 795 status = "disabled"; 796 #pwm-cells = <2>; 797 }; 798 799 pwm3: pwm@32a0000 { 800 compatible = "nvidia,tegra186-pwm"; 801 reg = <0x0 0x32a0000 0x0 0x10000>; 802 clocks = <&bpmp TEGRA186_CLK_PWM3>; 803 resets = <&bpmp TEGRA186_RESET_PWM3>; 804 reset-names = "pwm"; 805 status = "disabled"; 806 #pwm-cells = <2>; 807 }; 808 809 pwm5: pwm@32c0000 { 810 compatible = "nvidia,tegra186-pwm"; 811 reg = <0x0 0x32c0000 0x0 0x10000>; 812 clocks = <&bpmp TEGRA186_CLK_PWM5>; 813 resets = <&bpmp TEGRA186_RESET_PWM5>; 814 reset-names = "pwm"; 815 status = "disabled"; 816 #pwm-cells = <2>; 817 }; 818 819 pwm6: pwm@32d0000 { 820 compatible = "nvidia,tegra186-pwm"; 821 reg = <0x0 0x32d0000 0x0 0x10000>; 822 clocks = <&bpmp TEGRA186_CLK_PWM6>; 823 resets = <&bpmp TEGRA186_RESET_PWM6>; 824 reset-names = "pwm"; 825 status = "disabled"; 826 #pwm-cells = <2>; 827 }; 828 829 pwm7: pwm@32e0000 { 830 compatible = "nvidia,tegra186-pwm"; 831 reg = <0x0 0x32e0000 0x0 0x10000>; 832 clocks = <&bpmp TEGRA186_CLK_PWM7>; 833 resets = <&bpmp TEGRA186_RESET_PWM7>; 834 reset-names = "pwm"; 835 status = "disabled"; 836 #pwm-cells = <2>; 837 }; 838 839 pwm8: pwm@32f0000 { 840 compatible = "nvidia,tegra186-pwm"; 841 reg = <0x0 0x32f0000 0x0 0x10000>; 842 clocks = <&bpmp TEGRA186_CLK_PWM8>; 843 resets = <&bpmp TEGRA186_RESET_PWM8>; 844 reset-names = "pwm"; 845 status = "disabled"; 846 #pwm-cells = <2>; 847 }; 848 849 sdmmc1: mmc@3400000 { 850 compatible = "nvidia,tegra186-sdhci"; 851 reg = <0x0 0x03400000 0x0 0x10000>; 852 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 854 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 855 clock-names = "sdhci", "tmclk"; 856 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 857 reset-names = "sdhci"; 858 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 859 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 860 interconnect-names = "dma-mem", "write"; 861 iommus = <&smmu TEGRA186_SID_SDMMC1>; 862 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 863 pinctrl-0 = <&sdmmc1_3v3>; 864 pinctrl-1 = <&sdmmc1_1v8>; 865 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 866 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 867 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 868 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 869 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 870 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 871 nvidia,default-tap = <0x5>; 872 nvidia,default-trim = <0xb>; 873 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 874 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 875 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 876 status = "disabled"; 877 }; 878 879 sdmmc2: mmc@3420000 { 880 compatible = "nvidia,tegra186-sdhci"; 881 reg = <0x0 0x03420000 0x0 0x10000>; 882 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 884 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 885 clock-names = "sdhci", "tmclk"; 886 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 887 reset-names = "sdhci"; 888 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 889 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 890 interconnect-names = "dma-mem", "write"; 891 iommus = <&smmu TEGRA186_SID_SDMMC2>; 892 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 893 pinctrl-0 = <&sdmmc2_3v3>; 894 pinctrl-1 = <&sdmmc2_1v8>; 895 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 896 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 897 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 898 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 899 nvidia,default-tap = <0x5>; 900 nvidia,default-trim = <0xb>; 901 status = "disabled"; 902 }; 903 904 sdmmc3: mmc@3440000 { 905 compatible = "nvidia,tegra186-sdhci"; 906 reg = <0x0 0x03440000 0x0 0x10000>; 907 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 909 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 910 clock-names = "sdhci", "tmclk"; 911 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 912 reset-names = "sdhci"; 913 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 914 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 915 interconnect-names = "dma-mem", "write"; 916 iommus = <&smmu TEGRA186_SID_SDMMC3>; 917 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 918 pinctrl-0 = <&sdmmc3_3v3>; 919 pinctrl-1 = <&sdmmc3_1v8>; 920 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 921 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 922 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 923 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 924 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 925 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 926 nvidia,default-tap = <0x5>; 927 nvidia,default-trim = <0xb>; 928 status = "disabled"; 929 }; 930 931 sdmmc4: mmc@3460000 { 932 compatible = "nvidia,tegra186-sdhci"; 933 reg = <0x0 0x03460000 0x0 0x10000>; 934 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 936 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 937 clock-names = "sdhci", "tmclk"; 938 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 939 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 940 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 941 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 942 reset-names = "sdhci"; 943 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 944 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 945 interconnect-names = "dma-mem", "write"; 946 iommus = <&smmu TEGRA186_SID_SDMMC4>; 947 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 948 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 949 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 950 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 951 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 952 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 953 nvidia,default-tap = <0x9>; 954 nvidia,default-trim = <0x5>; 955 nvidia,dqs-trim = <63>; 956 mmc-hs400-1_8v; 957 supports-cqe; 958 status = "disabled"; 959 }; 960 961 sata@3507000 { 962 compatible = "nvidia,tegra186-ahci"; 963 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 964 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 965 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 966 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 967 968 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 969 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 970 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 971 interconnect-names = "dma-mem", "write"; 972 iommus = <&smmu TEGRA186_SID_SATA>; 973 974 clocks = <&bpmp TEGRA186_CLK_SATA>, 975 <&bpmp TEGRA186_CLK_SATA_OOB>; 976 clock-names = "sata", "sata-oob"; 977 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 978 <&bpmp TEGRA186_CLK_SATA_OOB>; 979 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 980 <&bpmp TEGRA186_CLK_PLLP>; 981 assigned-clock-rates = <102000000>, 982 <204000000>; 983 resets = <&bpmp TEGRA186_RESET_SATA>, 984 <&bpmp TEGRA186_RESET_SATACOLD>; 985 reset-names = "sata", "sata-cold"; 986 status = "disabled"; 987 }; 988 989 hda@3510000 { 990 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 991 reg = <0x0 0x03510000 0x0 0x10000>; 992 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&bpmp TEGRA186_CLK_HDA>, 994 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 995 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 996 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 997 resets = <&bpmp TEGRA186_RESET_HDA>, 998 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 999 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 1000 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1001 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1002 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 1003 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 1004 interconnect-names = "dma-mem", "write"; 1005 iommus = <&smmu TEGRA186_SID_HDA>; 1006 status = "disabled"; 1007 }; 1008 1009 padctl: padctl@3520000 { 1010 compatible = "nvidia,tegra186-xusb-padctl"; 1011 reg = <0x0 0x03520000 0x0 0x1000>, 1012 <0x0 0x03540000 0x0 0x1000>; 1013 reg-names = "padctl", "ao"; 1014 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1015 1016 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 1017 reset-names = "padctl"; 1018 1019 status = "disabled"; 1020 1021 pads { 1022 usb2 { 1023 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 1024 clock-names = "trk"; 1025 status = "disabled"; 1026 1027 lanes { 1028 usb2-0 { 1029 status = "disabled"; 1030 #phy-cells = <0>; 1031 }; 1032 1033 usb2-1 { 1034 status = "disabled"; 1035 #phy-cells = <0>; 1036 }; 1037 1038 usb2-2 { 1039 status = "disabled"; 1040 #phy-cells = <0>; 1041 }; 1042 }; 1043 }; 1044 1045 hsic { 1046 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 1047 clock-names = "trk"; 1048 status = "disabled"; 1049 1050 lanes { 1051 hsic-0 { 1052 status = "disabled"; 1053 #phy-cells = <0>; 1054 }; 1055 }; 1056 }; 1057 1058 usb3 { 1059 status = "disabled"; 1060 1061 lanes { 1062 usb3-0 { 1063 status = "disabled"; 1064 #phy-cells = <0>; 1065 }; 1066 1067 usb3-1 { 1068 status = "disabled"; 1069 #phy-cells = <0>; 1070 }; 1071 1072 usb3-2 { 1073 status = "disabled"; 1074 #phy-cells = <0>; 1075 }; 1076 }; 1077 }; 1078 }; 1079 1080 ports { 1081 usb2-0 { 1082 status = "disabled"; 1083 }; 1084 1085 usb2-1 { 1086 status = "disabled"; 1087 }; 1088 1089 usb2-2 { 1090 status = "disabled"; 1091 }; 1092 1093 hsic-0 { 1094 status = "disabled"; 1095 }; 1096 1097 usb3-0 { 1098 status = "disabled"; 1099 }; 1100 1101 usb3-1 { 1102 status = "disabled"; 1103 }; 1104 1105 usb3-2 { 1106 status = "disabled"; 1107 }; 1108 }; 1109 }; 1110 1111 usb@3530000 { 1112 compatible = "nvidia,tegra186-xusb"; 1113 reg = <0x0 0x03530000 0x0 0x8000>, 1114 <0x0 0x03538000 0x0 0x1000>; 1115 reg-names = "hcd", "fpci"; 1116 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 1119 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 1120 <&bpmp TEGRA186_CLK_XUSB_SS>, 1121 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1122 <&bpmp TEGRA186_CLK_CLK_M>, 1123 <&bpmp TEGRA186_CLK_XUSB_FS>, 1124 <&bpmp TEGRA186_CLK_PLLU>, 1125 <&bpmp TEGRA186_CLK_CLK_M>, 1126 <&bpmp TEGRA186_CLK_PLLE>; 1127 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 1128 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 1129 "pll_u_480m", "clk_m", "pll_e"; 1130 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 1131 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1132 power-domain-names = "xusb_host", "xusb_ss"; 1133 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1134 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1135 interconnect-names = "dma-mem", "write"; 1136 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 1141 nvidia,xusb-padctl = <&padctl>; 1142 }; 1143 1144 usb@3550000 { 1145 compatible = "nvidia,tegra186-xudc"; 1146 reg = <0x0 0x03550000 0x0 0x8000>, 1147 <0x0 0x03558000 0x0 0x1000>; 1148 reg-names = "base", "fpci"; 1149 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1151 <&bpmp TEGRA186_CLK_XUSB_SS>, 1152 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1153 <&bpmp TEGRA186_CLK_XUSB_FS>; 1154 clock-names = "dev", "ss", "ss_src", "fs_src"; 1155 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1156 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1157 interconnect-names = "dma-mem", "write"; 1158 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1159 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1160 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1161 power-domain-names = "dev", "ss"; 1162 nvidia,xusb-padctl = <&padctl>; 1163 status = "disabled"; 1164 }; 1165 1166 fuse@3820000 { 1167 compatible = "nvidia,tegra186-efuse"; 1168 reg = <0x0 0x03820000 0x0 0x10000>; 1169 clocks = <&bpmp TEGRA186_CLK_FUSE>; 1170 clock-names = "fuse"; 1171 }; 1172 1173 gic: interrupt-controller@3881000 { 1174 compatible = "arm,gic-400"; 1175 #interrupt-cells = <3>; 1176 interrupt-controller; 1177 reg = <0x0 0x03881000 0x0 0x1000>, 1178 <0x0 0x03882000 0x0 0x2000>, 1179 <0x0 0x03884000 0x0 0x2000>, 1180 <0x0 0x03886000 0x0 0x2000>; 1181 interrupts = <GIC_PPI 9 1182 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1183 interrupt-parent = <&gic>; 1184 }; 1185 1186 cec@3960000 { 1187 compatible = "nvidia,tegra186-cec"; 1188 reg = <0x0 0x03960000 0x0 0x10000>; 1189 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&bpmp TEGRA186_CLK_CEC>; 1191 clock-names = "cec"; 1192 status = "disabled"; 1193 }; 1194 1195 hsp_top0: hsp@3c00000 { 1196 compatible = "nvidia,tegra186-hsp"; 1197 reg = <0x0 0x03c00000 0x0 0xa0000>; 1198 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1199 interrupt-names = "doorbell"; 1200 #mbox-cells = <2>; 1201 status = "disabled"; 1202 }; 1203 1204 gen2_i2c: i2c@c240000 { 1205 compatible = "nvidia,tegra186-i2c"; 1206 reg = <0x0 0x0c240000 0x0 0x10000>; 1207 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 clocks = <&bpmp TEGRA186_CLK_I2C2>; 1211 clock-names = "div-clk"; 1212 resets = <&bpmp TEGRA186_RESET_I2C2>; 1213 reset-names = "i2c"; 1214 dmas = <&gpcdma 22>, <&gpcdma 22>; 1215 dma-names = "rx", "tx"; 1216 status = "disabled"; 1217 }; 1218 1219 gen8_i2c: i2c@c250000 { 1220 compatible = "nvidia,tegra186-i2c"; 1221 reg = <0x0 0x0c250000 0x0 0x10000>; 1222 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 clocks = <&bpmp TEGRA186_CLK_I2C8>; 1226 clock-names = "div-clk"; 1227 resets = <&bpmp TEGRA186_RESET_I2C8>; 1228 reset-names = "i2c"; 1229 dmas = <&gpcdma 0>, <&gpcdma 0>; 1230 dma-names = "rx", "tx"; 1231 status = "disabled"; 1232 }; 1233 1234 uartc: serial@c280000 { 1235 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1236 reg = <0x0 0x0c280000 0x0 0x40>; 1237 reg-shift = <2>; 1238 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&bpmp TEGRA186_CLK_UARTC>; 1240 clock-names = "serial"; 1241 resets = <&bpmp TEGRA186_RESET_UARTC>; 1242 reset-names = "serial"; 1243 status = "disabled"; 1244 }; 1245 1246 uartg: serial@c290000 { 1247 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1248 reg = <0x0 0x0c290000 0x0 0x40>; 1249 reg-shift = <2>; 1250 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1251 clocks = <&bpmp TEGRA186_CLK_UARTG>; 1252 clock-names = "serial"; 1253 resets = <&bpmp TEGRA186_RESET_UARTG>; 1254 reset-names = "serial"; 1255 status = "disabled"; 1256 }; 1257 1258 rtc: rtc@c2a0000 { 1259 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1260 reg = <0 0x0c2a0000 0 0x10000>; 1261 interrupt-parent = <&pmc>; 1262 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1263 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1264 clock-names = "rtc"; 1265 status = "disabled"; 1266 }; 1267 1268 gpio_aon: gpio@c2f0000 { 1269 compatible = "nvidia,tegra186-gpio-aon"; 1270 reg-names = "security", "gpio"; 1271 reg = <0x0 0xc2f0000 0x0 0x1000>, 1272 <0x0 0xc2f1000 0x0 0x1000>; 1273 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1274 gpio-controller; 1275 #gpio-cells = <2>; 1276 interrupt-controller; 1277 #interrupt-cells = <2>; 1278 }; 1279 1280 pwm4: pwm@c340000 { 1281 compatible = "nvidia,tegra186-pwm"; 1282 reg = <0x0 0xc340000 0x0 0x10000>; 1283 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1284 resets = <&bpmp TEGRA186_RESET_PWM4>; 1285 reset-names = "pwm"; 1286 status = "disabled"; 1287 #pwm-cells = <2>; 1288 }; 1289 1290 pmc: pmc@c360000 { 1291 compatible = "nvidia,tegra186-pmc"; 1292 reg = <0 0x0c360000 0 0x10000>, 1293 <0 0x0c370000 0 0x10000>, 1294 <0 0x0c380000 0 0x10000>, 1295 <0 0x0c390000 0 0x10000>; 1296 reg-names = "pmc", "wake", "aotag", "scratch"; 1297 1298 #interrupt-cells = <2>; 1299 interrupt-controller; 1300 1301 sdmmc1_1v8: sdmmc1-1v8 { 1302 pins = "sdmmc1-hv"; 1303 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1304 }; 1305 1306 sdmmc1_3v3: sdmmc1-3v3 { 1307 pins = "sdmmc1-hv"; 1308 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1309 }; 1310 1311 sdmmc2_1v8: sdmmc2-1v8 { 1312 pins = "sdmmc2-hv"; 1313 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1314 }; 1315 1316 sdmmc2_3v3: sdmmc2-3v3 { 1317 pins = "sdmmc2-hv"; 1318 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1319 }; 1320 1321 sdmmc3_1v8: sdmmc3-1v8 { 1322 pins = "sdmmc3-hv"; 1323 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1324 }; 1325 1326 sdmmc3_3v3: sdmmc3-3v3 { 1327 pins = "sdmmc3-hv"; 1328 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1329 }; 1330 }; 1331 1332 ccplex@e000000 { 1333 compatible = "nvidia,tegra186-ccplex-cluster"; 1334 reg = <0x0 0x0e000000 0x0 0x400000>; 1335 1336 nvidia,bpmp = <&bpmp>; 1337 }; 1338 1339 pcie@10003000 { 1340 compatible = "nvidia,tegra186-pcie"; 1341 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1342 device_type = "pci"; 1343 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1344 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1345 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1346 reg-names = "pads", "afi", "cs"; 1347 1348 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1349 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1350 interrupt-names = "intr", "msi"; 1351 1352 #interrupt-cells = <1>; 1353 interrupt-map-mask = <0 0 0 0>; 1354 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1355 1356 bus-range = <0x00 0xff>; 1357 #address-cells = <3>; 1358 #size-cells = <2>; 1359 1360 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1361 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1362 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1363 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1364 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1365 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1366 1367 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1368 <&bpmp TEGRA186_CLK_AFI>, 1369 <&bpmp TEGRA186_CLK_PLLE>; 1370 clock-names = "pex", "afi", "pll_e"; 1371 1372 resets = <&bpmp TEGRA186_RESET_PCIE>, 1373 <&bpmp TEGRA186_RESET_AFI>, 1374 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1375 reset-names = "pex", "afi", "pcie_x"; 1376 1377 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1378 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1379 interconnect-names = "dma-mem", "write"; 1380 1381 iommus = <&smmu TEGRA186_SID_AFI>; 1382 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1383 iommu-map-mask = <0x0>; 1384 1385 status = "disabled"; 1386 1387 pci@1,0 { 1388 device_type = "pci"; 1389 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1390 reg = <0x000800 0 0 0 0>; 1391 status = "disabled"; 1392 1393 #address-cells = <3>; 1394 #size-cells = <2>; 1395 ranges; 1396 1397 nvidia,num-lanes = <2>; 1398 }; 1399 1400 pci@2,0 { 1401 device_type = "pci"; 1402 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1403 reg = <0x001000 0 0 0 0>; 1404 status = "disabled"; 1405 1406 #address-cells = <3>; 1407 #size-cells = <2>; 1408 ranges; 1409 1410 nvidia,num-lanes = <1>; 1411 }; 1412 1413 pci@3,0 { 1414 device_type = "pci"; 1415 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1416 reg = <0x001800 0 0 0 0>; 1417 status = "disabled"; 1418 1419 #address-cells = <3>; 1420 #size-cells = <2>; 1421 ranges; 1422 1423 nvidia,num-lanes = <1>; 1424 }; 1425 }; 1426 1427 smmu: iommu@12000000 { 1428 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1429 reg = <0 0x12000000 0 0x800000>; 1430 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1495 stream-match-mask = <0x7f80>; 1496 #global-interrupts = <1>; 1497 #iommu-cells = <1>; 1498 1499 nvidia,memory-controller = <&mc>; 1500 }; 1501 1502 host1x@13e00000 { 1503 compatible = "nvidia,tegra186-host1x"; 1504 reg = <0x0 0x13e00000 0x0 0x10000>, 1505 <0x0 0x13e10000 0x0 0x10000>; 1506 reg-names = "hypervisor", "vm"; 1507 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1509 interrupt-names = "syncpt", "host1x"; 1510 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1511 clock-names = "host1x"; 1512 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1513 reset-names = "host1x"; 1514 1515 #address-cells = <1>; 1516 #size-cells = <1>; 1517 1518 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1519 1520 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1521 interconnect-names = "dma-mem"; 1522 1523 iommus = <&smmu TEGRA186_SID_HOST1X>; 1524 1525 /* Context isolation domains */ 1526 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1527 <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1528 <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1529 <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1530 <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1531 <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1532 <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1533 <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1534 1535 dpaux1: dpaux@15040000 { 1536 compatible = "nvidia,tegra186-dpaux"; 1537 reg = <0x15040000 0x10000>; 1538 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1539 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1540 <&bpmp TEGRA186_CLK_PLLDP>; 1541 clock-names = "dpaux", "parent"; 1542 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1543 reset-names = "dpaux"; 1544 status = "disabled"; 1545 1546 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1547 1548 state_dpaux1_aux: pinmux-aux { 1549 groups = "dpaux-io"; 1550 function = "aux"; 1551 }; 1552 1553 state_dpaux1_i2c: pinmux-i2c { 1554 groups = "dpaux-io"; 1555 function = "i2c"; 1556 }; 1557 1558 state_dpaux1_off: pinmux-off { 1559 groups = "dpaux-io"; 1560 function = "off"; 1561 }; 1562 1563 i2c-bus { 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 }; 1567 }; 1568 1569 display-hub@15200000 { 1570 compatible = "nvidia,tegra186-display"; 1571 reg = <0x15200000 0x00040000>; 1572 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1573 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1574 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1575 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1576 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1577 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1578 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1579 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1580 "wgrp3", "wgrp4", "wgrp5"; 1581 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1582 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1583 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1584 clock-names = "disp", "dsc", "hub"; 1585 status = "disabled"; 1586 1587 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1588 1589 #address-cells = <1>; 1590 #size-cells = <1>; 1591 1592 ranges = <0x15200000 0x15200000 0x40000>; 1593 1594 display@15200000 { 1595 compatible = "nvidia,tegra186-dc"; 1596 reg = <0x15200000 0x10000>; 1597 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1598 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1599 clock-names = "dc"; 1600 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1601 reset-names = "dc"; 1602 1603 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1604 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1605 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1606 interconnect-names = "dma-mem", "read-1"; 1607 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1608 1609 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1610 nvidia,head = <0>; 1611 }; 1612 1613 display@15210000 { 1614 compatible = "nvidia,tegra186-dc"; 1615 reg = <0x15210000 0x10000>; 1616 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1617 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1618 clock-names = "dc"; 1619 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1620 reset-names = "dc"; 1621 1622 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1623 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1624 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1625 interconnect-names = "dma-mem", "read-1"; 1626 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1627 1628 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1629 nvidia,head = <1>; 1630 }; 1631 1632 display@15220000 { 1633 compatible = "nvidia,tegra186-dc"; 1634 reg = <0x15220000 0x10000>; 1635 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1636 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1637 clock-names = "dc"; 1638 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1639 reset-names = "dc"; 1640 1641 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1642 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1643 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1644 interconnect-names = "dma-mem", "read-1"; 1645 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1646 1647 nvidia,outputs = <&sor0 &sor1>; 1648 nvidia,head = <2>; 1649 }; 1650 }; 1651 1652 dsia: dsi@15300000 { 1653 compatible = "nvidia,tegra186-dsi"; 1654 reg = <0x15300000 0x10000>; 1655 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1656 clocks = <&bpmp TEGRA186_CLK_DSI>, 1657 <&bpmp TEGRA186_CLK_DSIA_LP>, 1658 <&bpmp TEGRA186_CLK_PLLD>; 1659 clock-names = "dsi", "lp", "parent"; 1660 resets = <&bpmp TEGRA186_RESET_DSI>; 1661 reset-names = "dsi"; 1662 status = "disabled"; 1663 1664 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1665 }; 1666 1667 vic@15340000 { 1668 compatible = "nvidia,tegra186-vic"; 1669 reg = <0x15340000 0x40000>; 1670 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1671 clocks = <&bpmp TEGRA186_CLK_VIC>; 1672 clock-names = "vic"; 1673 resets = <&bpmp TEGRA186_RESET_VIC>; 1674 reset-names = "vic"; 1675 1676 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1677 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1678 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1679 interconnect-names = "dma-mem", "write"; 1680 iommus = <&smmu TEGRA186_SID_VIC>; 1681 }; 1682 1683 nvjpg@15380000 { 1684 compatible = "nvidia,tegra186-nvjpg"; 1685 reg = <0x15380000 0x40000>; 1686 clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1687 clock-names = "nvjpg"; 1688 resets = <&bpmp TEGRA186_RESET_NVJPG>; 1689 reset-names = "nvjpg"; 1690 1691 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1692 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1693 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1694 interconnect-names = "dma-mem", "write"; 1695 iommus = <&smmu TEGRA186_SID_NVJPG>; 1696 }; 1697 1698 dsib: dsi@15400000 { 1699 compatible = "nvidia,tegra186-dsi"; 1700 reg = <0x15400000 0x10000>; 1701 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1702 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1703 <&bpmp TEGRA186_CLK_DSIB_LP>, 1704 <&bpmp TEGRA186_CLK_PLLD>; 1705 clock-names = "dsi", "lp", "parent"; 1706 resets = <&bpmp TEGRA186_RESET_DSIB>; 1707 reset-names = "dsi"; 1708 status = "disabled"; 1709 1710 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1711 }; 1712 1713 nvdec@15480000 { 1714 compatible = "nvidia,tegra186-nvdec"; 1715 reg = <0x15480000 0x40000>; 1716 clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1717 clock-names = "nvdec"; 1718 resets = <&bpmp TEGRA186_RESET_NVDEC>; 1719 reset-names = "nvdec"; 1720 1721 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1722 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1723 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1724 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1725 interconnect-names = "dma-mem", "read-1", "write"; 1726 iommus = <&smmu TEGRA186_SID_NVDEC>; 1727 }; 1728 1729 nvenc@154c0000 { 1730 compatible = "nvidia,tegra186-nvenc"; 1731 reg = <0x154c0000 0x40000>; 1732 clocks = <&bpmp TEGRA186_CLK_NVENC>; 1733 clock-names = "nvenc"; 1734 resets = <&bpmp TEGRA186_RESET_NVENC>; 1735 reset-names = "nvenc"; 1736 1737 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1738 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1739 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1740 interconnect-names = "dma-mem", "write"; 1741 iommus = <&smmu TEGRA186_SID_NVENC>; 1742 }; 1743 1744 sor0: sor@15540000 { 1745 compatible = "nvidia,tegra186-sor"; 1746 reg = <0x15540000 0x10000>; 1747 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1748 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1749 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1750 <&bpmp TEGRA186_CLK_PLLD2>, 1751 <&bpmp TEGRA186_CLK_PLLDP>, 1752 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1753 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1754 clock-names = "sor", "out", "parent", "dp", "safe", 1755 "pad"; 1756 resets = <&bpmp TEGRA186_RESET_SOR0>; 1757 reset-names = "sor"; 1758 pinctrl-0 = <&state_dpaux_aux>; 1759 pinctrl-1 = <&state_dpaux_i2c>; 1760 pinctrl-2 = <&state_dpaux_off>; 1761 pinctrl-names = "aux", "i2c", "off"; 1762 status = "disabled"; 1763 1764 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1765 nvidia,interface = <0>; 1766 }; 1767 1768 sor1: sor@15580000 { 1769 compatible = "nvidia,tegra186-sor"; 1770 reg = <0x15580000 0x10000>; 1771 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1772 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1773 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1774 <&bpmp TEGRA186_CLK_PLLD3>, 1775 <&bpmp TEGRA186_CLK_PLLDP>, 1776 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1777 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1778 clock-names = "sor", "out", "parent", "dp", "safe", 1779 "pad"; 1780 resets = <&bpmp TEGRA186_RESET_SOR1>; 1781 reset-names = "sor"; 1782 pinctrl-0 = <&state_dpaux1_aux>; 1783 pinctrl-1 = <&state_dpaux1_i2c>; 1784 pinctrl-2 = <&state_dpaux1_off>; 1785 pinctrl-names = "aux", "i2c", "off"; 1786 status = "disabled"; 1787 1788 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1789 nvidia,interface = <1>; 1790 }; 1791 1792 dpaux: dpaux@155c0000 { 1793 compatible = "nvidia,tegra186-dpaux"; 1794 reg = <0x155c0000 0x10000>; 1795 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1796 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1797 <&bpmp TEGRA186_CLK_PLLDP>; 1798 clock-names = "dpaux", "parent"; 1799 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1800 reset-names = "dpaux"; 1801 status = "disabled"; 1802 1803 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1804 1805 state_dpaux_aux: pinmux-aux { 1806 groups = "dpaux-io"; 1807 function = "aux"; 1808 }; 1809 1810 state_dpaux_i2c: pinmux-i2c { 1811 groups = "dpaux-io"; 1812 function = "i2c"; 1813 }; 1814 1815 state_dpaux_off: pinmux-off { 1816 groups = "dpaux-io"; 1817 function = "off"; 1818 }; 1819 1820 i2c-bus { 1821 #address-cells = <1>; 1822 #size-cells = <0>; 1823 }; 1824 }; 1825 1826 padctl@15880000 { 1827 compatible = "nvidia,tegra186-dsi-padctl"; 1828 reg = <0x15880000 0x10000>; 1829 resets = <&bpmp TEGRA186_RESET_DSI>; 1830 reset-names = "dsi"; 1831 status = "disabled"; 1832 }; 1833 1834 dsic: dsi@15900000 { 1835 compatible = "nvidia,tegra186-dsi"; 1836 reg = <0x15900000 0x10000>; 1837 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1838 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1839 <&bpmp TEGRA186_CLK_DSIC_LP>, 1840 <&bpmp TEGRA186_CLK_PLLD>; 1841 clock-names = "dsi", "lp", "parent"; 1842 resets = <&bpmp TEGRA186_RESET_DSIC>; 1843 reset-names = "dsi"; 1844 status = "disabled"; 1845 1846 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1847 }; 1848 1849 dsid: dsi@15940000 { 1850 compatible = "nvidia,tegra186-dsi"; 1851 reg = <0x15940000 0x10000>; 1852 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1853 clocks = <&bpmp TEGRA186_CLK_DSID>, 1854 <&bpmp TEGRA186_CLK_DSID_LP>, 1855 <&bpmp TEGRA186_CLK_PLLD>; 1856 clock-names = "dsi", "lp", "parent"; 1857 resets = <&bpmp TEGRA186_RESET_DSID>; 1858 reset-names = "dsi"; 1859 status = "disabled"; 1860 1861 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1862 }; 1863 }; 1864 1865 gpu@17000000 { 1866 compatible = "nvidia,gp10b"; 1867 reg = <0x0 0x17000000 0x0 0x1000000>, 1868 <0x0 0x18000000 0x0 0x1000000>; 1869 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1871 interrupt-names = "stall", "nonstall"; 1872 1873 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1874 <&bpmp TEGRA186_CLK_GPU>; 1875 clock-names = "gpu", "pwr"; 1876 resets = <&bpmp TEGRA186_RESET_GPU>; 1877 reset-names = "gpu"; 1878 status = "disabled"; 1879 1880 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1881 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1882 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1883 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1884 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1885 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1886 }; 1887 1888 sram@30000000 { 1889 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1890 reg = <0x0 0x30000000 0x0 0x50000>; 1891 #address-cells = <1>; 1892 #size-cells = <1>; 1893 ranges = <0x0 0x0 0x30000000 0x50000>; 1894 no-memory-wc; 1895 1896 cpu_bpmp_tx: sram@4e000 { 1897 reg = <0x4e000 0x1000>; 1898 label = "cpu-bpmp-tx"; 1899 pool; 1900 }; 1901 1902 cpu_bpmp_rx: sram@4f000 { 1903 reg = <0x4f000 0x1000>; 1904 label = "cpu-bpmp-rx"; 1905 pool; 1906 }; 1907 }; 1908 1909 bpmp: bpmp { 1910 compatible = "nvidia,tegra186-bpmp"; 1911 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1912 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1913 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1914 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1915 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1916 iommus = <&smmu TEGRA186_SID_BPMP>; 1917 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1918 TEGRA_HSP_DB_MASTER_BPMP>; 1919 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1920 #clock-cells = <1>; 1921 #reset-cells = <1>; 1922 #power-domain-cells = <1>; 1923 1924 bpmp_i2c: i2c { 1925 compatible = "nvidia,tegra186-bpmp-i2c"; 1926 nvidia,bpmp-bus-id = <5>; 1927 #address-cells = <1>; 1928 #size-cells = <0>; 1929 status = "disabled"; 1930 }; 1931 1932 bpmp_thermal: thermal { 1933 compatible = "nvidia,tegra186-bpmp-thermal"; 1934 #thermal-sensor-cells = <1>; 1935 }; 1936 }; 1937 1938 cpus { 1939 #address-cells = <1>; 1940 #size-cells = <0>; 1941 1942 denver_0: cpu@0 { 1943 compatible = "nvidia,tegra186-denver"; 1944 device_type = "cpu"; 1945 i-cache-size = <0x20000>; 1946 i-cache-line-size = <64>; 1947 i-cache-sets = <512>; 1948 d-cache-size = <0x10000>; 1949 d-cache-line-size = <64>; 1950 d-cache-sets = <256>; 1951 next-level-cache = <&L2_DENVER>; 1952 reg = <0x000>; 1953 }; 1954 1955 denver_1: cpu@1 { 1956 compatible = "nvidia,tegra186-denver"; 1957 device_type = "cpu"; 1958 i-cache-size = <0x20000>; 1959 i-cache-line-size = <64>; 1960 i-cache-sets = <512>; 1961 d-cache-size = <0x10000>; 1962 d-cache-line-size = <64>; 1963 d-cache-sets = <256>; 1964 next-level-cache = <&L2_DENVER>; 1965 reg = <0x001>; 1966 }; 1967 1968 ca57_0: cpu@2 { 1969 compatible = "arm,cortex-a57"; 1970 device_type = "cpu"; 1971 i-cache-size = <0xC000>; 1972 i-cache-line-size = <64>; 1973 i-cache-sets = <256>; 1974 d-cache-size = <0x8000>; 1975 d-cache-line-size = <64>; 1976 d-cache-sets = <256>; 1977 next-level-cache = <&L2_A57>; 1978 reg = <0x100>; 1979 }; 1980 1981 ca57_1: cpu@3 { 1982 compatible = "arm,cortex-a57"; 1983 device_type = "cpu"; 1984 i-cache-size = <0xC000>; 1985 i-cache-line-size = <64>; 1986 i-cache-sets = <256>; 1987 d-cache-size = <0x8000>; 1988 d-cache-line-size = <64>; 1989 d-cache-sets = <256>; 1990 next-level-cache = <&L2_A57>; 1991 reg = <0x101>; 1992 }; 1993 1994 ca57_2: cpu@4 { 1995 compatible = "arm,cortex-a57"; 1996 device_type = "cpu"; 1997 i-cache-size = <0xC000>; 1998 i-cache-line-size = <64>; 1999 i-cache-sets = <256>; 2000 d-cache-size = <0x8000>; 2001 d-cache-line-size = <64>; 2002 d-cache-sets = <256>; 2003 next-level-cache = <&L2_A57>; 2004 reg = <0x102>; 2005 }; 2006 2007 ca57_3: cpu@5 { 2008 compatible = "arm,cortex-a57"; 2009 device_type = "cpu"; 2010 i-cache-size = <0xC000>; 2011 i-cache-line-size = <64>; 2012 i-cache-sets = <256>; 2013 d-cache-size = <0x8000>; 2014 d-cache-line-size = <64>; 2015 d-cache-sets = <256>; 2016 next-level-cache = <&L2_A57>; 2017 reg = <0x103>; 2018 }; 2019 2020 L2_DENVER: l2-cache0 { 2021 compatible = "cache"; 2022 cache-unified; 2023 cache-level = <2>; 2024 cache-size = <0x200000>; 2025 cache-line-size = <64>; 2026 cache-sets = <2048>; 2027 }; 2028 2029 L2_A57: l2-cache1 { 2030 compatible = "cache"; 2031 cache-unified; 2032 cache-level = <2>; 2033 cache-size = <0x200000>; 2034 cache-line-size = <64>; 2035 cache-sets = <2048>; 2036 }; 2037 }; 2038 2039 pmu-a57 { 2040 compatible = "arm,cortex-a57-pmu"; 2041 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 2045 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 2046 }; 2047 2048 pmu-denver { 2049 compatible = "nvidia,denver-pmu"; 2050 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2052 interrupt-affinity = <&denver_0 &denver_1>; 2053 }; 2054 2055 sound { 2056 status = "disabled"; 2057 2058 clocks = <&bpmp TEGRA186_CLK_PLLA>, 2059 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2060 clock-names = "pll_a", "plla_out0"; 2061 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2062 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2063 <&bpmp TEGRA186_CLK_AUD_MCLK>; 2064 assigned-clock-parents = <0>, 2065 <&bpmp TEGRA186_CLK_PLLA>, 2066 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2067 /* 2068 * PLLA supports dynamic ramp. Below initial rate is chosen 2069 * for this to work and oscillate between base rates required 2070 * for 8x and 11.025x sample rate streams. 2071 */ 2072 assigned-clock-rates = <258000000>; 2073 2074 iommus = <&smmu TEGRA186_SID_APE>; 2075 }; 2076 2077 thermal-zones { 2078 /* Cortex-A57 cluster */ 2079 cpu-thermal { 2080 polling-delay = <0>; 2081 polling-delay-passive = <1000>; 2082 2083 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 2084 2085 trips { 2086 critical { 2087 temperature = <101000>; 2088 hysteresis = <0>; 2089 type = "critical"; 2090 }; 2091 }; 2092 2093 cooling-maps { 2094 }; 2095 }; 2096 2097 /* Denver cluster */ 2098 aux-thermal { 2099 polling-delay = <0>; 2100 polling-delay-passive = <1000>; 2101 2102 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 2103 2104 trips { 2105 critical { 2106 temperature = <101000>; 2107 hysteresis = <0>; 2108 type = "critical"; 2109 }; 2110 }; 2111 2112 cooling-maps { 2113 }; 2114 }; 2115 2116 gpu-thermal { 2117 polling-delay = <0>; 2118 polling-delay-passive = <1000>; 2119 2120 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 2121 2122 trips { 2123 critical { 2124 temperature = <101000>; 2125 hysteresis = <0>; 2126 type = "critical"; 2127 }; 2128 }; 2129 2130 cooling-maps { 2131 }; 2132 }; 2133 2134 pll-thermal { 2135 polling-delay = <0>; 2136 polling-delay-passive = <1000>; 2137 2138 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 2139 2140 trips { 2141 critical { 2142 temperature = <101000>; 2143 hysteresis = <0>; 2144 type = "critical"; 2145 }; 2146 }; 2147 2148 cooling-maps { 2149 }; 2150 }; 2151 2152 ao-thermal { 2153 polling-delay = <0>; 2154 polling-delay-passive = <1000>; 2155 2156 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 2157 2158 trips { 2159 critical { 2160 temperature = <101000>; 2161 hysteresis = <0>; 2162 type = "critical"; 2163 }; 2164 }; 2165 2166 cooling-maps { 2167 }; 2168 }; 2169 }; 2170 2171 timer { 2172 compatible = "arm,armv8-timer"; 2173 interrupts = <GIC_PPI 13 2174 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2175 <GIC_PPI 14 2176 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2177 <GIC_PPI 11 2178 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2179 <GIC_PPI 10 2180 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2181 interrupt-parent = <&gic>; 2182 always-on; 2183 }; 2184}; 2185