1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra186-clock.h>
3#include <dt-bindings/gpio/tegra186-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/memory/tegra186-mc.h>
7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8#include <dt-bindings/power/tegra186-powergate.h>
9#include <dt-bindings/reset/tegra186-reset.h>
10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
11
12/ {
13	compatible = "nvidia,tegra186";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	misc@100000 {
19		compatible = "nvidia,tegra186-misc";
20		reg = <0x0 0x00100000 0x0 0xf000>,
21		      <0x0 0x0010f000 0x0 0x1000>;
22	};
23
24	gpio: gpio@2200000 {
25		compatible = "nvidia,tegra186-gpio";
26		reg-names = "security", "gpio";
27		reg = <0x0 0x2200000 0x0 0x10000>,
28		      <0x0 0x2210000 0x0 0x10000>;
29		interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
30			     <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
31			     <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
33			     <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
34			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35		#interrupt-cells = <2>;
36		interrupt-controller;
37		#gpio-cells = <2>;
38		gpio-controller;
39	};
40
41	ethernet@2490000 {
42		compatible = "nvidia,tegra186-eqos",
43			     "snps,dwc-qos-ethernet-4.10";
44		reg = <0x0 0x02490000 0x0 0x10000>;
45		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56			 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57			 <&bpmp TEGRA186_CLK_EQOS_RX>,
58			 <&bpmp TEGRA186_CLK_EQOS_TX>,
59			 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61		resets = <&bpmp TEGRA186_RESET_EQOS>;
62		reset-names = "eqos";
63		interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
64				<&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
65		interconnect-names = "dma-mem", "write";
66		iommus = <&smmu TEGRA186_SID_EQOS>;
67		status = "disabled";
68
69		snps,write-requests = <1>;
70		snps,read-requests = <3>;
71		snps,burst-map = <0x7>;
72		snps,txpbl = <32>;
73		snps,rxpbl = <8>;
74	};
75
76	aconnect@2900000 {
77		compatible = "nvidia,tegra186-aconnect",
78			     "nvidia,tegra210-aconnect";
79		clocks = <&bpmp TEGRA186_CLK_APE>,
80			 <&bpmp TEGRA186_CLK_APB2APE>;
81		clock-names = "ape", "apb2ape";
82		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
83		#address-cells = <1>;
84		#size-cells = <1>;
85		ranges = <0x02900000 0x0 0x02900000 0x200000>;
86		status = "disabled";
87
88		adma: dma-controller@2930000 {
89			compatible = "nvidia,tegra186-adma";
90			reg = <0x02930000 0x20000>;
91			interrupt-parent = <&agic>;
92			interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
93				      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
94				      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
95				      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
96				      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
97				      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
98				      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
99				      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
100				      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
101				      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
102				      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
103				      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
104				      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
105				      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
106				      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
107				      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
108				      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
109				      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
110				      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
111				      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
112				      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
113				      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
114				      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
115				      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
116				      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
117				      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
118				      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
119				      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
120				      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
121				      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
122				      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
123				      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
124			#dma-cells = <1>;
125			clocks = <&bpmp TEGRA186_CLK_AHUB>;
126			clock-names = "d_audio";
127			status = "disabled";
128		};
129
130		agic: interrupt-controller@2a40000 {
131			compatible = "nvidia,tegra186-agic",
132				     "nvidia,tegra210-agic";
133			#interrupt-cells = <3>;
134			interrupt-controller;
135			reg = <0x02a41000 0x1000>,
136			      <0x02a42000 0x2000>;
137			interrupts = <GIC_SPI 145
138				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
139			clocks = <&bpmp TEGRA186_CLK_APE>;
140			clock-names = "clk";
141			status = "disabled";
142		};
143
144		tegra_ahub: ahub@2900800 {
145			compatible = "nvidia,tegra186-ahub";
146			reg = <0x02900800 0x800>;
147			clocks = <&bpmp TEGRA186_CLK_AHUB>;
148			clock-names = "ahub";
149			assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
150			assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
151			#address-cells = <1>;
152			#size-cells = <1>;
153			ranges = <0x02900800 0x02900800 0x11800>;
154			status = "disabled";
155
156			tegra_admaif: admaif@290f000 {
157				compatible = "nvidia,tegra186-admaif";
158				reg = <0x0290f000 0x1000>;
159				dmas = <&adma 1>, <&adma 1>,
160				       <&adma 2>, <&adma 2>,
161				       <&adma 3>, <&adma 3>,
162				       <&adma 4>, <&adma 4>,
163				       <&adma 5>, <&adma 5>,
164				       <&adma 6>, <&adma 6>,
165				       <&adma 7>, <&adma 7>,
166				       <&adma 8>, <&adma 8>,
167				       <&adma 9>, <&adma 9>,
168				       <&adma 10>, <&adma 10>,
169				       <&adma 11>, <&adma 11>,
170				       <&adma 12>, <&adma 12>,
171				       <&adma 13>, <&adma 13>,
172				       <&adma 14>, <&adma 14>,
173				       <&adma 15>, <&adma 15>,
174				       <&adma 16>, <&adma 16>,
175				       <&adma 17>, <&adma 17>,
176				       <&adma 18>, <&adma 18>,
177				       <&adma 19>, <&adma 19>,
178				       <&adma 20>, <&adma 20>;
179				dma-names = "rx1", "tx1",
180					    "rx2", "tx2",
181					    "rx3", "tx3",
182					    "rx4", "tx4",
183					    "rx5", "tx5",
184					    "rx6", "tx6",
185					    "rx7", "tx7",
186					    "rx8", "tx8",
187					    "rx9", "tx9",
188					    "rx10", "tx10",
189					    "rx11", "tx11",
190					    "rx12", "tx12",
191					    "rx13", "tx13",
192					    "rx14", "tx14",
193					    "rx15", "tx15",
194					    "rx16", "tx16",
195					    "rx17", "tx17",
196					    "rx18", "tx18",
197					    "rx19", "tx19",
198					    "rx20", "tx20";
199				status = "disabled";
200			};
201
202			tegra_i2s1: i2s@2901000 {
203				compatible = "nvidia,tegra186-i2s",
204					     "nvidia,tegra210-i2s";
205				reg = <0x2901000 0x100>;
206				clocks = <&bpmp TEGRA186_CLK_I2S1>,
207					 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
208				clock-names = "i2s", "sync_input";
209				assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
210				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
211				assigned-clock-rates = <1536000>;
212				sound-name-prefix = "I2S1";
213				status = "disabled";
214			};
215
216			tegra_i2s2: i2s@2901100 {
217				compatible = "nvidia,tegra186-i2s",
218					     "nvidia,tegra210-i2s";
219				reg = <0x2901100 0x100>;
220				clocks = <&bpmp TEGRA186_CLK_I2S2>,
221					 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
222				clock-names = "i2s", "sync_input";
223				assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
224				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
225				assigned-clock-rates = <1536000>;
226				sound-name-prefix = "I2S2";
227				status = "disabled";
228			};
229
230			tegra_i2s3: i2s@2901200 {
231				compatible = "nvidia,tegra186-i2s",
232					     "nvidia,tegra210-i2s";
233				reg = <0x2901200 0x100>;
234				clocks = <&bpmp TEGRA186_CLK_I2S3>,
235					 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
236				clock-names = "i2s", "sync_input";
237				assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
238				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
239				assigned-clock-rates = <1536000>;
240				sound-name-prefix = "I2S3";
241				status = "disabled";
242			};
243
244			tegra_i2s4: i2s@2901300 {
245				compatible = "nvidia,tegra186-i2s",
246					     "nvidia,tegra210-i2s";
247				reg = <0x2901300 0x100>;
248				clocks = <&bpmp TEGRA186_CLK_I2S4>,
249					 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
250				clock-names = "i2s", "sync_input";
251				assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
252				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
253				assigned-clock-rates = <1536000>;
254				sound-name-prefix = "I2S4";
255				status = "disabled";
256			};
257
258			tegra_i2s5: i2s@2901400 {
259				compatible = "nvidia,tegra186-i2s",
260					     "nvidia,tegra210-i2s";
261				reg = <0x2901400 0x100>;
262				clocks = <&bpmp TEGRA186_CLK_I2S5>,
263					 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
264				clock-names = "i2s", "sync_input";
265				assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
266				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
267				assigned-clock-rates = <1536000>;
268				sound-name-prefix = "I2S5";
269				status = "disabled";
270			};
271
272			tegra_i2s6: i2s@2901500 {
273				compatible = "nvidia,tegra186-i2s",
274					     "nvidia,tegra210-i2s";
275				reg = <0x2901500 0x100>;
276				clocks = <&bpmp TEGRA186_CLK_I2S6>,
277					 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
278				clock-names = "i2s", "sync_input";
279				assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
280				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
281				assigned-clock-rates = <1536000>;
282				sound-name-prefix = "I2S6";
283				status = "disabled";
284			};
285
286			tegra_dmic1: dmic@2904000 {
287				compatible = "nvidia,tegra210-dmic";
288				reg = <0x2904000 0x100>;
289				clocks = <&bpmp TEGRA186_CLK_DMIC1>;
290				clock-names = "dmic";
291				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
292				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
293				assigned-clock-rates = <3072000>;
294				sound-name-prefix = "DMIC1";
295				status = "disabled";
296			};
297
298			tegra_dmic2: dmic@2904100 {
299				compatible = "nvidia,tegra210-dmic";
300				reg = <0x2904100 0x100>;
301				clocks = <&bpmp TEGRA186_CLK_DMIC2>;
302				clock-names = "dmic";
303				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
304				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
305				assigned-clock-rates = <3072000>;
306				sound-name-prefix = "DMIC2";
307				status = "disabled";
308			};
309
310			tegra_dmic3: dmic@2904200 {
311				compatible = "nvidia,tegra210-dmic";
312				reg = <0x2904200 0x100>;
313				clocks = <&bpmp TEGRA186_CLK_DMIC3>;
314				clock-names = "dmic";
315				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
316				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
317				assigned-clock-rates = <3072000>;
318				sound-name-prefix = "DMIC3";
319				status = "disabled";
320			};
321
322			tegra_dmic4: dmic@2904300 {
323				compatible = "nvidia,tegra210-dmic";
324				reg = <0x2904300 0x100>;
325				clocks = <&bpmp TEGRA186_CLK_DMIC4>;
326				clock-names = "dmic";
327				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
328				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
329				assigned-clock-rates = <3072000>;
330				sound-name-prefix = "DMIC4";
331				status = "disabled";
332			};
333
334			tegra_dspk1: dspk@2905000 {
335				compatible = "nvidia,tegra186-dspk";
336				reg = <0x2905000 0x100>;
337				clocks = <&bpmp TEGRA186_CLK_DSPK1>;
338				clock-names = "dspk";
339				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
340				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
341				assigned-clock-rates = <12288000>;
342				sound-name-prefix = "DSPK1";
343				status = "disabled";
344			};
345
346			tegra_dspk2: dspk@2905100 {
347				compatible = "nvidia,tegra186-dspk";
348				reg = <0x2905100 0x100>;
349				clocks = <&bpmp TEGRA186_CLK_DSPK2>;
350				clock-names = "dspk";
351				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
352				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
353				assigned-clock-rates = <12288000>;
354				sound-name-prefix = "DSPK2";
355				status = "disabled";
356			};
357
358			tegra_sfc1: sfc@2902000 {
359				compatible = "nvidia,tegra186-sfc",
360					     "nvidia,tegra210-sfc";
361				reg = <0x2902000 0x200>;
362				sound-name-prefix = "SFC1";
363				status = "disabled";
364			};
365
366			tegra_sfc2: sfc@2902200 {
367				compatible = "nvidia,tegra186-sfc",
368					     "nvidia,tegra210-sfc";
369				reg = <0x2902200 0x200>;
370				sound-name-prefix = "SFC2";
371				status = "disabled";
372			};
373
374			tegra_sfc3: sfc@2902400 {
375				compatible = "nvidia,tegra186-sfc",
376					     "nvidia,tegra210-sfc";
377				reg = <0x2902400 0x200>;
378				sound-name-prefix = "SFC3";
379				status = "disabled";
380			};
381
382			tegra_sfc4: sfc@2902600 {
383				compatible = "nvidia,tegra186-sfc",
384					     "nvidia,tegra210-sfc";
385				reg = <0x2902600 0x200>;
386				sound-name-prefix = "SFC4";
387				status = "disabled";
388			};
389
390			tegra_mvc1: mvc@290a000 {
391				compatible = "nvidia,tegra186-mvc",
392					     "nvidia,tegra210-mvc";
393				reg = <0x290a000 0x200>;
394				sound-name-prefix = "MVC1";
395				status = "disabled";
396			};
397
398			tegra_mvc2: mvc@290a200 {
399				compatible = "nvidia,tegra186-mvc",
400					     "nvidia,tegra210-mvc";
401				reg = <0x290a200 0x200>;
402				sound-name-prefix = "MVC2";
403				status = "disabled";
404			};
405
406			tegra_amx1: amx@2903000 {
407				compatible = "nvidia,tegra186-amx",
408					     "nvidia,tegra210-amx";
409				reg = <0x2903000 0x100>;
410				sound-name-prefix = "AMX1";
411				status = "disabled";
412			};
413
414			tegra_amx2: amx@2903100 {
415				compatible = "nvidia,tegra186-amx",
416					     "nvidia,tegra210-amx";
417				reg = <0x2903100 0x100>;
418				sound-name-prefix = "AMX2";
419				status = "disabled";
420			};
421
422			tegra_amx3: amx@2903200 {
423				compatible = "nvidia,tegra186-amx",
424					     "nvidia,tegra210-amx";
425				reg = <0x2903200 0x100>;
426				sound-name-prefix = "AMX3";
427				status = "disabled";
428			};
429
430			tegra_amx4: amx@2903300 {
431				compatible = "nvidia,tegra186-amx",
432					     "nvidia,tegra210-amx";
433				reg = <0x2903300 0x100>;
434				sound-name-prefix = "AMX4";
435				status = "disabled";
436			};
437
438			tegra_adx1: adx@2903800 {
439				compatible = "nvidia,tegra186-adx",
440					     "nvidia,tegra210-adx";
441				reg = <0x2903800 0x100>;
442				sound-name-prefix = "ADX1";
443				status = "disabled";
444			};
445
446			tegra_adx2: adx@2903900 {
447				compatible = "nvidia,tegra186-adx",
448					     "nvidia,tegra210-adx";
449				reg = <0x2903900 0x100>;
450				sound-name-prefix = "ADX2";
451				status = "disabled";
452			};
453
454			tegra_adx3: adx@2903a00 {
455				compatible = "nvidia,tegra186-adx",
456					     "nvidia,tegra210-adx";
457				reg = <0x2903a00 0x100>;
458				sound-name-prefix = "ADX3";
459				status = "disabled";
460			};
461
462			tegra_adx4: adx@2903b00 {
463				compatible = "nvidia,tegra186-adx",
464					     "nvidia,tegra210-adx";
465				reg = <0x2903b00 0x100>;
466				sound-name-prefix = "ADX4";
467				status = "disabled";
468			};
469
470			tegra_amixer: amixer@290bb00 {
471				compatible = "nvidia,tegra186-amixer",
472					     "nvidia,tegra210-amixer";
473				reg = <0x290bb00 0x800>;
474				sound-name-prefix = "MIXER1";
475				status = "disabled";
476			};
477		};
478	};
479
480	mc: memory-controller@2c00000 {
481		compatible = "nvidia,tegra186-mc";
482		reg = <0x0 0x02c00000 0x0 0xb0000>;
483		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
484		status = "disabled";
485
486		#interconnect-cells = <1>;
487		#address-cells = <2>;
488		#size-cells = <2>;
489
490		ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
491
492		/*
493		 * Memory clients have access to all 40 bits that the memory
494		 * controller can address.
495		 */
496		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
497
498		emc: external-memory-controller@2c60000 {
499			compatible = "nvidia,tegra186-emc";
500			reg = <0x0 0x02c60000 0x0 0x50000>;
501			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
502			clocks = <&bpmp TEGRA186_CLK_EMC>;
503			clock-names = "emc";
504
505			#interconnect-cells = <0>;
506
507			nvidia,bpmp = <&bpmp>;
508		};
509	};
510
511	timer@3010000 {
512		compatible = "nvidia,tegra186-timer";
513		reg = <0x0 0x03010000 0x0 0x000e0000>;
514		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
515			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
516			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
517			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
518			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
519			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
520			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
521			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
522			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
523			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
524		status = "disabled";
525	};
526
527	uarta: serial@3100000 {
528		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
529		reg = <0x0 0x03100000 0x0 0x40>;
530		reg-shift = <2>;
531		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
532		clocks = <&bpmp TEGRA186_CLK_UARTA>;
533		clock-names = "serial";
534		resets = <&bpmp TEGRA186_RESET_UARTA>;
535		reset-names = "serial";
536		status = "disabled";
537	};
538
539	uartb: serial@3110000 {
540		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
541		reg = <0x0 0x03110000 0x0 0x40>;
542		reg-shift = <2>;
543		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
544		clocks = <&bpmp TEGRA186_CLK_UARTB>;
545		clock-names = "serial";
546		resets = <&bpmp TEGRA186_RESET_UARTB>;
547		reset-names = "serial";
548		status = "disabled";
549	};
550
551	uartd: serial@3130000 {
552		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
553		reg = <0x0 0x03130000 0x0 0x40>;
554		reg-shift = <2>;
555		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
556		clocks = <&bpmp TEGRA186_CLK_UARTD>;
557		clock-names = "serial";
558		resets = <&bpmp TEGRA186_RESET_UARTD>;
559		reset-names = "serial";
560		status = "disabled";
561	};
562
563	uarte: serial@3140000 {
564		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
565		reg = <0x0 0x03140000 0x0 0x40>;
566		reg-shift = <2>;
567		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
568		clocks = <&bpmp TEGRA186_CLK_UARTE>;
569		clock-names = "serial";
570		resets = <&bpmp TEGRA186_RESET_UARTE>;
571		reset-names = "serial";
572		status = "disabled";
573	};
574
575	uartf: serial@3150000 {
576		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
577		reg = <0x0 0x03150000 0x0 0x40>;
578		reg-shift = <2>;
579		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
580		clocks = <&bpmp TEGRA186_CLK_UARTF>;
581		clock-names = "serial";
582		resets = <&bpmp TEGRA186_RESET_UARTF>;
583		reset-names = "serial";
584		status = "disabled";
585	};
586
587	gen1_i2c: i2c@3160000 {
588		compatible = "nvidia,tegra186-i2c";
589		reg = <0x0 0x03160000 0x0 0x10000>;
590		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
591		#address-cells = <1>;
592		#size-cells = <0>;
593		clocks = <&bpmp TEGRA186_CLK_I2C1>;
594		clock-names = "div-clk";
595		resets = <&bpmp TEGRA186_RESET_I2C1>;
596		reset-names = "i2c";
597		status = "disabled";
598	};
599
600	cam_i2c: i2c@3180000 {
601		compatible = "nvidia,tegra186-i2c";
602		reg = <0x0 0x03180000 0x0 0x10000>;
603		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
604		#address-cells = <1>;
605		#size-cells = <0>;
606		clocks = <&bpmp TEGRA186_CLK_I2C3>;
607		clock-names = "div-clk";
608		resets = <&bpmp TEGRA186_RESET_I2C3>;
609		reset-names = "i2c";
610		status = "disabled";
611	};
612
613	/* shares pads with dpaux1 */
614	dp_aux_ch1_i2c: i2c@3190000 {
615		compatible = "nvidia,tegra186-i2c";
616		reg = <0x0 0x03190000 0x0 0x10000>;
617		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
618		#address-cells = <1>;
619		#size-cells = <0>;
620		clocks = <&bpmp TEGRA186_CLK_I2C4>;
621		clock-names = "div-clk";
622		resets = <&bpmp TEGRA186_RESET_I2C4>;
623		reset-names = "i2c";
624		pinctrl-names = "default", "idle";
625		pinctrl-0 = <&state_dpaux1_i2c>;
626		pinctrl-1 = <&state_dpaux1_off>;
627		status = "disabled";
628	};
629
630	/* controlled by BPMP, should not be enabled */
631	pwr_i2c: i2c@31a0000 {
632		compatible = "nvidia,tegra186-i2c";
633		reg = <0x0 0x031a0000 0x0 0x10000>;
634		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
635		#address-cells = <1>;
636		#size-cells = <0>;
637		clocks = <&bpmp TEGRA186_CLK_I2C5>;
638		clock-names = "div-clk";
639		resets = <&bpmp TEGRA186_RESET_I2C5>;
640		reset-names = "i2c";
641		status = "disabled";
642	};
643
644	/* shares pads with dpaux0 */
645	dp_aux_ch0_i2c: i2c@31b0000 {
646		compatible = "nvidia,tegra186-i2c";
647		reg = <0x0 0x031b0000 0x0 0x10000>;
648		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
649		#address-cells = <1>;
650		#size-cells = <0>;
651		clocks = <&bpmp TEGRA186_CLK_I2C6>;
652		clock-names = "div-clk";
653		resets = <&bpmp TEGRA186_RESET_I2C6>;
654		reset-names = "i2c";
655		pinctrl-names = "default", "idle";
656		pinctrl-0 = <&state_dpaux_i2c>;
657		pinctrl-1 = <&state_dpaux_off>;
658		status = "disabled";
659	};
660
661	gen7_i2c: i2c@31c0000 {
662		compatible = "nvidia,tegra186-i2c";
663		reg = <0x0 0x031c0000 0x0 0x10000>;
664		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
665		#address-cells = <1>;
666		#size-cells = <0>;
667		clocks = <&bpmp TEGRA186_CLK_I2C7>;
668		clock-names = "div-clk";
669		resets = <&bpmp TEGRA186_RESET_I2C7>;
670		reset-names = "i2c";
671		status = "disabled";
672	};
673
674	gen9_i2c: i2c@31e0000 {
675		compatible = "nvidia,tegra186-i2c";
676		reg = <0x0 0x031e0000 0x0 0x10000>;
677		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
678		#address-cells = <1>;
679		#size-cells = <0>;
680		clocks = <&bpmp TEGRA186_CLK_I2C9>;
681		clock-names = "div-clk";
682		resets = <&bpmp TEGRA186_RESET_I2C9>;
683		reset-names = "i2c";
684		status = "disabled";
685	};
686
687	pwm1: pwm@3280000 {
688		compatible = "nvidia,tegra186-pwm";
689		reg = <0x0 0x3280000 0x0 0x10000>;
690		clocks = <&bpmp TEGRA186_CLK_PWM1>;
691		clock-names = "pwm";
692		resets = <&bpmp TEGRA186_RESET_PWM1>;
693		reset-names = "pwm";
694		status = "disabled";
695		#pwm-cells = <2>;
696	};
697
698	pwm2: pwm@3290000 {
699		compatible = "nvidia,tegra186-pwm";
700		reg = <0x0 0x3290000 0x0 0x10000>;
701		clocks = <&bpmp TEGRA186_CLK_PWM2>;
702		clock-names = "pwm";
703		resets = <&bpmp TEGRA186_RESET_PWM2>;
704		reset-names = "pwm";
705		status = "disabled";
706		#pwm-cells = <2>;
707	};
708
709	pwm3: pwm@32a0000 {
710		compatible = "nvidia,tegra186-pwm";
711		reg = <0x0 0x32a0000 0x0 0x10000>;
712		clocks = <&bpmp TEGRA186_CLK_PWM3>;
713		clock-names = "pwm";
714		resets = <&bpmp TEGRA186_RESET_PWM3>;
715		reset-names = "pwm";
716		status = "disabled";
717		#pwm-cells = <2>;
718	};
719
720	pwm5: pwm@32c0000 {
721		compatible = "nvidia,tegra186-pwm";
722		reg = <0x0 0x32c0000 0x0 0x10000>;
723		clocks = <&bpmp TEGRA186_CLK_PWM5>;
724		clock-names = "pwm";
725		resets = <&bpmp TEGRA186_RESET_PWM5>;
726		reset-names = "pwm";
727		status = "disabled";
728		#pwm-cells = <2>;
729	};
730
731	pwm6: pwm@32d0000 {
732		compatible = "nvidia,tegra186-pwm";
733		reg = <0x0 0x32d0000 0x0 0x10000>;
734		clocks = <&bpmp TEGRA186_CLK_PWM6>;
735		clock-names = "pwm";
736		resets = <&bpmp TEGRA186_RESET_PWM6>;
737		reset-names = "pwm";
738		status = "disabled";
739		#pwm-cells = <2>;
740	};
741
742	pwm7: pwm@32e0000 {
743		compatible = "nvidia,tegra186-pwm";
744		reg = <0x0 0x32e0000 0x0 0x10000>;
745		clocks = <&bpmp TEGRA186_CLK_PWM7>;
746		clock-names = "pwm";
747		resets = <&bpmp TEGRA186_RESET_PWM7>;
748		reset-names = "pwm";
749		status = "disabled";
750		#pwm-cells = <2>;
751	};
752
753	pwm8: pwm@32f0000 {
754		compatible = "nvidia,tegra186-pwm";
755		reg = <0x0 0x32f0000 0x0 0x10000>;
756		clocks = <&bpmp TEGRA186_CLK_PWM8>;
757		clock-names = "pwm";
758		resets = <&bpmp TEGRA186_RESET_PWM8>;
759		reset-names = "pwm";
760		status = "disabled";
761		#pwm-cells = <2>;
762	};
763
764	sdmmc1: mmc@3400000 {
765		compatible = "nvidia,tegra186-sdhci";
766		reg = <0x0 0x03400000 0x0 0x10000>;
767		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
768		clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
769			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
770		clock-names = "sdhci", "tmclk";
771		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
772		reset-names = "sdhci";
773		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
774				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
775		interconnect-names = "dma-mem", "write";
776		iommus = <&smmu TEGRA186_SID_SDMMC1>;
777		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
778		pinctrl-0 = <&sdmmc1_3v3>;
779		pinctrl-1 = <&sdmmc1_1v8>;
780		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
781		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
782		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
783		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
784		nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
785		nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
786		nvidia,default-tap = <0x5>;
787		nvidia,default-trim = <0xb>;
788		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
789				  <&bpmp TEGRA186_CLK_PLLP_OUT0>;
790		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
791		status = "disabled";
792	};
793
794	sdmmc2: mmc@3420000 {
795		compatible = "nvidia,tegra186-sdhci";
796		reg = <0x0 0x03420000 0x0 0x10000>;
797		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
798		clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
799			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
800		clock-names = "sdhci", "tmclk";
801		resets = <&bpmp TEGRA186_RESET_SDMMC2>;
802		reset-names = "sdhci";
803		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
804				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
805		interconnect-names = "dma-mem", "write";
806		iommus = <&smmu TEGRA186_SID_SDMMC2>;
807		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
808		pinctrl-0 = <&sdmmc2_3v3>;
809		pinctrl-1 = <&sdmmc2_1v8>;
810		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
811		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
812		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
813		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
814		nvidia,default-tap = <0x5>;
815		nvidia,default-trim = <0xb>;
816		status = "disabled";
817	};
818
819	sdmmc3: mmc@3440000 {
820		compatible = "nvidia,tegra186-sdhci";
821		reg = <0x0 0x03440000 0x0 0x10000>;
822		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
823		clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
824			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
825		clock-names = "sdhci", "tmclk";
826		resets = <&bpmp TEGRA186_RESET_SDMMC3>;
827		reset-names = "sdhci";
828		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
829				<&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
830		interconnect-names = "dma-mem", "write";
831		iommus = <&smmu TEGRA186_SID_SDMMC3>;
832		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
833		pinctrl-0 = <&sdmmc3_3v3>;
834		pinctrl-1 = <&sdmmc3_1v8>;
835		nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
836		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
837		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
838		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
839		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
840		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
841		nvidia,default-tap = <0x5>;
842		nvidia,default-trim = <0xb>;
843		status = "disabled";
844	};
845
846	sdmmc4: mmc@3460000 {
847		compatible = "nvidia,tegra186-sdhci";
848		reg = <0x0 0x03460000 0x0 0x10000>;
849		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
850		clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
851			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
852		clock-names = "sdhci", "tmclk";
853		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
854				  <&bpmp TEGRA186_CLK_PLLC4_VCO>;
855		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
856		resets = <&bpmp TEGRA186_RESET_SDMMC4>;
857		reset-names = "sdhci";
858		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
859				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
860		interconnect-names = "dma-mem", "write";
861		iommus = <&smmu TEGRA186_SID_SDMMC4>;
862		nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
863		nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
864		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
865		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
866		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
867		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
868		nvidia,default-tap = <0x9>;
869		nvidia,default-trim = <0x5>;
870		nvidia,dqs-trim = <63>;
871		mmc-hs400-1_8v;
872		supports-cqe;
873		status = "disabled";
874	};
875
876	hda@3510000 {
877		compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
878		reg = <0x0 0x03510000 0x0 0x10000>;
879		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
880		clocks = <&bpmp TEGRA186_CLK_HDA>,
881			 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
882			 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
883		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
884		resets = <&bpmp TEGRA186_RESET_HDA>,
885			 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
886			 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
887		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
888		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
889		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
890				<&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
891		interconnect-names = "dma-mem", "write";
892		iommus = <&smmu TEGRA186_SID_HDA>;
893		status = "disabled";
894	};
895
896	padctl: padctl@3520000 {
897		compatible = "nvidia,tegra186-xusb-padctl";
898		reg = <0x0 0x03520000 0x0 0x1000>,
899		      <0x0 0x03540000 0x0 0x1000>;
900		reg-names = "padctl", "ao";
901		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
902
903		resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
904		reset-names = "padctl";
905
906		status = "disabled";
907
908		pads {
909			usb2 {
910				clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
911				clock-names = "trk";
912				status = "disabled";
913
914				lanes {
915					usb2-0 {
916						status = "disabled";
917						#phy-cells = <0>;
918					};
919
920					usb2-1 {
921						status = "disabled";
922						#phy-cells = <0>;
923					};
924
925					usb2-2 {
926						status = "disabled";
927						#phy-cells = <0>;
928					};
929				};
930			};
931
932			hsic {
933				clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
934				clock-names = "trk";
935				status = "disabled";
936
937				lanes {
938					hsic-0 {
939						status = "disabled";
940						#phy-cells = <0>;
941					};
942				};
943			};
944
945			usb3 {
946				status = "disabled";
947
948				lanes {
949					usb3-0 {
950						status = "disabled";
951						#phy-cells = <0>;
952					};
953
954					usb3-1 {
955						status = "disabled";
956						#phy-cells = <0>;
957					};
958
959					usb3-2 {
960						status = "disabled";
961						#phy-cells = <0>;
962					};
963				};
964			};
965		};
966
967		ports {
968			usb2-0 {
969				status = "disabled";
970			};
971
972			usb2-1 {
973				status = "disabled";
974			};
975
976			usb2-2 {
977				status = "disabled";
978			};
979
980			hsic-0 {
981				status = "disabled";
982			};
983
984			usb3-0 {
985				status = "disabled";
986			};
987
988			usb3-1 {
989				status = "disabled";
990			};
991
992			usb3-2 {
993				status = "disabled";
994			};
995		};
996	};
997
998	usb@3530000 {
999		compatible = "nvidia,tegra186-xusb";
1000		reg = <0x0 0x03530000 0x0 0x8000>,
1001		      <0x0 0x03538000 0x0 0x1000>;
1002		reg-names = "hcd", "fpci";
1003		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1004			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1005		clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
1006			 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
1007			 <&bpmp TEGRA186_CLK_XUSB_SS>,
1008			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1009			 <&bpmp TEGRA186_CLK_CLK_M>,
1010			 <&bpmp TEGRA186_CLK_XUSB_FS>,
1011			 <&bpmp TEGRA186_CLK_PLLU>,
1012			 <&bpmp TEGRA186_CLK_CLK_M>,
1013			 <&bpmp TEGRA186_CLK_PLLE>;
1014		clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
1015			      "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
1016			      "pll_u_480m", "clk_m", "pll_e";
1017		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1018				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1019		power-domain-names = "xusb_host", "xusb_ss";
1020		interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1021				<&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1022		interconnect-names = "dma-mem", "write";
1023		iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
1024		#address-cells = <1>;
1025		#size-cells = <0>;
1026		status = "disabled";
1027
1028		nvidia,xusb-padctl = <&padctl>;
1029	};
1030
1031	usb@3550000 {
1032		compatible = "nvidia,tegra186-xudc";
1033		reg = <0x0 0x03550000 0x0 0x8000>,
1034		      <0x0 0x03558000 0x0 0x1000>;
1035		reg-names = "base", "fpci";
1036		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1037		clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
1038			 <&bpmp TEGRA186_CLK_XUSB_SS>,
1039			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1040			 <&bpmp TEGRA186_CLK_XUSB_FS>;
1041		clock-names = "dev", "ss", "ss_src", "fs_src";
1042		interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>,
1043				<&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>;
1044		interconnect-names = "dma-mem", "write";
1045		iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
1046		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1047				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1048		power-domain-names = "dev", "ss";
1049		nvidia,xusb-padctl = <&padctl>;
1050		status = "disabled";
1051	};
1052
1053	fuse@3820000 {
1054		compatible = "nvidia,tegra186-efuse";
1055		reg = <0x0 0x03820000 0x0 0x10000>;
1056		clocks = <&bpmp TEGRA186_CLK_FUSE>;
1057		clock-names = "fuse";
1058	};
1059
1060	gic: interrupt-controller@3881000 {
1061		compatible = "arm,gic-400";
1062		#interrupt-cells = <3>;
1063		interrupt-controller;
1064		reg = <0x0 0x03881000 0x0 0x1000>,
1065		      <0x0 0x03882000 0x0 0x2000>,
1066		      <0x0 0x03884000 0x0 0x2000>,
1067		      <0x0 0x03886000 0x0 0x2000>;
1068		interrupts = <GIC_PPI 9
1069			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1070		interrupt-parent = <&gic>;
1071	};
1072
1073	cec@3960000 {
1074		compatible = "nvidia,tegra186-cec";
1075		reg = <0x0 0x03960000 0x0 0x10000>;
1076		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1077		clocks = <&bpmp TEGRA186_CLK_CEC>;
1078		clock-names = "cec";
1079		status = "disabled";
1080	};
1081
1082	hsp_top0: hsp@3c00000 {
1083		compatible = "nvidia,tegra186-hsp";
1084		reg = <0x0 0x03c00000 0x0 0xa0000>;
1085		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1086		interrupt-names = "doorbell";
1087		#mbox-cells = <2>;
1088		status = "disabled";
1089	};
1090
1091	gen2_i2c: i2c@c240000 {
1092		compatible = "nvidia,tegra186-i2c";
1093		reg = <0x0 0x0c240000 0x0 0x10000>;
1094		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1095		#address-cells = <1>;
1096		#size-cells = <0>;
1097		clocks = <&bpmp TEGRA186_CLK_I2C2>;
1098		clock-names = "div-clk";
1099		resets = <&bpmp TEGRA186_RESET_I2C2>;
1100		reset-names = "i2c";
1101		status = "disabled";
1102	};
1103
1104	gen8_i2c: i2c@c250000 {
1105		compatible = "nvidia,tegra186-i2c";
1106		reg = <0x0 0x0c250000 0x0 0x10000>;
1107		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1108		#address-cells = <1>;
1109		#size-cells = <0>;
1110		clocks = <&bpmp TEGRA186_CLK_I2C8>;
1111		clock-names = "div-clk";
1112		resets = <&bpmp TEGRA186_RESET_I2C8>;
1113		reset-names = "i2c";
1114		status = "disabled";
1115	};
1116
1117	uartc: serial@c280000 {
1118		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1119		reg = <0x0 0x0c280000 0x0 0x40>;
1120		reg-shift = <2>;
1121		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1122		clocks = <&bpmp TEGRA186_CLK_UARTC>;
1123		clock-names = "serial";
1124		resets = <&bpmp TEGRA186_RESET_UARTC>;
1125		reset-names = "serial";
1126		status = "disabled";
1127	};
1128
1129	uartg: serial@c290000 {
1130		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1131		reg = <0x0 0x0c290000 0x0 0x40>;
1132		reg-shift = <2>;
1133		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1134		clocks = <&bpmp TEGRA186_CLK_UARTG>;
1135		clock-names = "serial";
1136		resets = <&bpmp TEGRA186_RESET_UARTG>;
1137		reset-names = "serial";
1138		status = "disabled";
1139	};
1140
1141	rtc: rtc@c2a0000 {
1142		compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1143		reg = <0 0x0c2a0000 0 0x10000>;
1144		interrupt-parent = <&pmc>;
1145		interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1146		clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1147		clock-names = "rtc";
1148		status = "disabled";
1149	};
1150
1151	gpio_aon: gpio@c2f0000 {
1152		compatible = "nvidia,tegra186-gpio-aon";
1153		reg-names = "security", "gpio";
1154		reg = <0x0 0xc2f0000 0x0 0x1000>,
1155		      <0x0 0xc2f1000 0x0 0x1000>;
1156		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1157		gpio-controller;
1158		#gpio-cells = <2>;
1159		interrupt-controller;
1160		#interrupt-cells = <2>;
1161	};
1162
1163	pwm4: pwm@c340000 {
1164		compatible = "nvidia,tegra186-pwm";
1165		reg = <0x0 0xc340000 0x0 0x10000>;
1166		clocks = <&bpmp TEGRA186_CLK_PWM4>;
1167		clock-names = "pwm";
1168		resets = <&bpmp TEGRA186_RESET_PWM4>;
1169		reset-names = "pwm";
1170		status = "disabled";
1171		#pwm-cells = <2>;
1172	};
1173
1174	pmc: pmc@c360000 {
1175		compatible = "nvidia,tegra186-pmc";
1176		reg = <0 0x0c360000 0 0x10000>,
1177		      <0 0x0c370000 0 0x10000>,
1178		      <0 0x0c380000 0 0x10000>,
1179		      <0 0x0c390000 0 0x10000>;
1180		reg-names = "pmc", "wake", "aotag", "scratch";
1181
1182		#interrupt-cells = <2>;
1183		interrupt-controller;
1184
1185		sdmmc1_3v3: sdmmc1-3v3 {
1186			pins = "sdmmc1-hv";
1187			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1188		};
1189
1190		sdmmc1_1v8: sdmmc1-1v8 {
1191			pins = "sdmmc1-hv";
1192			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1193		};
1194
1195		sdmmc2_3v3: sdmmc2-3v3 {
1196			pins = "sdmmc2-hv";
1197			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1198		};
1199
1200		sdmmc2_1v8: sdmmc2-1v8 {
1201			pins = "sdmmc2-hv";
1202			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1203		};
1204
1205		sdmmc3_3v3: sdmmc3-3v3 {
1206			pins = "sdmmc3-hv";
1207			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1208		};
1209
1210		sdmmc3_1v8: sdmmc3-1v8 {
1211			pins = "sdmmc3-hv";
1212			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1213		};
1214	};
1215
1216	ccplex@e000000 {
1217		compatible = "nvidia,tegra186-ccplex-cluster";
1218		reg = <0x0 0x0e000000 0x0 0x3fffff>;
1219
1220		nvidia,bpmp = <&bpmp>;
1221	};
1222
1223	pcie@10003000 {
1224		compatible = "nvidia,tegra186-pcie";
1225		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1226		device_type = "pci";
1227		reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1228		      <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1229		      <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1230		reg-names = "pads", "afi", "cs";
1231
1232		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1233			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1234		interrupt-names = "intr", "msi";
1235
1236		#interrupt-cells = <1>;
1237		interrupt-map-mask = <0 0 0 0>;
1238		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1239
1240		bus-range = <0x00 0xff>;
1241		#address-cells = <3>;
1242		#size-cells = <2>;
1243
1244		ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1245			 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1246			 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1247			 <0x01000000 0 0x0        0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1248			 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1249			 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1250
1251		clocks = <&bpmp TEGRA186_CLK_PCIE>,
1252			 <&bpmp TEGRA186_CLK_AFI>,
1253			 <&bpmp TEGRA186_CLK_PLLE>;
1254		clock-names = "pex", "afi", "pll_e";
1255
1256		resets = <&bpmp TEGRA186_RESET_PCIE>,
1257			 <&bpmp TEGRA186_RESET_AFI>,
1258			 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1259		reset-names = "pex", "afi", "pcie_x";
1260
1261		interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
1262				<&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
1263		interconnect-names = "dma-mem", "write";
1264
1265		iommus = <&smmu TEGRA186_SID_AFI>;
1266		iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1267		iommu-map-mask = <0x0>;
1268
1269		status = "disabled";
1270
1271		pci@1,0 {
1272			device_type = "pci";
1273			assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1274			reg = <0x000800 0 0 0 0>;
1275			status = "disabled";
1276
1277			#address-cells = <3>;
1278			#size-cells = <2>;
1279			ranges;
1280
1281			nvidia,num-lanes = <2>;
1282		};
1283
1284		pci@2,0 {
1285			device_type = "pci";
1286			assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1287			reg = <0x001000 0 0 0 0>;
1288			status = "disabled";
1289
1290			#address-cells = <3>;
1291			#size-cells = <2>;
1292			ranges;
1293
1294			nvidia,num-lanes = <1>;
1295		};
1296
1297		pci@3,0 {
1298			device_type = "pci";
1299			assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1300			reg = <0x001800 0 0 0 0>;
1301			status = "disabled";
1302
1303			#address-cells = <3>;
1304			#size-cells = <2>;
1305			ranges;
1306
1307			nvidia,num-lanes = <1>;
1308		};
1309	};
1310
1311	smmu: iommu@12000000 {
1312		compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
1313		reg = <0 0x12000000 0 0x800000>;
1314		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1315			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1316			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1317			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1318			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1319			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1320			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1321			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1322			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1323			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1324			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1325			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1326			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1327			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1328			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1329			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1330			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1331			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1332			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1333			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1334			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1335			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1336			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1337			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1338			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1339			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1340			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1341			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1342			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1343			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1344			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1345			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1346			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1347			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1348			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1349			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1350			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1351			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1352			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1353			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1354			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1355			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1356			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1357			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1358			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1359			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1360			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1361			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1362			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1363			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1364			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1365			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1366			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1367			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1368			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1369			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1370			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1371			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1372			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1373			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1374			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1375			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1376			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1377			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1378			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1379		stream-match-mask = <0x7f80>;
1380		#global-interrupts = <1>;
1381		#iommu-cells = <1>;
1382
1383		nvidia,memory-controller = <&mc>;
1384	};
1385
1386	host1x@13e00000 {
1387		compatible = "nvidia,tegra186-host1x";
1388		reg = <0x0 0x13e00000 0x0 0x10000>,
1389		      <0x0 0x13e10000 0x0 0x10000>;
1390		reg-names = "hypervisor", "vm";
1391		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1392		             <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1393		interrupt-names = "syncpt", "host1x";
1394		clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1395		clock-names = "host1x";
1396		resets = <&bpmp TEGRA186_RESET_HOST1X>;
1397		reset-names = "host1x";
1398
1399		#address-cells = <1>;
1400		#size-cells = <1>;
1401
1402		ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1403
1404		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
1405		interconnect-names = "dma-mem";
1406
1407		iommus = <&smmu TEGRA186_SID_HOST1X>;
1408
1409		dpaux1: dpaux@15040000 {
1410			compatible = "nvidia,tegra186-dpaux";
1411			reg = <0x15040000 0x10000>;
1412			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1413			clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1414				 <&bpmp TEGRA186_CLK_PLLDP>;
1415			clock-names = "dpaux", "parent";
1416			resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1417			reset-names = "dpaux";
1418			status = "disabled";
1419
1420			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1421
1422			state_dpaux1_aux: pinmux-aux {
1423				groups = "dpaux-io";
1424				function = "aux";
1425			};
1426
1427			state_dpaux1_i2c: pinmux-i2c {
1428				groups = "dpaux-io";
1429				function = "i2c";
1430			};
1431
1432			state_dpaux1_off: pinmux-off {
1433				groups = "dpaux-io";
1434				function = "off";
1435			};
1436
1437			i2c-bus {
1438				#address-cells = <1>;
1439				#size-cells = <0>;
1440			};
1441		};
1442
1443		display-hub@15200000 {
1444			compatible = "nvidia,tegra186-display";
1445			reg = <0x15200000 0x00040000>;
1446			resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1447				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1448				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1449				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1450				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1451				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1452				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1453			reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1454				      "wgrp3", "wgrp4", "wgrp5";
1455			clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1456				 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1457				 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1458			clock-names = "disp", "dsc", "hub";
1459			status = "disabled";
1460
1461			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1462
1463			#address-cells = <1>;
1464			#size-cells = <1>;
1465
1466			ranges = <0x15200000 0x15200000 0x40000>;
1467
1468			display@15200000 {
1469				compatible = "nvidia,tegra186-dc";
1470				reg = <0x15200000 0x10000>;
1471				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1472				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1473				clock-names = "dc";
1474				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1475				reset-names = "dc";
1476
1477				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1478				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1479						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1480				interconnect-names = "dma-mem", "read-1";
1481				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1482
1483				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1484				nvidia,head = <0>;
1485			};
1486
1487			display@15210000 {
1488				compatible = "nvidia,tegra186-dc";
1489				reg = <0x15210000 0x10000>;
1490				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1491				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1492				clock-names = "dc";
1493				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1494				reset-names = "dc";
1495
1496				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1497				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1498						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1499				interconnect-names = "dma-mem", "read-1";
1500				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1501
1502				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1503				nvidia,head = <1>;
1504			};
1505
1506			display@15220000 {
1507				compatible = "nvidia,tegra186-dc";
1508				reg = <0x15220000 0x10000>;
1509				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1510				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1511				clock-names = "dc";
1512				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1513				reset-names = "dc";
1514
1515				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1516				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1517						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1518				interconnect-names = "dma-mem", "read-1";
1519				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1520
1521				nvidia,outputs = <&sor0 &sor1>;
1522				nvidia,head = <2>;
1523			};
1524		};
1525
1526		dsia: dsi@15300000 {
1527			compatible = "nvidia,tegra186-dsi";
1528			reg = <0x15300000 0x10000>;
1529			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1530			clocks = <&bpmp TEGRA186_CLK_DSI>,
1531				 <&bpmp TEGRA186_CLK_DSIA_LP>,
1532				 <&bpmp TEGRA186_CLK_PLLD>;
1533			clock-names = "dsi", "lp", "parent";
1534			resets = <&bpmp TEGRA186_RESET_DSI>;
1535			reset-names = "dsi";
1536			status = "disabled";
1537
1538			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1539		};
1540
1541		vic@15340000 {
1542			compatible = "nvidia,tegra186-vic";
1543			reg = <0x15340000 0x40000>;
1544			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1545			clocks = <&bpmp TEGRA186_CLK_VIC>;
1546			clock-names = "vic";
1547			resets = <&bpmp TEGRA186_RESET_VIC>;
1548			reset-names = "vic";
1549
1550			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1551			interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
1552					<&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
1553			interconnect-names = "dma-mem", "write";
1554			iommus = <&smmu TEGRA186_SID_VIC>;
1555		};
1556
1557		nvjpg@15380000 {
1558			compatible = "nvidia,tegra186-nvjpg";
1559			reg = <0x15380000 0x40000>;
1560			clocks = <&bpmp TEGRA186_CLK_NVJPG>;
1561			clock-names = "nvjpg";
1562			resets = <&bpmp TEGRA186_RESET_NVJPG>;
1563			reset-names = "nvjpg";
1564
1565			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
1566			interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
1567					<&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
1568			interconnect-names = "dma-mem", "write";
1569			iommus = <&smmu TEGRA186_SID_NVJPG>;
1570		};
1571
1572		dsib: dsi@15400000 {
1573			compatible = "nvidia,tegra186-dsi";
1574			reg = <0x15400000 0x10000>;
1575			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1576			clocks = <&bpmp TEGRA186_CLK_DSIB>,
1577				 <&bpmp TEGRA186_CLK_DSIB_LP>,
1578				 <&bpmp TEGRA186_CLK_PLLD>;
1579			clock-names = "dsi", "lp", "parent";
1580			resets = <&bpmp TEGRA186_RESET_DSIB>;
1581			reset-names = "dsi";
1582			status = "disabled";
1583
1584			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1585		};
1586
1587		nvdec@15480000 {
1588			compatible = "nvidia,tegra186-nvdec";
1589			reg = <0x15480000 0x40000>;
1590			clocks = <&bpmp TEGRA186_CLK_NVDEC>;
1591			clock-names = "nvdec";
1592			resets = <&bpmp TEGRA186_RESET_NVDEC>;
1593			reset-names = "nvdec";
1594
1595			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1596			interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
1597					<&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
1598					<&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
1599			interconnect-names = "dma-mem", "read-1", "write";
1600			iommus = <&smmu TEGRA186_SID_NVDEC>;
1601		};
1602
1603		nvenc@154c0000 {
1604			compatible = "nvidia,tegra186-nvenc";
1605			reg = <0x154c0000 0x40000>;
1606			clocks = <&bpmp TEGRA186_CLK_NVENC>;
1607			clock-names = "nvenc";
1608			resets = <&bpmp TEGRA186_RESET_NVENC>;
1609			reset-names = "nvenc";
1610
1611			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
1612			interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
1613					<&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
1614			interconnect-names = "dma-mem", "write";
1615			iommus = <&smmu TEGRA186_SID_NVENC>;
1616		};
1617
1618		sor0: sor@15540000 {
1619			compatible = "nvidia,tegra186-sor";
1620			reg = <0x15540000 0x10000>;
1621			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1622			clocks = <&bpmp TEGRA186_CLK_SOR0>,
1623				 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1624				 <&bpmp TEGRA186_CLK_PLLD2>,
1625				 <&bpmp TEGRA186_CLK_PLLDP>,
1626				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1627				 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1628			clock-names = "sor", "out", "parent", "dp", "safe",
1629				      "pad";
1630			resets = <&bpmp TEGRA186_RESET_SOR0>;
1631			reset-names = "sor";
1632			pinctrl-0 = <&state_dpaux_aux>;
1633			pinctrl-1 = <&state_dpaux_i2c>;
1634			pinctrl-2 = <&state_dpaux_off>;
1635			pinctrl-names = "aux", "i2c", "off";
1636			status = "disabled";
1637
1638			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1639			nvidia,interface = <0>;
1640		};
1641
1642		sor1: sor@15580000 {
1643			compatible = "nvidia,tegra186-sor";
1644			reg = <0x15580000 0x10000>;
1645			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1646			clocks = <&bpmp TEGRA186_CLK_SOR1>,
1647				 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1648				 <&bpmp TEGRA186_CLK_PLLD3>,
1649				 <&bpmp TEGRA186_CLK_PLLDP>,
1650				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1651				 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1652			clock-names = "sor", "out", "parent", "dp", "safe",
1653				      "pad";
1654			resets = <&bpmp TEGRA186_RESET_SOR1>;
1655			reset-names = "sor";
1656			pinctrl-0 = <&state_dpaux1_aux>;
1657			pinctrl-1 = <&state_dpaux1_i2c>;
1658			pinctrl-2 = <&state_dpaux1_off>;
1659			pinctrl-names = "aux", "i2c", "off";
1660			status = "disabled";
1661
1662			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1663			nvidia,interface = <1>;
1664		};
1665
1666		dpaux: dpaux@155c0000 {
1667			compatible = "nvidia,tegra186-dpaux";
1668			reg = <0x155c0000 0x10000>;
1669			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1670			clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1671				 <&bpmp TEGRA186_CLK_PLLDP>;
1672			clock-names = "dpaux", "parent";
1673			resets = <&bpmp TEGRA186_RESET_DPAUX>;
1674			reset-names = "dpaux";
1675			status = "disabled";
1676
1677			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1678
1679			state_dpaux_aux: pinmux-aux {
1680				groups = "dpaux-io";
1681				function = "aux";
1682			};
1683
1684			state_dpaux_i2c: pinmux-i2c {
1685				groups = "dpaux-io";
1686				function = "i2c";
1687			};
1688
1689			state_dpaux_off: pinmux-off {
1690				groups = "dpaux-io";
1691				function = "off";
1692			};
1693
1694			i2c-bus {
1695				#address-cells = <1>;
1696				#size-cells = <0>;
1697			};
1698		};
1699
1700		padctl@15880000 {
1701			compatible = "nvidia,tegra186-dsi-padctl";
1702			reg = <0x15880000 0x10000>;
1703			resets = <&bpmp TEGRA186_RESET_DSI>;
1704			reset-names = "dsi";
1705			status = "disabled";
1706		};
1707
1708		dsic: dsi@15900000 {
1709			compatible = "nvidia,tegra186-dsi";
1710			reg = <0x15900000 0x10000>;
1711			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1712			clocks = <&bpmp TEGRA186_CLK_DSIC>,
1713				 <&bpmp TEGRA186_CLK_DSIC_LP>,
1714				 <&bpmp TEGRA186_CLK_PLLD>;
1715			clock-names = "dsi", "lp", "parent";
1716			resets = <&bpmp TEGRA186_RESET_DSIC>;
1717			reset-names = "dsi";
1718			status = "disabled";
1719
1720			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1721		};
1722
1723		dsid: dsi@15940000 {
1724			compatible = "nvidia,tegra186-dsi";
1725			reg = <0x15940000 0x10000>;
1726			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1727			clocks = <&bpmp TEGRA186_CLK_DSID>,
1728				 <&bpmp TEGRA186_CLK_DSID_LP>,
1729				 <&bpmp TEGRA186_CLK_PLLD>;
1730			clock-names = "dsi", "lp", "parent";
1731			resets = <&bpmp TEGRA186_RESET_DSID>;
1732			reset-names = "dsi";
1733			status = "disabled";
1734
1735			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1736		};
1737	};
1738
1739	gpu@17000000 {
1740		compatible = "nvidia,gp10b";
1741		reg = <0x0 0x17000000 0x0 0x1000000>,
1742		      <0x0 0x18000000 0x0 0x1000000>;
1743		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1744			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1745		interrupt-names = "stall", "nonstall";
1746
1747		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1748			 <&bpmp TEGRA186_CLK_GPU>;
1749		clock-names = "gpu", "pwr";
1750		resets = <&bpmp TEGRA186_RESET_GPU>;
1751		reset-names = "gpu";
1752		status = "disabled";
1753
1754		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1755		interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
1756				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
1757				<&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
1758				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
1759		interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1760	};
1761
1762	sram@30000000 {
1763		compatible = "nvidia,tegra186-sysram", "mmio-sram";
1764		reg = <0x0 0x30000000 0x0 0x50000>;
1765		#address-cells = <1>;
1766		#size-cells = <1>;
1767		ranges = <0x0 0x0 0x30000000 0x50000>;
1768
1769		cpu_bpmp_tx: sram@4e000 {
1770			reg = <0x4e000 0x1000>;
1771			label = "cpu-bpmp-tx";
1772			pool;
1773		};
1774
1775		cpu_bpmp_rx: sram@4f000 {
1776			reg = <0x4f000 0x1000>;
1777			label = "cpu-bpmp-rx";
1778			pool;
1779		};
1780	};
1781
1782	sata@3507000 {
1783		compatible = "nvidia,tegra186-ahci";
1784		reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
1785		      <0x0 0x03500000 0x0 0x00007000>, /* SATA */
1786		      <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
1787		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1788
1789		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
1790		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,
1791				<&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;
1792		interconnect-names = "dma-mem", "write";
1793		iommus = <&smmu TEGRA186_SID_SATA>;
1794
1795		clocks = <&bpmp TEGRA186_CLK_SATA>,
1796			 <&bpmp TEGRA186_CLK_SATA_OOB>;
1797		clock-names = "sata", "sata-oob";
1798		assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
1799				  <&bpmp TEGRA186_CLK_SATA_OOB>;
1800		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
1801					 <&bpmp TEGRA186_CLK_PLLP>;
1802		assigned-clock-rates = <102000000>,
1803				       <204000000>;
1804		resets = <&bpmp TEGRA186_RESET_SATA>,
1805			<&bpmp TEGRA186_RESET_SATACOLD>;
1806		reset-names = "sata", "sata-cold";
1807		status = "disabled";
1808	};
1809
1810	bpmp: bpmp {
1811		compatible = "nvidia,tegra186-bpmp";
1812		interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
1813				<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
1814				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
1815				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
1816		interconnect-names = "read", "write", "dma-mem", "dma-write";
1817		iommus = <&smmu TEGRA186_SID_BPMP>;
1818		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1819				    TEGRA_HSP_DB_MASTER_BPMP>;
1820		shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
1821		#clock-cells = <1>;
1822		#reset-cells = <1>;
1823		#power-domain-cells = <1>;
1824
1825		bpmp_i2c: i2c {
1826			compatible = "nvidia,tegra186-bpmp-i2c";
1827			nvidia,bpmp-bus-id = <5>;
1828			#address-cells = <1>;
1829			#size-cells = <0>;
1830			status = "disabled";
1831		};
1832
1833		bpmp_thermal: thermal {
1834			compatible = "nvidia,tegra186-bpmp-thermal";
1835			#thermal-sensor-cells = <1>;
1836		};
1837	};
1838
1839	cpus {
1840		#address-cells = <1>;
1841		#size-cells = <0>;
1842
1843		denver_0: cpu@0 {
1844			compatible = "nvidia,tegra186-denver";
1845			device_type = "cpu";
1846			i-cache-size = <0x20000>;
1847			i-cache-line-size = <64>;
1848			i-cache-sets = <512>;
1849			d-cache-size = <0x10000>;
1850			d-cache-line-size = <64>;
1851			d-cache-sets = <256>;
1852			next-level-cache = <&L2_DENVER>;
1853			reg = <0x000>;
1854		};
1855
1856		denver_1: cpu@1 {
1857			compatible = "nvidia,tegra186-denver";
1858			device_type = "cpu";
1859			i-cache-size = <0x20000>;
1860			i-cache-line-size = <64>;
1861			i-cache-sets = <512>;
1862			d-cache-size = <0x10000>;
1863			d-cache-line-size = <64>;
1864			d-cache-sets = <256>;
1865			next-level-cache = <&L2_DENVER>;
1866			reg = <0x001>;
1867		};
1868
1869		ca57_0: cpu@2 {
1870			compatible = "arm,cortex-a57";
1871			device_type = "cpu";
1872			i-cache-size = <0xC000>;
1873			i-cache-line-size = <64>;
1874			i-cache-sets = <256>;
1875			d-cache-size = <0x8000>;
1876			d-cache-line-size = <64>;
1877			d-cache-sets = <256>;
1878			next-level-cache = <&L2_A57>;
1879			reg = <0x100>;
1880		};
1881
1882		ca57_1: cpu@3 {
1883			compatible = "arm,cortex-a57";
1884			device_type = "cpu";
1885			i-cache-size = <0xC000>;
1886			i-cache-line-size = <64>;
1887			i-cache-sets = <256>;
1888			d-cache-size = <0x8000>;
1889			d-cache-line-size = <64>;
1890			d-cache-sets = <256>;
1891			next-level-cache = <&L2_A57>;
1892			reg = <0x101>;
1893		};
1894
1895		ca57_2: cpu@4 {
1896			compatible = "arm,cortex-a57";
1897			device_type = "cpu";
1898			i-cache-size = <0xC000>;
1899			i-cache-line-size = <64>;
1900			i-cache-sets = <256>;
1901			d-cache-size = <0x8000>;
1902			d-cache-line-size = <64>;
1903			d-cache-sets = <256>;
1904			next-level-cache = <&L2_A57>;
1905			reg = <0x102>;
1906		};
1907
1908		ca57_3: cpu@5 {
1909			compatible = "arm,cortex-a57";
1910			device_type = "cpu";
1911			i-cache-size = <0xC000>;
1912			i-cache-line-size = <64>;
1913			i-cache-sets = <256>;
1914			d-cache-size = <0x8000>;
1915			d-cache-line-size = <64>;
1916			d-cache-sets = <256>;
1917			next-level-cache = <&L2_A57>;
1918			reg = <0x103>;
1919		};
1920
1921		L2_DENVER: l2-cache0 {
1922			compatible = "cache";
1923			cache-unified;
1924			cache-level = <2>;
1925			cache-size = <0x200000>;
1926			cache-line-size = <64>;
1927			cache-sets = <2048>;
1928		};
1929
1930		L2_A57: l2-cache1 {
1931			compatible = "cache";
1932			cache-unified;
1933			cache-level = <2>;
1934			cache-size = <0x200000>;
1935			cache-line-size = <64>;
1936			cache-sets = <2048>;
1937		};
1938	};
1939
1940	pmu_denver {
1941		compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
1942		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1943			     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1944		interrupt-affinity = <&denver_0 &denver_1>;
1945	};
1946
1947	pmu_a57 {
1948		compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
1949		interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1950			     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1951			     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1952			     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1953		interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
1954	};
1955
1956	sound {
1957		status = "disabled";
1958
1959		clocks = <&bpmp TEGRA186_CLK_PLLA>,
1960			 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
1961		clock-names = "pll_a", "plla_out0";
1962		assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
1963				  <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
1964				  <&bpmp TEGRA186_CLK_AUD_MCLK>;
1965		assigned-clock-parents = <0>,
1966					 <&bpmp TEGRA186_CLK_PLLA>,
1967					 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
1968		/*
1969		 * PLLA supports dynamic ramp. Below initial rate is chosen
1970		 * for this to work and oscillate between base rates required
1971		 * for 8x and 11.025x sample rate streams.
1972		 */
1973		assigned-clock-rates = <258000000>;
1974
1975		iommus = <&smmu TEGRA186_SID_APE>;
1976	};
1977
1978	thermal-zones {
1979		/* Cortex-A57 cluster */
1980		cpu-thermal {
1981			polling-delay = <0>;
1982			polling-delay-passive = <1000>;
1983
1984			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
1985
1986			trips {
1987				critical {
1988					temperature = <101000>;
1989					hysteresis = <0>;
1990					type = "critical";
1991				};
1992			};
1993
1994			cooling-maps {
1995			};
1996		};
1997
1998		/* Denver cluster */
1999		aux-thermal {
2000			polling-delay = <0>;
2001			polling-delay-passive = <1000>;
2002
2003			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
2004
2005			trips {
2006				critical {
2007					temperature = <101000>;
2008					hysteresis = <0>;
2009					type = "critical";
2010				};
2011			};
2012
2013			cooling-maps {
2014			};
2015		};
2016
2017		gpu-thermal {
2018			polling-delay = <0>;
2019			polling-delay-passive = <1000>;
2020
2021			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
2022
2023			trips {
2024				critical {
2025					temperature = <101000>;
2026					hysteresis = <0>;
2027					type = "critical";
2028				};
2029			};
2030
2031			cooling-maps {
2032			};
2033		};
2034
2035		pll-thermal {
2036			polling-delay = <0>;
2037			polling-delay-passive = <1000>;
2038
2039			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
2040
2041			trips {
2042				critical {
2043					temperature = <101000>;
2044					hysteresis = <0>;
2045					type = "critical";
2046				};
2047			};
2048
2049			cooling-maps {
2050			};
2051		};
2052
2053		ao-thermal {
2054			polling-delay = <0>;
2055			polling-delay-passive = <1000>;
2056
2057			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2058
2059			trips {
2060				critical {
2061					temperature = <101000>;
2062					hysteresis = <0>;
2063					type = "critical";
2064				};
2065			};
2066
2067			cooling-maps {
2068			};
2069		};
2070	};
2071
2072	timer {
2073		compatible = "arm,armv8-timer";
2074		interrupts = <GIC_PPI 13
2075				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2076			     <GIC_PPI 14
2077				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2078			     <GIC_PPI 11
2079				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2080			     <GIC_PPI 10
2081				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2082		interrupt-parent = <&gic>;
2083		always-on;
2084	};
2085};
2086