1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 gpcdma: dma-controller@2600000 { 77 compatible = "nvidia,tegra186-gpcdma"; 78 reg = <0x0 0x2600000 0x0 0x210000>; 79 resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80 reset-names = "gpcdma"; 81 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 112 #dma-cells = <1>; 113 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 114 dma-coherent; 115 status = "okay"; 116 }; 117 118 aconnect@2900000 { 119 compatible = "nvidia,tegra186-aconnect", 120 "nvidia,tegra210-aconnect"; 121 clocks = <&bpmp TEGRA186_CLK_APE>, 122 <&bpmp TEGRA186_CLK_APB2APE>; 123 clock-names = "ape", "apb2ape"; 124 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0x02900000 0x0 0x02900000 0x200000>; 128 status = "disabled"; 129 130 adma: dma-controller@2930000 { 131 compatible = "nvidia,tegra186-adma"; 132 reg = <0x02930000 0x20000>; 133 interrupt-parent = <&agic>; 134 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 166 #dma-cells = <1>; 167 clocks = <&bpmp TEGRA186_CLK_AHUB>; 168 clock-names = "d_audio"; 169 status = "disabled"; 170 }; 171 172 agic: interrupt-controller@2a40000 { 173 compatible = "nvidia,tegra186-agic", 174 "nvidia,tegra210-agic"; 175 #interrupt-cells = <3>; 176 interrupt-controller; 177 reg = <0x02a41000 0x1000>, 178 <0x02a42000 0x2000>; 179 interrupts = <GIC_SPI 145 180 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 181 clocks = <&bpmp TEGRA186_CLK_APE>; 182 clock-names = "clk"; 183 status = "disabled"; 184 }; 185 186 tegra_ahub: ahub@2900800 { 187 compatible = "nvidia,tegra186-ahub"; 188 reg = <0x02900800 0x800>; 189 clocks = <&bpmp TEGRA186_CLK_AHUB>; 190 clock-names = "ahub"; 191 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 192 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 193 #address-cells = <1>; 194 #size-cells = <1>; 195 ranges = <0x02900800 0x02900800 0x11800>; 196 status = "disabled"; 197 198 tegra_admaif: admaif@290f000 { 199 compatible = "nvidia,tegra186-admaif"; 200 reg = <0x0290f000 0x1000>; 201 dmas = <&adma 1>, <&adma 1>, 202 <&adma 2>, <&adma 2>, 203 <&adma 3>, <&adma 3>, 204 <&adma 4>, <&adma 4>, 205 <&adma 5>, <&adma 5>, 206 <&adma 6>, <&adma 6>, 207 <&adma 7>, <&adma 7>, 208 <&adma 8>, <&adma 8>, 209 <&adma 9>, <&adma 9>, 210 <&adma 10>, <&adma 10>, 211 <&adma 11>, <&adma 11>, 212 <&adma 12>, <&adma 12>, 213 <&adma 13>, <&adma 13>, 214 <&adma 14>, <&adma 14>, 215 <&adma 15>, <&adma 15>, 216 <&adma 16>, <&adma 16>, 217 <&adma 17>, <&adma 17>, 218 <&adma 18>, <&adma 18>, 219 <&adma 19>, <&adma 19>, 220 <&adma 20>, <&adma 20>; 221 dma-names = "rx1", "tx1", 222 "rx2", "tx2", 223 "rx3", "tx3", 224 "rx4", "tx4", 225 "rx5", "tx5", 226 "rx6", "tx6", 227 "rx7", "tx7", 228 "rx8", "tx8", 229 "rx9", "tx9", 230 "rx10", "tx10", 231 "rx11", "tx11", 232 "rx12", "tx12", 233 "rx13", "tx13", 234 "rx14", "tx14", 235 "rx15", "tx15", 236 "rx16", "tx16", 237 "rx17", "tx17", 238 "rx18", "tx18", 239 "rx19", "tx19", 240 "rx20", "tx20"; 241 status = "disabled"; 242 }; 243 244 tegra_i2s1: i2s@2901000 { 245 compatible = "nvidia,tegra186-i2s", 246 "nvidia,tegra210-i2s"; 247 reg = <0x2901000 0x100>; 248 clocks = <&bpmp TEGRA186_CLK_I2S1>, 249 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 250 clock-names = "i2s", "sync_input"; 251 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253 assigned-clock-rates = <1536000>; 254 sound-name-prefix = "I2S1"; 255 status = "disabled"; 256 }; 257 258 tegra_i2s2: i2s@2901100 { 259 compatible = "nvidia,tegra186-i2s", 260 "nvidia,tegra210-i2s"; 261 reg = <0x2901100 0x100>; 262 clocks = <&bpmp TEGRA186_CLK_I2S2>, 263 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 264 clock-names = "i2s", "sync_input"; 265 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267 assigned-clock-rates = <1536000>; 268 sound-name-prefix = "I2S2"; 269 status = "disabled"; 270 }; 271 272 tegra_i2s3: i2s@2901200 { 273 compatible = "nvidia,tegra186-i2s", 274 "nvidia,tegra210-i2s"; 275 reg = <0x2901200 0x100>; 276 clocks = <&bpmp TEGRA186_CLK_I2S3>, 277 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 278 clock-names = "i2s", "sync_input"; 279 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281 assigned-clock-rates = <1536000>; 282 sound-name-prefix = "I2S3"; 283 status = "disabled"; 284 }; 285 286 tegra_i2s4: i2s@2901300 { 287 compatible = "nvidia,tegra186-i2s", 288 "nvidia,tegra210-i2s"; 289 reg = <0x2901300 0x100>; 290 clocks = <&bpmp TEGRA186_CLK_I2S4>, 291 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 292 clock-names = "i2s", "sync_input"; 293 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 294 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 295 assigned-clock-rates = <1536000>; 296 sound-name-prefix = "I2S4"; 297 status = "disabled"; 298 }; 299 300 tegra_i2s5: i2s@2901400 { 301 compatible = "nvidia,tegra186-i2s", 302 "nvidia,tegra210-i2s"; 303 reg = <0x2901400 0x100>; 304 clocks = <&bpmp TEGRA186_CLK_I2S5>, 305 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 306 clock-names = "i2s", "sync_input"; 307 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 308 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 309 assigned-clock-rates = <1536000>; 310 sound-name-prefix = "I2S5"; 311 status = "disabled"; 312 }; 313 314 tegra_i2s6: i2s@2901500 { 315 compatible = "nvidia,tegra186-i2s", 316 "nvidia,tegra210-i2s"; 317 reg = <0x2901500 0x100>; 318 clocks = <&bpmp TEGRA186_CLK_I2S6>, 319 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 320 clock-names = "i2s", "sync_input"; 321 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 322 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 323 assigned-clock-rates = <1536000>; 324 sound-name-prefix = "I2S6"; 325 status = "disabled"; 326 }; 327 328 tegra_dmic1: dmic@2904000 { 329 compatible = "nvidia,tegra210-dmic"; 330 reg = <0x2904000 0x100>; 331 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 332 clock-names = "dmic"; 333 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 334 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 335 assigned-clock-rates = <3072000>; 336 sound-name-prefix = "DMIC1"; 337 status = "disabled"; 338 }; 339 340 tegra_dmic2: dmic@2904100 { 341 compatible = "nvidia,tegra210-dmic"; 342 reg = <0x2904100 0x100>; 343 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 344 clock-names = "dmic"; 345 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 346 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 347 assigned-clock-rates = <3072000>; 348 sound-name-prefix = "DMIC2"; 349 status = "disabled"; 350 }; 351 352 tegra_dmic3: dmic@2904200 { 353 compatible = "nvidia,tegra210-dmic"; 354 reg = <0x2904200 0x100>; 355 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 356 clock-names = "dmic"; 357 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 358 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 359 assigned-clock-rates = <3072000>; 360 sound-name-prefix = "DMIC3"; 361 status = "disabled"; 362 }; 363 364 tegra_dmic4: dmic@2904300 { 365 compatible = "nvidia,tegra210-dmic"; 366 reg = <0x2904300 0x100>; 367 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 368 clock-names = "dmic"; 369 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 370 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 371 assigned-clock-rates = <3072000>; 372 sound-name-prefix = "DMIC4"; 373 status = "disabled"; 374 }; 375 376 tegra_dspk1: dspk@2905000 { 377 compatible = "nvidia,tegra186-dspk"; 378 reg = <0x2905000 0x100>; 379 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 380 clock-names = "dspk"; 381 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 382 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 383 assigned-clock-rates = <12288000>; 384 sound-name-prefix = "DSPK1"; 385 status = "disabled"; 386 }; 387 388 tegra_dspk2: dspk@2905100 { 389 compatible = "nvidia,tegra186-dspk"; 390 reg = <0x2905100 0x100>; 391 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 392 clock-names = "dspk"; 393 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 394 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 395 assigned-clock-rates = <12288000>; 396 sound-name-prefix = "DSPK2"; 397 status = "disabled"; 398 }; 399 400 tegra_sfc1: sfc@2902000 { 401 compatible = "nvidia,tegra186-sfc", 402 "nvidia,tegra210-sfc"; 403 reg = <0x2902000 0x200>; 404 sound-name-prefix = "SFC1"; 405 status = "disabled"; 406 }; 407 408 tegra_sfc2: sfc@2902200 { 409 compatible = "nvidia,tegra186-sfc", 410 "nvidia,tegra210-sfc"; 411 reg = <0x2902200 0x200>; 412 sound-name-prefix = "SFC2"; 413 status = "disabled"; 414 }; 415 416 tegra_sfc3: sfc@2902400 { 417 compatible = "nvidia,tegra186-sfc", 418 "nvidia,tegra210-sfc"; 419 reg = <0x2902400 0x200>; 420 sound-name-prefix = "SFC3"; 421 status = "disabled"; 422 }; 423 424 tegra_sfc4: sfc@2902600 { 425 compatible = "nvidia,tegra186-sfc", 426 "nvidia,tegra210-sfc"; 427 reg = <0x2902600 0x200>; 428 sound-name-prefix = "SFC4"; 429 status = "disabled"; 430 }; 431 432 tegra_mvc1: mvc@290a000 { 433 compatible = "nvidia,tegra186-mvc", 434 "nvidia,tegra210-mvc"; 435 reg = <0x290a000 0x200>; 436 sound-name-prefix = "MVC1"; 437 status = "disabled"; 438 }; 439 440 tegra_mvc2: mvc@290a200 { 441 compatible = "nvidia,tegra186-mvc", 442 "nvidia,tegra210-mvc"; 443 reg = <0x290a200 0x200>; 444 sound-name-prefix = "MVC2"; 445 status = "disabled"; 446 }; 447 448 tegra_amx1: amx@2903000 { 449 compatible = "nvidia,tegra186-amx", 450 "nvidia,tegra210-amx"; 451 reg = <0x2903000 0x100>; 452 sound-name-prefix = "AMX1"; 453 status = "disabled"; 454 }; 455 456 tegra_amx2: amx@2903100 { 457 compatible = "nvidia,tegra186-amx", 458 "nvidia,tegra210-amx"; 459 reg = <0x2903100 0x100>; 460 sound-name-prefix = "AMX2"; 461 status = "disabled"; 462 }; 463 464 tegra_amx3: amx@2903200 { 465 compatible = "nvidia,tegra186-amx", 466 "nvidia,tegra210-amx"; 467 reg = <0x2903200 0x100>; 468 sound-name-prefix = "AMX3"; 469 status = "disabled"; 470 }; 471 472 tegra_amx4: amx@2903300 { 473 compatible = "nvidia,tegra186-amx", 474 "nvidia,tegra210-amx"; 475 reg = <0x2903300 0x100>; 476 sound-name-prefix = "AMX4"; 477 status = "disabled"; 478 }; 479 480 tegra_adx1: adx@2903800 { 481 compatible = "nvidia,tegra186-adx", 482 "nvidia,tegra210-adx"; 483 reg = <0x2903800 0x100>; 484 sound-name-prefix = "ADX1"; 485 status = "disabled"; 486 }; 487 488 tegra_adx2: adx@2903900 { 489 compatible = "nvidia,tegra186-adx", 490 "nvidia,tegra210-adx"; 491 reg = <0x2903900 0x100>; 492 sound-name-prefix = "ADX2"; 493 status = "disabled"; 494 }; 495 496 tegra_adx3: adx@2903a00 { 497 compatible = "nvidia,tegra186-adx", 498 "nvidia,tegra210-adx"; 499 reg = <0x2903a00 0x100>; 500 sound-name-prefix = "ADX3"; 501 status = "disabled"; 502 }; 503 504 tegra_adx4: adx@2903b00 { 505 compatible = "nvidia,tegra186-adx", 506 "nvidia,tegra210-adx"; 507 reg = <0x2903b00 0x100>; 508 sound-name-prefix = "ADX4"; 509 status = "disabled"; 510 }; 511 512 tegra_ope1: processing-engine@2908000 { 513 compatible = "nvidia,tegra186-ope", 514 "nvidia,tegra210-ope"; 515 reg = <0x2908000 0x100>; 516 #address-cells = <1>; 517 #size-cells = <1>; 518 ranges; 519 sound-name-prefix = "OPE1"; 520 status = "disabled"; 521 522 equalizer@2908100 { 523 compatible = "nvidia,tegra186-peq", 524 "nvidia,tegra210-peq"; 525 reg = <0x2908100 0x100>; 526 }; 527 528 dynamic-range-compressor@2908200 { 529 compatible = "nvidia,tegra186-mbdrc", 530 "nvidia,tegra210-mbdrc"; 531 reg = <0x2908200 0x200>; 532 }; 533 }; 534 535 tegra_amixer: amixer@290bb00 { 536 compatible = "nvidia,tegra186-amixer", 537 "nvidia,tegra210-amixer"; 538 reg = <0x290bb00 0x800>; 539 sound-name-prefix = "MIXER1"; 540 status = "disabled"; 541 }; 542 543 tegra_asrc: asrc@2910000 { 544 compatible = "nvidia,tegra186-asrc"; 545 reg = <0x2910000 0x2000>; 546 sound-name-prefix = "ASRC1"; 547 status = "disabled"; 548 }; 549 }; 550 }; 551 552 mc: memory-controller@2c00000 { 553 compatible = "nvidia,tegra186-mc"; 554 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 555 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 556 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 557 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 558 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 559 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 560 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 561 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 562 status = "disabled"; 563 564 #interconnect-cells = <1>; 565 #address-cells = <2>; 566 #size-cells = <2>; 567 568 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 569 570 /* 571 * Memory clients have access to all 40 bits that the memory 572 * controller can address. 573 */ 574 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 575 576 emc: external-memory-controller@2c60000 { 577 compatible = "nvidia,tegra186-emc"; 578 reg = <0x0 0x02c60000 0x0 0x50000>; 579 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&bpmp TEGRA186_CLK_EMC>; 581 clock-names = "emc"; 582 583 #interconnect-cells = <0>; 584 585 nvidia,bpmp = <&bpmp>; 586 }; 587 }; 588 589 timer@3010000 { 590 compatible = "nvidia,tegra186-timer"; 591 reg = <0x0 0x03010000 0x0 0x000e0000>; 592 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 602 status = "okay"; 603 }; 604 605 uarta: serial@3100000 { 606 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 607 reg = <0x0 0x03100000 0x0 0x40>; 608 reg-shift = <2>; 609 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&bpmp TEGRA186_CLK_UARTA>; 611 clock-names = "serial"; 612 resets = <&bpmp TEGRA186_RESET_UARTA>; 613 reset-names = "serial"; 614 status = "disabled"; 615 }; 616 617 uartb: serial@3110000 { 618 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 619 reg = <0x0 0x03110000 0x0 0x40>; 620 reg-shift = <2>; 621 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&bpmp TEGRA186_CLK_UARTB>; 623 clock-names = "serial"; 624 resets = <&bpmp TEGRA186_RESET_UARTB>; 625 reset-names = "serial"; 626 status = "disabled"; 627 }; 628 629 uartd: serial@3130000 { 630 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 631 reg = <0x0 0x03130000 0x0 0x40>; 632 reg-shift = <2>; 633 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&bpmp TEGRA186_CLK_UARTD>; 635 clock-names = "serial"; 636 resets = <&bpmp TEGRA186_RESET_UARTD>; 637 reset-names = "serial"; 638 status = "disabled"; 639 }; 640 641 uarte: serial@3140000 { 642 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 643 reg = <0x0 0x03140000 0x0 0x40>; 644 reg-shift = <2>; 645 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&bpmp TEGRA186_CLK_UARTE>; 647 clock-names = "serial"; 648 resets = <&bpmp TEGRA186_RESET_UARTE>; 649 reset-names = "serial"; 650 status = "disabled"; 651 }; 652 653 uartf: serial@3150000 { 654 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 655 reg = <0x0 0x03150000 0x0 0x40>; 656 reg-shift = <2>; 657 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&bpmp TEGRA186_CLK_UARTF>; 659 clock-names = "serial"; 660 resets = <&bpmp TEGRA186_RESET_UARTF>; 661 reset-names = "serial"; 662 status = "disabled"; 663 }; 664 665 gen1_i2c: i2c@3160000 { 666 compatible = "nvidia,tegra186-i2c"; 667 reg = <0x0 0x03160000 0x0 0x10000>; 668 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&bpmp TEGRA186_CLK_I2C1>; 672 clock-names = "div-clk"; 673 resets = <&bpmp TEGRA186_RESET_I2C1>; 674 reset-names = "i2c"; 675 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 676 dma-coherent; 677 dmas = <&gpcdma 21>, <&gpcdma 21>; 678 dma-names = "rx", "tx"; 679 status = "disabled"; 680 }; 681 682 cam_i2c: i2c@3180000 { 683 compatible = "nvidia,tegra186-i2c"; 684 reg = <0x0 0x03180000 0x0 0x10000>; 685 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 clocks = <&bpmp TEGRA186_CLK_I2C3>; 689 clock-names = "div-clk"; 690 resets = <&bpmp TEGRA186_RESET_I2C3>; 691 reset-names = "i2c"; 692 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 693 dma-coherent; 694 dmas = <&gpcdma 23>, <&gpcdma 23>; 695 dma-names = "rx", "tx"; 696 status = "disabled"; 697 }; 698 699 /* shares pads with dpaux1 */ 700 dp_aux_ch1_i2c: i2c@3190000 { 701 compatible = "nvidia,tegra186-i2c"; 702 reg = <0x0 0x03190000 0x0 0x10000>; 703 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 clocks = <&bpmp TEGRA186_CLK_I2C4>; 707 clock-names = "div-clk"; 708 resets = <&bpmp TEGRA186_RESET_I2C4>; 709 reset-names = "i2c"; 710 pinctrl-names = "default", "idle"; 711 pinctrl-0 = <&state_dpaux1_i2c>; 712 pinctrl-1 = <&state_dpaux1_off>; 713 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 714 dma-coherent; 715 dmas = <&gpcdma 26>, <&gpcdma 26>; 716 dma-names = "rx", "tx"; 717 status = "disabled"; 718 }; 719 720 /* controlled by BPMP, should not be enabled */ 721 pwr_i2c: i2c@31a0000 { 722 compatible = "nvidia,tegra186-i2c"; 723 reg = <0x0 0x031a0000 0x0 0x10000>; 724 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 clocks = <&bpmp TEGRA186_CLK_I2C5>; 728 clock-names = "div-clk"; 729 resets = <&bpmp TEGRA186_RESET_I2C5>; 730 reset-names = "i2c"; 731 status = "disabled"; 732 }; 733 734 /* shares pads with dpaux0 */ 735 dp_aux_ch0_i2c: i2c@31b0000 { 736 compatible = "nvidia,tegra186-i2c"; 737 reg = <0x0 0x031b0000 0x0 0x10000>; 738 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 clocks = <&bpmp TEGRA186_CLK_I2C6>; 742 clock-names = "div-clk"; 743 resets = <&bpmp TEGRA186_RESET_I2C6>; 744 reset-names = "i2c"; 745 pinctrl-names = "default", "idle"; 746 pinctrl-0 = <&state_dpaux_i2c>; 747 pinctrl-1 = <&state_dpaux_off>; 748 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 749 dma-coherent; 750 dmas = <&gpcdma 30>, <&gpcdma 30>; 751 dma-names = "rx", "tx"; 752 status = "disabled"; 753 }; 754 755 gen7_i2c: i2c@31c0000 { 756 compatible = "nvidia,tegra186-i2c"; 757 reg = <0x0 0x031c0000 0x0 0x10000>; 758 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 clocks = <&bpmp TEGRA186_CLK_I2C7>; 762 clock-names = "div-clk"; 763 resets = <&bpmp TEGRA186_RESET_I2C7>; 764 reset-names = "i2c"; 765 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 766 dma-coherent; 767 dmas = <&gpcdma 27>, <&gpcdma 27>; 768 dma-names = "rx", "tx"; 769 status = "disabled"; 770 }; 771 772 gen9_i2c: i2c@31e0000 { 773 compatible = "nvidia,tegra186-i2c"; 774 reg = <0x0 0x031e0000 0x0 0x10000>; 775 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 clocks = <&bpmp TEGRA186_CLK_I2C9>; 779 clock-names = "div-clk"; 780 resets = <&bpmp TEGRA186_RESET_I2C9>; 781 reset-names = "i2c"; 782 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 783 dma-coherent; 784 dmas = <&gpcdma 31>, <&gpcdma 31>; 785 dma-names = "rx", "tx"; 786 status = "disabled"; 787 }; 788 789 pwm1: pwm@3280000 { 790 compatible = "nvidia,tegra186-pwm"; 791 reg = <0x0 0x3280000 0x0 0x10000>; 792 clocks = <&bpmp TEGRA186_CLK_PWM1>; 793 resets = <&bpmp TEGRA186_RESET_PWM1>; 794 reset-names = "pwm"; 795 status = "disabled"; 796 #pwm-cells = <2>; 797 }; 798 799 pwm2: pwm@3290000 { 800 compatible = "nvidia,tegra186-pwm"; 801 reg = <0x0 0x3290000 0x0 0x10000>; 802 clocks = <&bpmp TEGRA186_CLK_PWM2>; 803 resets = <&bpmp TEGRA186_RESET_PWM2>; 804 reset-names = "pwm"; 805 status = "disabled"; 806 #pwm-cells = <2>; 807 }; 808 809 pwm3: pwm@32a0000 { 810 compatible = "nvidia,tegra186-pwm"; 811 reg = <0x0 0x32a0000 0x0 0x10000>; 812 clocks = <&bpmp TEGRA186_CLK_PWM3>; 813 resets = <&bpmp TEGRA186_RESET_PWM3>; 814 reset-names = "pwm"; 815 status = "disabled"; 816 #pwm-cells = <2>; 817 }; 818 819 pwm5: pwm@32c0000 { 820 compatible = "nvidia,tegra186-pwm"; 821 reg = <0x0 0x32c0000 0x0 0x10000>; 822 clocks = <&bpmp TEGRA186_CLK_PWM5>; 823 resets = <&bpmp TEGRA186_RESET_PWM5>; 824 reset-names = "pwm"; 825 status = "disabled"; 826 #pwm-cells = <2>; 827 }; 828 829 pwm6: pwm@32d0000 { 830 compatible = "nvidia,tegra186-pwm"; 831 reg = <0x0 0x32d0000 0x0 0x10000>; 832 clocks = <&bpmp TEGRA186_CLK_PWM6>; 833 resets = <&bpmp TEGRA186_RESET_PWM6>; 834 reset-names = "pwm"; 835 status = "disabled"; 836 #pwm-cells = <2>; 837 }; 838 839 pwm7: pwm@32e0000 { 840 compatible = "nvidia,tegra186-pwm"; 841 reg = <0x0 0x32e0000 0x0 0x10000>; 842 clocks = <&bpmp TEGRA186_CLK_PWM7>; 843 resets = <&bpmp TEGRA186_RESET_PWM7>; 844 reset-names = "pwm"; 845 status = "disabled"; 846 #pwm-cells = <2>; 847 }; 848 849 pwm8: pwm@32f0000 { 850 compatible = "nvidia,tegra186-pwm"; 851 reg = <0x0 0x32f0000 0x0 0x10000>; 852 clocks = <&bpmp TEGRA186_CLK_PWM8>; 853 resets = <&bpmp TEGRA186_RESET_PWM8>; 854 reset-names = "pwm"; 855 status = "disabled"; 856 #pwm-cells = <2>; 857 }; 858 859 sdmmc1: mmc@3400000 { 860 compatible = "nvidia,tegra186-sdhci"; 861 reg = <0x0 0x03400000 0x0 0x10000>; 862 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 864 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 865 clock-names = "sdhci", "tmclk"; 866 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 867 reset-names = "sdhci"; 868 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 869 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 870 interconnect-names = "dma-mem", "write"; 871 iommus = <&smmu TEGRA186_SID_SDMMC1>; 872 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 873 pinctrl-0 = <&sdmmc1_3v3>; 874 pinctrl-1 = <&sdmmc1_1v8>; 875 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 876 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 877 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 878 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 879 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 880 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 881 nvidia,default-tap = <0x5>; 882 nvidia,default-trim = <0xb>; 883 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 884 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 885 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 886 status = "disabled"; 887 }; 888 889 sdmmc2: mmc@3420000 { 890 compatible = "nvidia,tegra186-sdhci"; 891 reg = <0x0 0x03420000 0x0 0x10000>; 892 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 894 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 895 clock-names = "sdhci", "tmclk"; 896 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 897 reset-names = "sdhci"; 898 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 899 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 900 interconnect-names = "dma-mem", "write"; 901 iommus = <&smmu TEGRA186_SID_SDMMC2>; 902 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 903 pinctrl-0 = <&sdmmc2_3v3>; 904 pinctrl-1 = <&sdmmc2_1v8>; 905 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 906 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 907 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 908 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 909 nvidia,default-tap = <0x5>; 910 nvidia,default-trim = <0xb>; 911 status = "disabled"; 912 }; 913 914 sdmmc3: mmc@3440000 { 915 compatible = "nvidia,tegra186-sdhci"; 916 reg = <0x0 0x03440000 0x0 0x10000>; 917 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 919 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 920 clock-names = "sdhci", "tmclk"; 921 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 922 reset-names = "sdhci"; 923 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 924 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 925 interconnect-names = "dma-mem", "write"; 926 iommus = <&smmu TEGRA186_SID_SDMMC3>; 927 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 928 pinctrl-0 = <&sdmmc3_3v3>; 929 pinctrl-1 = <&sdmmc3_1v8>; 930 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 931 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 932 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 933 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 934 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 935 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 936 nvidia,default-tap = <0x5>; 937 nvidia,default-trim = <0xb>; 938 status = "disabled"; 939 }; 940 941 sdmmc4: mmc@3460000 { 942 compatible = "nvidia,tegra186-sdhci"; 943 reg = <0x0 0x03460000 0x0 0x10000>; 944 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 946 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 947 clock-names = "sdhci", "tmclk"; 948 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 949 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 950 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 951 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 952 reset-names = "sdhci"; 953 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 954 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 955 interconnect-names = "dma-mem", "write"; 956 iommus = <&smmu TEGRA186_SID_SDMMC4>; 957 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 958 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 959 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 960 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 961 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 962 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 963 nvidia,default-tap = <0x9>; 964 nvidia,default-trim = <0x5>; 965 nvidia,dqs-trim = <63>; 966 mmc-hs400-1_8v; 967 supports-cqe; 968 status = "disabled"; 969 }; 970 971 hda@3510000 { 972 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 973 reg = <0x0 0x03510000 0x0 0x10000>; 974 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&bpmp TEGRA186_CLK_HDA>, 976 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 977 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 978 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 979 resets = <&bpmp TEGRA186_RESET_HDA>, 980 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 981 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 982 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 983 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 984 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 985 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 986 interconnect-names = "dma-mem", "write"; 987 iommus = <&smmu TEGRA186_SID_HDA>; 988 status = "disabled"; 989 }; 990 991 padctl: padctl@3520000 { 992 compatible = "nvidia,tegra186-xusb-padctl"; 993 reg = <0x0 0x03520000 0x0 0x1000>, 994 <0x0 0x03540000 0x0 0x1000>; 995 reg-names = "padctl", "ao"; 996 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 997 998 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 999 reset-names = "padctl"; 1000 1001 status = "disabled"; 1002 1003 pads { 1004 usb2 { 1005 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 1006 clock-names = "trk"; 1007 status = "disabled"; 1008 1009 lanes { 1010 usb2-0 { 1011 status = "disabled"; 1012 #phy-cells = <0>; 1013 }; 1014 1015 usb2-1 { 1016 status = "disabled"; 1017 #phy-cells = <0>; 1018 }; 1019 1020 usb2-2 { 1021 status = "disabled"; 1022 #phy-cells = <0>; 1023 }; 1024 }; 1025 }; 1026 1027 hsic { 1028 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 1029 clock-names = "trk"; 1030 status = "disabled"; 1031 1032 lanes { 1033 hsic-0 { 1034 status = "disabled"; 1035 #phy-cells = <0>; 1036 }; 1037 }; 1038 }; 1039 1040 usb3 { 1041 status = "disabled"; 1042 1043 lanes { 1044 usb3-0 { 1045 status = "disabled"; 1046 #phy-cells = <0>; 1047 }; 1048 1049 usb3-1 { 1050 status = "disabled"; 1051 #phy-cells = <0>; 1052 }; 1053 1054 usb3-2 { 1055 status = "disabled"; 1056 #phy-cells = <0>; 1057 }; 1058 }; 1059 }; 1060 }; 1061 1062 ports { 1063 usb2-0 { 1064 status = "disabled"; 1065 }; 1066 1067 usb2-1 { 1068 status = "disabled"; 1069 }; 1070 1071 usb2-2 { 1072 status = "disabled"; 1073 }; 1074 1075 hsic-0 { 1076 status = "disabled"; 1077 }; 1078 1079 usb3-0 { 1080 status = "disabled"; 1081 }; 1082 1083 usb3-1 { 1084 status = "disabled"; 1085 }; 1086 1087 usb3-2 { 1088 status = "disabled"; 1089 }; 1090 }; 1091 }; 1092 1093 usb@3530000 { 1094 compatible = "nvidia,tegra186-xusb"; 1095 reg = <0x0 0x03530000 0x0 0x8000>, 1096 <0x0 0x03538000 0x0 0x1000>; 1097 reg-names = "hcd", "fpci"; 1098 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 1101 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 1102 <&bpmp TEGRA186_CLK_XUSB_SS>, 1103 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1104 <&bpmp TEGRA186_CLK_CLK_M>, 1105 <&bpmp TEGRA186_CLK_XUSB_FS>, 1106 <&bpmp TEGRA186_CLK_PLLU>, 1107 <&bpmp TEGRA186_CLK_CLK_M>, 1108 <&bpmp TEGRA186_CLK_PLLE>; 1109 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 1110 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 1111 "pll_u_480m", "clk_m", "pll_e"; 1112 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 1113 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1114 power-domain-names = "xusb_host", "xusb_ss"; 1115 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1116 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1117 interconnect-names = "dma-mem", "write"; 1118 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 1123 nvidia,xusb-padctl = <&padctl>; 1124 }; 1125 1126 usb@3550000 { 1127 compatible = "nvidia,tegra186-xudc"; 1128 reg = <0x0 0x03550000 0x0 0x8000>, 1129 <0x0 0x03558000 0x0 0x1000>; 1130 reg-names = "base", "fpci"; 1131 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1133 <&bpmp TEGRA186_CLK_XUSB_SS>, 1134 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1135 <&bpmp TEGRA186_CLK_XUSB_FS>; 1136 clock-names = "dev", "ss", "ss_src", "fs_src"; 1137 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1138 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1139 interconnect-names = "dma-mem", "write"; 1140 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1141 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1142 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1143 power-domain-names = "dev", "ss"; 1144 nvidia,xusb-padctl = <&padctl>; 1145 status = "disabled"; 1146 }; 1147 1148 fuse@3820000 { 1149 compatible = "nvidia,tegra186-efuse"; 1150 reg = <0x0 0x03820000 0x0 0x10000>; 1151 clocks = <&bpmp TEGRA186_CLK_FUSE>; 1152 clock-names = "fuse"; 1153 }; 1154 1155 gic: interrupt-controller@3881000 { 1156 compatible = "arm,gic-400"; 1157 #interrupt-cells = <3>; 1158 interrupt-controller; 1159 reg = <0x0 0x03881000 0x0 0x1000>, 1160 <0x0 0x03882000 0x0 0x2000>, 1161 <0x0 0x03884000 0x0 0x2000>, 1162 <0x0 0x03886000 0x0 0x2000>; 1163 interrupts = <GIC_PPI 9 1164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1165 interrupt-parent = <&gic>; 1166 }; 1167 1168 cec@3960000 { 1169 compatible = "nvidia,tegra186-cec"; 1170 reg = <0x0 0x03960000 0x0 0x10000>; 1171 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&bpmp TEGRA186_CLK_CEC>; 1173 clock-names = "cec"; 1174 status = "disabled"; 1175 }; 1176 1177 hsp_top0: hsp@3c00000 { 1178 compatible = "nvidia,tegra186-hsp"; 1179 reg = <0x0 0x03c00000 0x0 0xa0000>; 1180 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1181 interrupt-names = "doorbell"; 1182 #mbox-cells = <2>; 1183 status = "disabled"; 1184 }; 1185 1186 gen2_i2c: i2c@c240000 { 1187 compatible = "nvidia,tegra186-i2c"; 1188 reg = <0x0 0x0c240000 0x0 0x10000>; 1189 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 clocks = <&bpmp TEGRA186_CLK_I2C2>; 1193 clock-names = "div-clk"; 1194 resets = <&bpmp TEGRA186_RESET_I2C2>; 1195 reset-names = "i2c"; 1196 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 1197 dma-coherent; 1198 dmas = <&gpcdma 22>, <&gpcdma 22>; 1199 dma-names = "rx", "tx"; 1200 status = "disabled"; 1201 }; 1202 1203 gen8_i2c: i2c@c250000 { 1204 compatible = "nvidia,tegra186-i2c"; 1205 reg = <0x0 0x0c250000 0x0 0x10000>; 1206 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 clocks = <&bpmp TEGRA186_CLK_I2C8>; 1210 clock-names = "div-clk"; 1211 resets = <&bpmp TEGRA186_RESET_I2C8>; 1212 reset-names = "i2c"; 1213 iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 1214 dma-coherent; 1215 dmas = <&gpcdma 0>, <&gpcdma 0>; 1216 dma-names = "rx", "tx"; 1217 status = "disabled"; 1218 }; 1219 1220 uartc: serial@c280000 { 1221 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1222 reg = <0x0 0x0c280000 0x0 0x40>; 1223 reg-shift = <2>; 1224 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1225 clocks = <&bpmp TEGRA186_CLK_UARTC>; 1226 clock-names = "serial"; 1227 resets = <&bpmp TEGRA186_RESET_UARTC>; 1228 reset-names = "serial"; 1229 status = "disabled"; 1230 }; 1231 1232 uartg: serial@c290000 { 1233 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1234 reg = <0x0 0x0c290000 0x0 0x40>; 1235 reg-shift = <2>; 1236 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1237 clocks = <&bpmp TEGRA186_CLK_UARTG>; 1238 clock-names = "serial"; 1239 resets = <&bpmp TEGRA186_RESET_UARTG>; 1240 reset-names = "serial"; 1241 status = "disabled"; 1242 }; 1243 1244 rtc: rtc@c2a0000 { 1245 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 1246 reg = <0 0x0c2a0000 0 0x10000>; 1247 interrupt-parent = <&pmc>; 1248 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1249 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 1250 clock-names = "rtc"; 1251 status = "disabled"; 1252 }; 1253 1254 gpio_aon: gpio@c2f0000 { 1255 compatible = "nvidia,tegra186-gpio-aon"; 1256 reg-names = "security", "gpio"; 1257 reg = <0x0 0xc2f0000 0x0 0x1000>, 1258 <0x0 0xc2f1000 0x0 0x1000>; 1259 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1260 gpio-controller; 1261 #gpio-cells = <2>; 1262 interrupt-controller; 1263 #interrupt-cells = <2>; 1264 }; 1265 1266 pwm4: pwm@c340000 { 1267 compatible = "nvidia,tegra186-pwm"; 1268 reg = <0x0 0xc340000 0x0 0x10000>; 1269 clocks = <&bpmp TEGRA186_CLK_PWM4>; 1270 resets = <&bpmp TEGRA186_RESET_PWM4>; 1271 reset-names = "pwm"; 1272 status = "disabled"; 1273 #pwm-cells = <2>; 1274 }; 1275 1276 pmc: pmc@c360000 { 1277 compatible = "nvidia,tegra186-pmc"; 1278 reg = <0 0x0c360000 0 0x10000>, 1279 <0 0x0c370000 0 0x10000>, 1280 <0 0x0c380000 0 0x10000>, 1281 <0 0x0c390000 0 0x10000>; 1282 reg-names = "pmc", "wake", "aotag", "scratch"; 1283 1284 #interrupt-cells = <2>; 1285 interrupt-controller; 1286 1287 sdmmc1_3v3: sdmmc1-3v3 { 1288 pins = "sdmmc1-hv"; 1289 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1290 }; 1291 1292 sdmmc1_1v8: sdmmc1-1v8 { 1293 pins = "sdmmc1-hv"; 1294 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1295 }; 1296 1297 sdmmc2_3v3: sdmmc2-3v3 { 1298 pins = "sdmmc2-hv"; 1299 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1300 }; 1301 1302 sdmmc2_1v8: sdmmc2-1v8 { 1303 pins = "sdmmc2-hv"; 1304 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1305 }; 1306 1307 sdmmc3_3v3: sdmmc3-3v3 { 1308 pins = "sdmmc3-hv"; 1309 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1310 }; 1311 1312 sdmmc3_1v8: sdmmc3-1v8 { 1313 pins = "sdmmc3-hv"; 1314 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1315 }; 1316 }; 1317 1318 ccplex@e000000 { 1319 compatible = "nvidia,tegra186-ccplex-cluster"; 1320 reg = <0x0 0x0e000000 0x0 0x400000>; 1321 1322 nvidia,bpmp = <&bpmp>; 1323 }; 1324 1325 pcie@10003000 { 1326 compatible = "nvidia,tegra186-pcie"; 1327 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1328 device_type = "pci"; 1329 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1330 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1331 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1332 reg-names = "pads", "afi", "cs"; 1333 1334 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1335 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1336 interrupt-names = "intr", "msi"; 1337 1338 #interrupt-cells = <1>; 1339 interrupt-map-mask = <0 0 0 0>; 1340 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1341 1342 bus-range = <0x00 0xff>; 1343 #address-cells = <3>; 1344 #size-cells = <2>; 1345 1346 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1347 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1348 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1349 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1350 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1351 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1352 1353 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1354 <&bpmp TEGRA186_CLK_AFI>, 1355 <&bpmp TEGRA186_CLK_PLLE>; 1356 clock-names = "pex", "afi", "pll_e"; 1357 1358 resets = <&bpmp TEGRA186_RESET_PCIE>, 1359 <&bpmp TEGRA186_RESET_AFI>, 1360 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1361 reset-names = "pex", "afi", "pcie_x"; 1362 1363 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1364 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1365 interconnect-names = "dma-mem", "write"; 1366 1367 iommus = <&smmu TEGRA186_SID_AFI>; 1368 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1369 iommu-map-mask = <0x0>; 1370 1371 status = "disabled"; 1372 1373 pci@1,0 { 1374 device_type = "pci"; 1375 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1376 reg = <0x000800 0 0 0 0>; 1377 status = "disabled"; 1378 1379 #address-cells = <3>; 1380 #size-cells = <2>; 1381 ranges; 1382 1383 nvidia,num-lanes = <2>; 1384 }; 1385 1386 pci@2,0 { 1387 device_type = "pci"; 1388 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1389 reg = <0x001000 0 0 0 0>; 1390 status = "disabled"; 1391 1392 #address-cells = <3>; 1393 #size-cells = <2>; 1394 ranges; 1395 1396 nvidia,num-lanes = <1>; 1397 }; 1398 1399 pci@3,0 { 1400 device_type = "pci"; 1401 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1402 reg = <0x001800 0 0 0 0>; 1403 status = "disabled"; 1404 1405 #address-cells = <3>; 1406 #size-cells = <2>; 1407 ranges; 1408 1409 nvidia,num-lanes = <1>; 1410 }; 1411 }; 1412 1413 smmu: iommu@12000000 { 1414 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1415 reg = <0 0x12000000 0 0x800000>; 1416 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1481 stream-match-mask = <0x7f80>; 1482 #global-interrupts = <1>; 1483 #iommu-cells = <1>; 1484 1485 nvidia,memory-controller = <&mc>; 1486 }; 1487 1488 host1x@13e00000 { 1489 compatible = "nvidia,tegra186-host1x"; 1490 reg = <0x0 0x13e00000 0x0 0x10000>, 1491 <0x0 0x13e10000 0x0 0x10000>; 1492 reg-names = "hypervisor", "vm"; 1493 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1495 interrupt-names = "syncpt", "host1x"; 1496 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1497 clock-names = "host1x"; 1498 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1499 reset-names = "host1x"; 1500 1501 #address-cells = <1>; 1502 #size-cells = <1>; 1503 1504 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1505 1506 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1507 interconnect-names = "dma-mem"; 1508 1509 iommus = <&smmu TEGRA186_SID_HOST1X>; 1510 1511 /* Context isolation domains */ 1512 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1513 <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1514 <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1515 <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1516 <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1517 <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1518 <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1519 <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1520 1521 dpaux1: dpaux@15040000 { 1522 compatible = "nvidia,tegra186-dpaux"; 1523 reg = <0x15040000 0x10000>; 1524 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1525 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1526 <&bpmp TEGRA186_CLK_PLLDP>; 1527 clock-names = "dpaux", "parent"; 1528 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1529 reset-names = "dpaux"; 1530 status = "disabled"; 1531 1532 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1533 1534 state_dpaux1_aux: pinmux-aux { 1535 groups = "dpaux-io"; 1536 function = "aux"; 1537 }; 1538 1539 state_dpaux1_i2c: pinmux-i2c { 1540 groups = "dpaux-io"; 1541 function = "i2c"; 1542 }; 1543 1544 state_dpaux1_off: pinmux-off { 1545 groups = "dpaux-io"; 1546 function = "off"; 1547 }; 1548 1549 i2c-bus { 1550 #address-cells = <1>; 1551 #size-cells = <0>; 1552 }; 1553 }; 1554 1555 display-hub@15200000 { 1556 compatible = "nvidia,tegra186-display"; 1557 reg = <0x15200000 0x00040000>; 1558 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1559 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1560 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1561 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1562 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1563 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1564 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1565 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1566 "wgrp3", "wgrp4", "wgrp5"; 1567 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1568 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1569 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1570 clock-names = "disp", "dsc", "hub"; 1571 status = "disabled"; 1572 1573 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1574 1575 #address-cells = <1>; 1576 #size-cells = <1>; 1577 1578 ranges = <0x15200000 0x15200000 0x40000>; 1579 1580 display@15200000 { 1581 compatible = "nvidia,tegra186-dc"; 1582 reg = <0x15200000 0x10000>; 1583 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1584 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1585 clock-names = "dc"; 1586 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1587 reset-names = "dc"; 1588 1589 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1590 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1591 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1592 interconnect-names = "dma-mem", "read-1"; 1593 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1594 1595 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1596 nvidia,head = <0>; 1597 }; 1598 1599 display@15210000 { 1600 compatible = "nvidia,tegra186-dc"; 1601 reg = <0x15210000 0x10000>; 1602 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1603 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1604 clock-names = "dc"; 1605 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1606 reset-names = "dc"; 1607 1608 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1609 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1610 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1611 interconnect-names = "dma-mem", "read-1"; 1612 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1613 1614 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1615 nvidia,head = <1>; 1616 }; 1617 1618 display@15220000 { 1619 compatible = "nvidia,tegra186-dc"; 1620 reg = <0x15220000 0x10000>; 1621 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1622 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1623 clock-names = "dc"; 1624 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1625 reset-names = "dc"; 1626 1627 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1628 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1629 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1630 interconnect-names = "dma-mem", "read-1"; 1631 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1632 1633 nvidia,outputs = <&sor0 &sor1>; 1634 nvidia,head = <2>; 1635 }; 1636 }; 1637 1638 dsia: dsi@15300000 { 1639 compatible = "nvidia,tegra186-dsi"; 1640 reg = <0x15300000 0x10000>; 1641 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1642 clocks = <&bpmp TEGRA186_CLK_DSI>, 1643 <&bpmp TEGRA186_CLK_DSIA_LP>, 1644 <&bpmp TEGRA186_CLK_PLLD>; 1645 clock-names = "dsi", "lp", "parent"; 1646 resets = <&bpmp TEGRA186_RESET_DSI>; 1647 reset-names = "dsi"; 1648 status = "disabled"; 1649 1650 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1651 }; 1652 1653 vic@15340000 { 1654 compatible = "nvidia,tegra186-vic"; 1655 reg = <0x15340000 0x40000>; 1656 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1657 clocks = <&bpmp TEGRA186_CLK_VIC>; 1658 clock-names = "vic"; 1659 resets = <&bpmp TEGRA186_RESET_VIC>; 1660 reset-names = "vic"; 1661 1662 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1663 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1664 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1665 interconnect-names = "dma-mem", "write"; 1666 iommus = <&smmu TEGRA186_SID_VIC>; 1667 }; 1668 1669 nvjpg@15380000 { 1670 compatible = "nvidia,tegra186-nvjpg"; 1671 reg = <0x15380000 0x40000>; 1672 clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1673 clock-names = "nvjpg"; 1674 resets = <&bpmp TEGRA186_RESET_NVJPG>; 1675 reset-names = "nvjpg"; 1676 1677 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1678 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1679 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1680 interconnect-names = "dma-mem", "write"; 1681 iommus = <&smmu TEGRA186_SID_NVJPG>; 1682 }; 1683 1684 dsib: dsi@15400000 { 1685 compatible = "nvidia,tegra186-dsi"; 1686 reg = <0x15400000 0x10000>; 1687 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1688 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1689 <&bpmp TEGRA186_CLK_DSIB_LP>, 1690 <&bpmp TEGRA186_CLK_PLLD>; 1691 clock-names = "dsi", "lp", "parent"; 1692 resets = <&bpmp TEGRA186_RESET_DSIB>; 1693 reset-names = "dsi"; 1694 status = "disabled"; 1695 1696 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1697 }; 1698 1699 nvdec@15480000 { 1700 compatible = "nvidia,tegra186-nvdec"; 1701 reg = <0x15480000 0x40000>; 1702 clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1703 clock-names = "nvdec"; 1704 resets = <&bpmp TEGRA186_RESET_NVDEC>; 1705 reset-names = "nvdec"; 1706 1707 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1708 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1709 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1710 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1711 interconnect-names = "dma-mem", "read-1", "write"; 1712 iommus = <&smmu TEGRA186_SID_NVDEC>; 1713 }; 1714 1715 nvenc@154c0000 { 1716 compatible = "nvidia,tegra186-nvenc"; 1717 reg = <0x154c0000 0x40000>; 1718 clocks = <&bpmp TEGRA186_CLK_NVENC>; 1719 clock-names = "nvenc"; 1720 resets = <&bpmp TEGRA186_RESET_NVENC>; 1721 reset-names = "nvenc"; 1722 1723 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1724 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1725 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1726 interconnect-names = "dma-mem", "write"; 1727 iommus = <&smmu TEGRA186_SID_NVENC>; 1728 }; 1729 1730 sor0: sor@15540000 { 1731 compatible = "nvidia,tegra186-sor"; 1732 reg = <0x15540000 0x10000>; 1733 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1734 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1735 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1736 <&bpmp TEGRA186_CLK_PLLD2>, 1737 <&bpmp TEGRA186_CLK_PLLDP>, 1738 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1739 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1740 clock-names = "sor", "out", "parent", "dp", "safe", 1741 "pad"; 1742 resets = <&bpmp TEGRA186_RESET_SOR0>; 1743 reset-names = "sor"; 1744 pinctrl-0 = <&state_dpaux_aux>; 1745 pinctrl-1 = <&state_dpaux_i2c>; 1746 pinctrl-2 = <&state_dpaux_off>; 1747 pinctrl-names = "aux", "i2c", "off"; 1748 status = "disabled"; 1749 1750 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1751 nvidia,interface = <0>; 1752 }; 1753 1754 sor1: sor@15580000 { 1755 compatible = "nvidia,tegra186-sor"; 1756 reg = <0x15580000 0x10000>; 1757 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1758 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1759 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1760 <&bpmp TEGRA186_CLK_PLLD3>, 1761 <&bpmp TEGRA186_CLK_PLLDP>, 1762 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1763 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1764 clock-names = "sor", "out", "parent", "dp", "safe", 1765 "pad"; 1766 resets = <&bpmp TEGRA186_RESET_SOR1>; 1767 reset-names = "sor"; 1768 pinctrl-0 = <&state_dpaux1_aux>; 1769 pinctrl-1 = <&state_dpaux1_i2c>; 1770 pinctrl-2 = <&state_dpaux1_off>; 1771 pinctrl-names = "aux", "i2c", "off"; 1772 status = "disabled"; 1773 1774 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1775 nvidia,interface = <1>; 1776 }; 1777 1778 dpaux: dpaux@155c0000 { 1779 compatible = "nvidia,tegra186-dpaux"; 1780 reg = <0x155c0000 0x10000>; 1781 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1782 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1783 <&bpmp TEGRA186_CLK_PLLDP>; 1784 clock-names = "dpaux", "parent"; 1785 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1786 reset-names = "dpaux"; 1787 status = "disabled"; 1788 1789 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1790 1791 state_dpaux_aux: pinmux-aux { 1792 groups = "dpaux-io"; 1793 function = "aux"; 1794 }; 1795 1796 state_dpaux_i2c: pinmux-i2c { 1797 groups = "dpaux-io"; 1798 function = "i2c"; 1799 }; 1800 1801 state_dpaux_off: pinmux-off { 1802 groups = "dpaux-io"; 1803 function = "off"; 1804 }; 1805 1806 i2c-bus { 1807 #address-cells = <1>; 1808 #size-cells = <0>; 1809 }; 1810 }; 1811 1812 padctl@15880000 { 1813 compatible = "nvidia,tegra186-dsi-padctl"; 1814 reg = <0x15880000 0x10000>; 1815 resets = <&bpmp TEGRA186_RESET_DSI>; 1816 reset-names = "dsi"; 1817 status = "disabled"; 1818 }; 1819 1820 dsic: dsi@15900000 { 1821 compatible = "nvidia,tegra186-dsi"; 1822 reg = <0x15900000 0x10000>; 1823 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1824 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1825 <&bpmp TEGRA186_CLK_DSIC_LP>, 1826 <&bpmp TEGRA186_CLK_PLLD>; 1827 clock-names = "dsi", "lp", "parent"; 1828 resets = <&bpmp TEGRA186_RESET_DSIC>; 1829 reset-names = "dsi"; 1830 status = "disabled"; 1831 1832 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1833 }; 1834 1835 dsid: dsi@15940000 { 1836 compatible = "nvidia,tegra186-dsi"; 1837 reg = <0x15940000 0x10000>; 1838 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1839 clocks = <&bpmp TEGRA186_CLK_DSID>, 1840 <&bpmp TEGRA186_CLK_DSID_LP>, 1841 <&bpmp TEGRA186_CLK_PLLD>; 1842 clock-names = "dsi", "lp", "parent"; 1843 resets = <&bpmp TEGRA186_RESET_DSID>; 1844 reset-names = "dsi"; 1845 status = "disabled"; 1846 1847 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1848 }; 1849 }; 1850 1851 gpu@17000000 { 1852 compatible = "nvidia,gp10b"; 1853 reg = <0x0 0x17000000 0x0 0x1000000>, 1854 <0x0 0x18000000 0x0 0x1000000>; 1855 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1857 interrupt-names = "stall", "nonstall"; 1858 1859 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1860 <&bpmp TEGRA186_CLK_GPU>; 1861 clock-names = "gpu", "pwr"; 1862 resets = <&bpmp TEGRA186_RESET_GPU>; 1863 reset-names = "gpu"; 1864 status = "disabled"; 1865 1866 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1867 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1868 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1869 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1870 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1871 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1872 }; 1873 1874 sram@30000000 { 1875 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1876 reg = <0x0 0x30000000 0x0 0x50000>; 1877 #address-cells = <1>; 1878 #size-cells = <1>; 1879 ranges = <0x0 0x0 0x30000000 0x50000>; 1880 no-memory-wc; 1881 1882 cpu_bpmp_tx: sram@4e000 { 1883 reg = <0x4e000 0x1000>; 1884 label = "cpu-bpmp-tx"; 1885 pool; 1886 }; 1887 1888 cpu_bpmp_rx: sram@4f000 { 1889 reg = <0x4f000 0x1000>; 1890 label = "cpu-bpmp-rx"; 1891 pool; 1892 }; 1893 }; 1894 1895 sata@3507000 { 1896 compatible = "nvidia,tegra186-ahci"; 1897 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1898 <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1899 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1900 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1901 1902 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1903 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1904 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1905 interconnect-names = "dma-mem", "write"; 1906 iommus = <&smmu TEGRA186_SID_SATA>; 1907 1908 clocks = <&bpmp TEGRA186_CLK_SATA>, 1909 <&bpmp TEGRA186_CLK_SATA_OOB>; 1910 clock-names = "sata", "sata-oob"; 1911 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1912 <&bpmp TEGRA186_CLK_SATA_OOB>; 1913 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1914 <&bpmp TEGRA186_CLK_PLLP>; 1915 assigned-clock-rates = <102000000>, 1916 <204000000>; 1917 resets = <&bpmp TEGRA186_RESET_SATA>, 1918 <&bpmp TEGRA186_RESET_SATACOLD>; 1919 reset-names = "sata", "sata-cold"; 1920 status = "disabled"; 1921 }; 1922 1923 bpmp: bpmp { 1924 compatible = "nvidia,tegra186-bpmp"; 1925 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1926 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1927 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1928 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1929 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1930 iommus = <&smmu TEGRA186_SID_BPMP>; 1931 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1932 TEGRA_HSP_DB_MASTER_BPMP>; 1933 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1934 #clock-cells = <1>; 1935 #reset-cells = <1>; 1936 #power-domain-cells = <1>; 1937 1938 bpmp_i2c: i2c { 1939 compatible = "nvidia,tegra186-bpmp-i2c"; 1940 nvidia,bpmp-bus-id = <5>; 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 status = "disabled"; 1944 }; 1945 1946 bpmp_thermal: thermal { 1947 compatible = "nvidia,tegra186-bpmp-thermal"; 1948 #thermal-sensor-cells = <1>; 1949 }; 1950 }; 1951 1952 cpus { 1953 #address-cells = <1>; 1954 #size-cells = <0>; 1955 1956 denver_0: cpu@0 { 1957 compatible = "nvidia,tegra186-denver"; 1958 device_type = "cpu"; 1959 i-cache-size = <0x20000>; 1960 i-cache-line-size = <64>; 1961 i-cache-sets = <512>; 1962 d-cache-size = <0x10000>; 1963 d-cache-line-size = <64>; 1964 d-cache-sets = <256>; 1965 next-level-cache = <&L2_DENVER>; 1966 reg = <0x000>; 1967 }; 1968 1969 denver_1: cpu@1 { 1970 compatible = "nvidia,tegra186-denver"; 1971 device_type = "cpu"; 1972 i-cache-size = <0x20000>; 1973 i-cache-line-size = <64>; 1974 i-cache-sets = <512>; 1975 d-cache-size = <0x10000>; 1976 d-cache-line-size = <64>; 1977 d-cache-sets = <256>; 1978 next-level-cache = <&L2_DENVER>; 1979 reg = <0x001>; 1980 }; 1981 1982 ca57_0: cpu@2 { 1983 compatible = "arm,cortex-a57"; 1984 device_type = "cpu"; 1985 i-cache-size = <0xC000>; 1986 i-cache-line-size = <64>; 1987 i-cache-sets = <256>; 1988 d-cache-size = <0x8000>; 1989 d-cache-line-size = <64>; 1990 d-cache-sets = <256>; 1991 next-level-cache = <&L2_A57>; 1992 reg = <0x100>; 1993 }; 1994 1995 ca57_1: cpu@3 { 1996 compatible = "arm,cortex-a57"; 1997 device_type = "cpu"; 1998 i-cache-size = <0xC000>; 1999 i-cache-line-size = <64>; 2000 i-cache-sets = <256>; 2001 d-cache-size = <0x8000>; 2002 d-cache-line-size = <64>; 2003 d-cache-sets = <256>; 2004 next-level-cache = <&L2_A57>; 2005 reg = <0x101>; 2006 }; 2007 2008 ca57_2: cpu@4 { 2009 compatible = "arm,cortex-a57"; 2010 device_type = "cpu"; 2011 i-cache-size = <0xC000>; 2012 i-cache-line-size = <64>; 2013 i-cache-sets = <256>; 2014 d-cache-size = <0x8000>; 2015 d-cache-line-size = <64>; 2016 d-cache-sets = <256>; 2017 next-level-cache = <&L2_A57>; 2018 reg = <0x102>; 2019 }; 2020 2021 ca57_3: cpu@5 { 2022 compatible = "arm,cortex-a57"; 2023 device_type = "cpu"; 2024 i-cache-size = <0xC000>; 2025 i-cache-line-size = <64>; 2026 i-cache-sets = <256>; 2027 d-cache-size = <0x8000>; 2028 d-cache-line-size = <64>; 2029 d-cache-sets = <256>; 2030 next-level-cache = <&L2_A57>; 2031 reg = <0x103>; 2032 }; 2033 2034 L2_DENVER: l2-cache0 { 2035 compatible = "cache"; 2036 cache-unified; 2037 cache-level = <2>; 2038 cache-size = <0x200000>; 2039 cache-line-size = <64>; 2040 cache-sets = <2048>; 2041 }; 2042 2043 L2_A57: l2-cache1 { 2044 compatible = "cache"; 2045 cache-unified; 2046 cache-level = <2>; 2047 cache-size = <0x200000>; 2048 cache-line-size = <64>; 2049 cache-sets = <2048>; 2050 }; 2051 }; 2052 2053 pmu_denver { 2054 compatible = "nvidia,denver-pmu"; 2055 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2057 interrupt-affinity = <&denver_0 &denver_1>; 2058 }; 2059 2060 pmu_a57 { 2061 compatible = "arm,cortex-a57-pmu"; 2062 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 2066 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 2067 }; 2068 2069 sound { 2070 status = "disabled"; 2071 2072 clocks = <&bpmp TEGRA186_CLK_PLLA>, 2073 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2074 clock-names = "pll_a", "plla_out0"; 2075 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2076 <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2077 <&bpmp TEGRA186_CLK_AUD_MCLK>; 2078 assigned-clock-parents = <0>, 2079 <&bpmp TEGRA186_CLK_PLLA>, 2080 <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2081 /* 2082 * PLLA supports dynamic ramp. Below initial rate is chosen 2083 * for this to work and oscillate between base rates required 2084 * for 8x and 11.025x sample rate streams. 2085 */ 2086 assigned-clock-rates = <258000000>; 2087 2088 iommus = <&smmu TEGRA186_SID_APE>; 2089 }; 2090 2091 thermal-zones { 2092 /* Cortex-A57 cluster */ 2093 cpu-thermal { 2094 polling-delay = <0>; 2095 polling-delay-passive = <1000>; 2096 2097 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 2098 2099 trips { 2100 critical { 2101 temperature = <101000>; 2102 hysteresis = <0>; 2103 type = "critical"; 2104 }; 2105 }; 2106 2107 cooling-maps { 2108 }; 2109 }; 2110 2111 /* Denver cluster */ 2112 aux-thermal { 2113 polling-delay = <0>; 2114 polling-delay-passive = <1000>; 2115 2116 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 2117 2118 trips { 2119 critical { 2120 temperature = <101000>; 2121 hysteresis = <0>; 2122 type = "critical"; 2123 }; 2124 }; 2125 2126 cooling-maps { 2127 }; 2128 }; 2129 2130 gpu-thermal { 2131 polling-delay = <0>; 2132 polling-delay-passive = <1000>; 2133 2134 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 2135 2136 trips { 2137 critical { 2138 temperature = <101000>; 2139 hysteresis = <0>; 2140 type = "critical"; 2141 }; 2142 }; 2143 2144 cooling-maps { 2145 }; 2146 }; 2147 2148 pll-thermal { 2149 polling-delay = <0>; 2150 polling-delay-passive = <1000>; 2151 2152 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 2153 2154 trips { 2155 critical { 2156 temperature = <101000>; 2157 hysteresis = <0>; 2158 type = "critical"; 2159 }; 2160 }; 2161 2162 cooling-maps { 2163 }; 2164 }; 2165 2166 ao-thermal { 2167 polling-delay = <0>; 2168 polling-delay-passive = <1000>; 2169 2170 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 2171 2172 trips { 2173 critical { 2174 temperature = <101000>; 2175 hysteresis = <0>; 2176 type = "critical"; 2177 }; 2178 }; 2179 2180 cooling-maps { 2181 }; 2182 }; 2183 }; 2184 2185 timer { 2186 compatible = "arm,armv8-timer"; 2187 interrupts = <GIC_PPI 13 2188 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2189 <GIC_PPI 14 2190 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2191 <GIC_PPI 11 2192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2193 <GIC_PPI 10 2194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2195 interrupt-parent = <&gic>; 2196 always-on; 2197 }; 2198}; 2199