1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra186-clock.h>
3#include <dt-bindings/gpio/tegra186-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/memory/tegra186-mc.h>
7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8#include <dt-bindings/power/tegra186-powergate.h>
9#include <dt-bindings/reset/tegra186-reset.h>
10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
11
12/ {
13	compatible = "nvidia,tegra186";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	misc@100000 {
19		compatible = "nvidia,tegra186-misc";
20		reg = <0x0 0x00100000 0x0 0xf000>,
21		      <0x0 0x0010f000 0x0 0x1000>;
22	};
23
24	gpio: gpio@2200000 {
25		compatible = "nvidia,tegra186-gpio";
26		reg-names = "security", "gpio";
27		reg = <0x0 0x2200000 0x0 0x10000>,
28		      <0x0 0x2210000 0x0 0x10000>;
29		interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
30			     <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
31			     <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
33			     <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
34			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35		#interrupt-cells = <2>;
36		interrupt-controller;
37		#gpio-cells = <2>;
38		gpio-controller;
39	};
40
41	ethernet@2490000 {
42		compatible = "nvidia,tegra186-eqos",
43			     "snps,dwc-qos-ethernet-4.10";
44		reg = <0x0 0x02490000 0x0 0x10000>;
45		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56			 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57			 <&bpmp TEGRA186_CLK_EQOS_RX>,
58			 <&bpmp TEGRA186_CLK_EQOS_TX>,
59			 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61		resets = <&bpmp TEGRA186_RESET_EQOS>;
62		reset-names = "eqos";
63		interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
64				<&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
65		interconnect-names = "dma-mem", "write";
66		iommus = <&smmu TEGRA186_SID_EQOS>;
67		status = "disabled";
68
69		snps,write-requests = <1>;
70		snps,read-requests = <3>;
71		snps,burst-map = <0x7>;
72		snps,txpbl = <32>;
73		snps,rxpbl = <8>;
74	};
75
76	gpcdma: dma-controller@2600000 {
77		compatible = "nvidia,tegra186-gpcdma";
78		reg = <0x0 0x2600000 0x0 0x210000>;
79		resets = <&bpmp TEGRA186_RESET_GPCDMA>;
80		reset-names = "gpcdma";
81		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
82			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
83			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
84			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
85			     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
86			     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
87			     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
88			     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
89			     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
90			     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
91			     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
92			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
93			     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
94			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
95			     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
96			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
97			     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
98			     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
99			     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
100			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
101			     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
102			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
103			     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
104			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
105			     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
106			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
107			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
108			     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
109			     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
110			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
111			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
112		#dma-cells = <1>;
113		iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
114		dma-coherent;
115		status = "okay";
116	};
117
118	aconnect@2900000 {
119		compatible = "nvidia,tegra186-aconnect",
120			     "nvidia,tegra210-aconnect";
121		clocks = <&bpmp TEGRA186_CLK_APE>,
122			 <&bpmp TEGRA186_CLK_APB2APE>;
123		clock-names = "ape", "apb2ape";
124		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
125		#address-cells = <1>;
126		#size-cells = <1>;
127		ranges = <0x02900000 0x0 0x02900000 0x200000>;
128		status = "disabled";
129
130		adma: dma-controller@2930000 {
131			compatible = "nvidia,tegra186-adma";
132			reg = <0x02930000 0x20000>;
133			interrupt-parent = <&agic>;
134			interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
135				      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
136				      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
137				      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
138				      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
139				      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
140				      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
141				      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
142				      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
143				      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
144				      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
145				      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
146				      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
147				      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
148				      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
149				      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
150				      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
151				      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
152				      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
153				      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
154				      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
155				      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
156				      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
157				      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
158				      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
159				      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
160				      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
161				      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
162				      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
163				      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
164				      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
165				      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
166			#dma-cells = <1>;
167			clocks = <&bpmp TEGRA186_CLK_AHUB>;
168			clock-names = "d_audio";
169			status = "disabled";
170		};
171
172		agic: interrupt-controller@2a40000 {
173			compatible = "nvidia,tegra186-agic",
174				     "nvidia,tegra210-agic";
175			#interrupt-cells = <3>;
176			interrupt-controller;
177			reg = <0x02a41000 0x1000>,
178			      <0x02a42000 0x2000>;
179			interrupts = <GIC_SPI 145
180				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
181			clocks = <&bpmp TEGRA186_CLK_APE>;
182			clock-names = "clk";
183			status = "disabled";
184		};
185
186		tegra_ahub: ahub@2900800 {
187			compatible = "nvidia,tegra186-ahub";
188			reg = <0x02900800 0x800>;
189			clocks = <&bpmp TEGRA186_CLK_AHUB>;
190			clock-names = "ahub";
191			assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
192			assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
193			#address-cells = <1>;
194			#size-cells = <1>;
195			ranges = <0x02900800 0x02900800 0x11800>;
196			status = "disabled";
197
198			tegra_admaif: admaif@290f000 {
199				compatible = "nvidia,tegra186-admaif";
200				reg = <0x0290f000 0x1000>;
201				dmas = <&adma 1>, <&adma 1>,
202				       <&adma 2>, <&adma 2>,
203				       <&adma 3>, <&adma 3>,
204				       <&adma 4>, <&adma 4>,
205				       <&adma 5>, <&adma 5>,
206				       <&adma 6>, <&adma 6>,
207				       <&adma 7>, <&adma 7>,
208				       <&adma 8>, <&adma 8>,
209				       <&adma 9>, <&adma 9>,
210				       <&adma 10>, <&adma 10>,
211				       <&adma 11>, <&adma 11>,
212				       <&adma 12>, <&adma 12>,
213				       <&adma 13>, <&adma 13>,
214				       <&adma 14>, <&adma 14>,
215				       <&adma 15>, <&adma 15>,
216				       <&adma 16>, <&adma 16>,
217				       <&adma 17>, <&adma 17>,
218				       <&adma 18>, <&adma 18>,
219				       <&adma 19>, <&adma 19>,
220				       <&adma 20>, <&adma 20>;
221				dma-names = "rx1", "tx1",
222					    "rx2", "tx2",
223					    "rx3", "tx3",
224					    "rx4", "tx4",
225					    "rx5", "tx5",
226					    "rx6", "tx6",
227					    "rx7", "tx7",
228					    "rx8", "tx8",
229					    "rx9", "tx9",
230					    "rx10", "tx10",
231					    "rx11", "tx11",
232					    "rx12", "tx12",
233					    "rx13", "tx13",
234					    "rx14", "tx14",
235					    "rx15", "tx15",
236					    "rx16", "tx16",
237					    "rx17", "tx17",
238					    "rx18", "tx18",
239					    "rx19", "tx19",
240					    "rx20", "tx20";
241				status = "disabled";
242			};
243
244			tegra_i2s1: i2s@2901000 {
245				compatible = "nvidia,tegra186-i2s",
246					     "nvidia,tegra210-i2s";
247				reg = <0x2901000 0x100>;
248				clocks = <&bpmp TEGRA186_CLK_I2S1>,
249					 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
250				clock-names = "i2s", "sync_input";
251				assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
252				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
253				assigned-clock-rates = <1536000>;
254				sound-name-prefix = "I2S1";
255				status = "disabled";
256			};
257
258			tegra_i2s2: i2s@2901100 {
259				compatible = "nvidia,tegra186-i2s",
260					     "nvidia,tegra210-i2s";
261				reg = <0x2901100 0x100>;
262				clocks = <&bpmp TEGRA186_CLK_I2S2>,
263					 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
264				clock-names = "i2s", "sync_input";
265				assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
266				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
267				assigned-clock-rates = <1536000>;
268				sound-name-prefix = "I2S2";
269				status = "disabled";
270			};
271
272			tegra_i2s3: i2s@2901200 {
273				compatible = "nvidia,tegra186-i2s",
274					     "nvidia,tegra210-i2s";
275				reg = <0x2901200 0x100>;
276				clocks = <&bpmp TEGRA186_CLK_I2S3>,
277					 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
278				clock-names = "i2s", "sync_input";
279				assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
280				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
281				assigned-clock-rates = <1536000>;
282				sound-name-prefix = "I2S3";
283				status = "disabled";
284			};
285
286			tegra_i2s4: i2s@2901300 {
287				compatible = "nvidia,tegra186-i2s",
288					     "nvidia,tegra210-i2s";
289				reg = <0x2901300 0x100>;
290				clocks = <&bpmp TEGRA186_CLK_I2S4>,
291					 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
292				clock-names = "i2s", "sync_input";
293				assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
294				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
295				assigned-clock-rates = <1536000>;
296				sound-name-prefix = "I2S4";
297				status = "disabled";
298			};
299
300			tegra_i2s5: i2s@2901400 {
301				compatible = "nvidia,tegra186-i2s",
302					     "nvidia,tegra210-i2s";
303				reg = <0x2901400 0x100>;
304				clocks = <&bpmp TEGRA186_CLK_I2S5>,
305					 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
306				clock-names = "i2s", "sync_input";
307				assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
308				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
309				assigned-clock-rates = <1536000>;
310				sound-name-prefix = "I2S5";
311				status = "disabled";
312			};
313
314			tegra_i2s6: i2s@2901500 {
315				compatible = "nvidia,tegra186-i2s",
316					     "nvidia,tegra210-i2s";
317				reg = <0x2901500 0x100>;
318				clocks = <&bpmp TEGRA186_CLK_I2S6>,
319					 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
320				clock-names = "i2s", "sync_input";
321				assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
322				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
323				assigned-clock-rates = <1536000>;
324				sound-name-prefix = "I2S6";
325				status = "disabled";
326			};
327
328			tegra_dmic1: dmic@2904000 {
329				compatible = "nvidia,tegra210-dmic";
330				reg = <0x2904000 0x100>;
331				clocks = <&bpmp TEGRA186_CLK_DMIC1>;
332				clock-names = "dmic";
333				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
334				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
335				assigned-clock-rates = <3072000>;
336				sound-name-prefix = "DMIC1";
337				status = "disabled";
338			};
339
340			tegra_dmic2: dmic@2904100 {
341				compatible = "nvidia,tegra210-dmic";
342				reg = <0x2904100 0x100>;
343				clocks = <&bpmp TEGRA186_CLK_DMIC2>;
344				clock-names = "dmic";
345				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
346				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
347				assigned-clock-rates = <3072000>;
348				sound-name-prefix = "DMIC2";
349				status = "disabled";
350			};
351
352			tegra_dmic3: dmic@2904200 {
353				compatible = "nvidia,tegra210-dmic";
354				reg = <0x2904200 0x100>;
355				clocks = <&bpmp TEGRA186_CLK_DMIC3>;
356				clock-names = "dmic";
357				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
358				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
359				assigned-clock-rates = <3072000>;
360				sound-name-prefix = "DMIC3";
361				status = "disabled";
362			};
363
364			tegra_dmic4: dmic@2904300 {
365				compatible = "nvidia,tegra210-dmic";
366				reg = <0x2904300 0x100>;
367				clocks = <&bpmp TEGRA186_CLK_DMIC4>;
368				clock-names = "dmic";
369				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
370				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
371				assigned-clock-rates = <3072000>;
372				sound-name-prefix = "DMIC4";
373				status = "disabled";
374			};
375
376			tegra_dspk1: dspk@2905000 {
377				compatible = "nvidia,tegra186-dspk";
378				reg = <0x2905000 0x100>;
379				clocks = <&bpmp TEGRA186_CLK_DSPK1>;
380				clock-names = "dspk";
381				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
382				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
383				assigned-clock-rates = <12288000>;
384				sound-name-prefix = "DSPK1";
385				status = "disabled";
386			};
387
388			tegra_dspk2: dspk@2905100 {
389				compatible = "nvidia,tegra186-dspk";
390				reg = <0x2905100 0x100>;
391				clocks = <&bpmp TEGRA186_CLK_DSPK2>;
392				clock-names = "dspk";
393				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
394				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
395				assigned-clock-rates = <12288000>;
396				sound-name-prefix = "DSPK2";
397				status = "disabled";
398			};
399
400			tegra_sfc1: sfc@2902000 {
401				compatible = "nvidia,tegra186-sfc",
402					     "nvidia,tegra210-sfc";
403				reg = <0x2902000 0x200>;
404				sound-name-prefix = "SFC1";
405				status = "disabled";
406			};
407
408			tegra_sfc2: sfc@2902200 {
409				compatible = "nvidia,tegra186-sfc",
410					     "nvidia,tegra210-sfc";
411				reg = <0x2902200 0x200>;
412				sound-name-prefix = "SFC2";
413				status = "disabled";
414			};
415
416			tegra_sfc3: sfc@2902400 {
417				compatible = "nvidia,tegra186-sfc",
418					     "nvidia,tegra210-sfc";
419				reg = <0x2902400 0x200>;
420				sound-name-prefix = "SFC3";
421				status = "disabled";
422			};
423
424			tegra_sfc4: sfc@2902600 {
425				compatible = "nvidia,tegra186-sfc",
426					     "nvidia,tegra210-sfc";
427				reg = <0x2902600 0x200>;
428				sound-name-prefix = "SFC4";
429				status = "disabled";
430			};
431
432			tegra_mvc1: mvc@290a000 {
433				compatible = "nvidia,tegra186-mvc",
434					     "nvidia,tegra210-mvc";
435				reg = <0x290a000 0x200>;
436				sound-name-prefix = "MVC1";
437				status = "disabled";
438			};
439
440			tegra_mvc2: mvc@290a200 {
441				compatible = "nvidia,tegra186-mvc",
442					     "nvidia,tegra210-mvc";
443				reg = <0x290a200 0x200>;
444				sound-name-prefix = "MVC2";
445				status = "disabled";
446			};
447
448			tegra_amx1: amx@2903000 {
449				compatible = "nvidia,tegra186-amx",
450					     "nvidia,tegra210-amx";
451				reg = <0x2903000 0x100>;
452				sound-name-prefix = "AMX1";
453				status = "disabled";
454			};
455
456			tegra_amx2: amx@2903100 {
457				compatible = "nvidia,tegra186-amx",
458					     "nvidia,tegra210-amx";
459				reg = <0x2903100 0x100>;
460				sound-name-prefix = "AMX2";
461				status = "disabled";
462			};
463
464			tegra_amx3: amx@2903200 {
465				compatible = "nvidia,tegra186-amx",
466					     "nvidia,tegra210-amx";
467				reg = <0x2903200 0x100>;
468				sound-name-prefix = "AMX3";
469				status = "disabled";
470			};
471
472			tegra_amx4: amx@2903300 {
473				compatible = "nvidia,tegra186-amx",
474					     "nvidia,tegra210-amx";
475				reg = <0x2903300 0x100>;
476				sound-name-prefix = "AMX4";
477				status = "disabled";
478			};
479
480			tegra_adx1: adx@2903800 {
481				compatible = "nvidia,tegra186-adx",
482					     "nvidia,tegra210-adx";
483				reg = <0x2903800 0x100>;
484				sound-name-prefix = "ADX1";
485				status = "disabled";
486			};
487
488			tegra_adx2: adx@2903900 {
489				compatible = "nvidia,tegra186-adx",
490					     "nvidia,tegra210-adx";
491				reg = <0x2903900 0x100>;
492				sound-name-prefix = "ADX2";
493				status = "disabled";
494			};
495
496			tegra_adx3: adx@2903a00 {
497				compatible = "nvidia,tegra186-adx",
498					     "nvidia,tegra210-adx";
499				reg = <0x2903a00 0x100>;
500				sound-name-prefix = "ADX3";
501				status = "disabled";
502			};
503
504			tegra_adx4: adx@2903b00 {
505				compatible = "nvidia,tegra186-adx",
506					     "nvidia,tegra210-adx";
507				reg = <0x2903b00 0x100>;
508				sound-name-prefix = "ADX4";
509				status = "disabled";
510			};
511
512			tegra_amixer: amixer@290bb00 {
513				compatible = "nvidia,tegra186-amixer",
514					     "nvidia,tegra210-amixer";
515				reg = <0x290bb00 0x800>;
516				sound-name-prefix = "MIXER1";
517				status = "disabled";
518			};
519
520			tegra_asrc: asrc@2910000 {
521				compatible = "nvidia,tegra186-asrc";
522				reg = <0x2910000 0x2000>;
523				sound-name-prefix = "ASRC1";
524				status = "disabled";
525			};
526		};
527	};
528
529	mc: memory-controller@2c00000 {
530		compatible = "nvidia,tegra186-mc";
531		reg = <0x0 0x02c00000 0x0 0xb0000>;
532		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
533		status = "disabled";
534
535		#interconnect-cells = <1>;
536		#address-cells = <2>;
537		#size-cells = <2>;
538
539		ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
540
541		/*
542		 * Memory clients have access to all 40 bits that the memory
543		 * controller can address.
544		 */
545		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
546
547		emc: external-memory-controller@2c60000 {
548			compatible = "nvidia,tegra186-emc";
549			reg = <0x0 0x02c60000 0x0 0x50000>;
550			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
551			clocks = <&bpmp TEGRA186_CLK_EMC>;
552			clock-names = "emc";
553
554			#interconnect-cells = <0>;
555
556			nvidia,bpmp = <&bpmp>;
557		};
558	};
559
560	timer@3010000 {
561		compatible = "nvidia,tegra186-timer";
562		reg = <0x0 0x03010000 0x0 0x000e0000>;
563		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
564			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
565			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
566			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
567			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
568			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
569			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
570			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
571			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
572			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
573		status = "disabled";
574	};
575
576	uarta: serial@3100000 {
577		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
578		reg = <0x0 0x03100000 0x0 0x40>;
579		reg-shift = <2>;
580		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
581		clocks = <&bpmp TEGRA186_CLK_UARTA>;
582		clock-names = "serial";
583		resets = <&bpmp TEGRA186_RESET_UARTA>;
584		reset-names = "serial";
585		status = "disabled";
586	};
587
588	uartb: serial@3110000 {
589		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
590		reg = <0x0 0x03110000 0x0 0x40>;
591		reg-shift = <2>;
592		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
593		clocks = <&bpmp TEGRA186_CLK_UARTB>;
594		clock-names = "serial";
595		resets = <&bpmp TEGRA186_RESET_UARTB>;
596		reset-names = "serial";
597		status = "disabled";
598	};
599
600	uartd: serial@3130000 {
601		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
602		reg = <0x0 0x03130000 0x0 0x40>;
603		reg-shift = <2>;
604		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
605		clocks = <&bpmp TEGRA186_CLK_UARTD>;
606		clock-names = "serial";
607		resets = <&bpmp TEGRA186_RESET_UARTD>;
608		reset-names = "serial";
609		status = "disabled";
610	};
611
612	uarte: serial@3140000 {
613		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
614		reg = <0x0 0x03140000 0x0 0x40>;
615		reg-shift = <2>;
616		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
617		clocks = <&bpmp TEGRA186_CLK_UARTE>;
618		clock-names = "serial";
619		resets = <&bpmp TEGRA186_RESET_UARTE>;
620		reset-names = "serial";
621		status = "disabled";
622	};
623
624	uartf: serial@3150000 {
625		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
626		reg = <0x0 0x03150000 0x0 0x40>;
627		reg-shift = <2>;
628		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
629		clocks = <&bpmp TEGRA186_CLK_UARTF>;
630		clock-names = "serial";
631		resets = <&bpmp TEGRA186_RESET_UARTF>;
632		reset-names = "serial";
633		status = "disabled";
634	};
635
636	gen1_i2c: i2c@3160000 {
637		compatible = "nvidia,tegra186-i2c";
638		reg = <0x0 0x03160000 0x0 0x10000>;
639		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
640		#address-cells = <1>;
641		#size-cells = <0>;
642		clocks = <&bpmp TEGRA186_CLK_I2C1>;
643		clock-names = "div-clk";
644		resets = <&bpmp TEGRA186_RESET_I2C1>;
645		reset-names = "i2c";
646		status = "disabled";
647	};
648
649	cam_i2c: i2c@3180000 {
650		compatible = "nvidia,tegra186-i2c";
651		reg = <0x0 0x03180000 0x0 0x10000>;
652		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
653		#address-cells = <1>;
654		#size-cells = <0>;
655		clocks = <&bpmp TEGRA186_CLK_I2C3>;
656		clock-names = "div-clk";
657		resets = <&bpmp TEGRA186_RESET_I2C3>;
658		reset-names = "i2c";
659		status = "disabled";
660	};
661
662	/* shares pads with dpaux1 */
663	dp_aux_ch1_i2c: i2c@3190000 {
664		compatible = "nvidia,tegra186-i2c";
665		reg = <0x0 0x03190000 0x0 0x10000>;
666		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
667		#address-cells = <1>;
668		#size-cells = <0>;
669		clocks = <&bpmp TEGRA186_CLK_I2C4>;
670		clock-names = "div-clk";
671		resets = <&bpmp TEGRA186_RESET_I2C4>;
672		reset-names = "i2c";
673		pinctrl-names = "default", "idle";
674		pinctrl-0 = <&state_dpaux1_i2c>;
675		pinctrl-1 = <&state_dpaux1_off>;
676		status = "disabled";
677	};
678
679	/* controlled by BPMP, should not be enabled */
680	pwr_i2c: i2c@31a0000 {
681		compatible = "nvidia,tegra186-i2c";
682		reg = <0x0 0x031a0000 0x0 0x10000>;
683		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
684		#address-cells = <1>;
685		#size-cells = <0>;
686		clocks = <&bpmp TEGRA186_CLK_I2C5>;
687		clock-names = "div-clk";
688		resets = <&bpmp TEGRA186_RESET_I2C5>;
689		reset-names = "i2c";
690		status = "disabled";
691	};
692
693	/* shares pads with dpaux0 */
694	dp_aux_ch0_i2c: i2c@31b0000 {
695		compatible = "nvidia,tegra186-i2c";
696		reg = <0x0 0x031b0000 0x0 0x10000>;
697		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
698		#address-cells = <1>;
699		#size-cells = <0>;
700		clocks = <&bpmp TEGRA186_CLK_I2C6>;
701		clock-names = "div-clk";
702		resets = <&bpmp TEGRA186_RESET_I2C6>;
703		reset-names = "i2c";
704		pinctrl-names = "default", "idle";
705		pinctrl-0 = <&state_dpaux_i2c>;
706		pinctrl-1 = <&state_dpaux_off>;
707		status = "disabled";
708	};
709
710	gen7_i2c: i2c@31c0000 {
711		compatible = "nvidia,tegra186-i2c";
712		reg = <0x0 0x031c0000 0x0 0x10000>;
713		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
714		#address-cells = <1>;
715		#size-cells = <0>;
716		clocks = <&bpmp TEGRA186_CLK_I2C7>;
717		clock-names = "div-clk";
718		resets = <&bpmp TEGRA186_RESET_I2C7>;
719		reset-names = "i2c";
720		status = "disabled";
721	};
722
723	gen9_i2c: i2c@31e0000 {
724		compatible = "nvidia,tegra186-i2c";
725		reg = <0x0 0x031e0000 0x0 0x10000>;
726		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
727		#address-cells = <1>;
728		#size-cells = <0>;
729		clocks = <&bpmp TEGRA186_CLK_I2C9>;
730		clock-names = "div-clk";
731		resets = <&bpmp TEGRA186_RESET_I2C9>;
732		reset-names = "i2c";
733		status = "disabled";
734	};
735
736	pwm1: pwm@3280000 {
737		compatible = "nvidia,tegra186-pwm";
738		reg = <0x0 0x3280000 0x0 0x10000>;
739		clocks = <&bpmp TEGRA186_CLK_PWM1>;
740		clock-names = "pwm";
741		resets = <&bpmp TEGRA186_RESET_PWM1>;
742		reset-names = "pwm";
743		status = "disabled";
744		#pwm-cells = <2>;
745	};
746
747	pwm2: pwm@3290000 {
748		compatible = "nvidia,tegra186-pwm";
749		reg = <0x0 0x3290000 0x0 0x10000>;
750		clocks = <&bpmp TEGRA186_CLK_PWM2>;
751		clock-names = "pwm";
752		resets = <&bpmp TEGRA186_RESET_PWM2>;
753		reset-names = "pwm";
754		status = "disabled";
755		#pwm-cells = <2>;
756	};
757
758	pwm3: pwm@32a0000 {
759		compatible = "nvidia,tegra186-pwm";
760		reg = <0x0 0x32a0000 0x0 0x10000>;
761		clocks = <&bpmp TEGRA186_CLK_PWM3>;
762		clock-names = "pwm";
763		resets = <&bpmp TEGRA186_RESET_PWM3>;
764		reset-names = "pwm";
765		status = "disabled";
766		#pwm-cells = <2>;
767	};
768
769	pwm5: pwm@32c0000 {
770		compatible = "nvidia,tegra186-pwm";
771		reg = <0x0 0x32c0000 0x0 0x10000>;
772		clocks = <&bpmp TEGRA186_CLK_PWM5>;
773		clock-names = "pwm";
774		resets = <&bpmp TEGRA186_RESET_PWM5>;
775		reset-names = "pwm";
776		status = "disabled";
777		#pwm-cells = <2>;
778	};
779
780	pwm6: pwm@32d0000 {
781		compatible = "nvidia,tegra186-pwm";
782		reg = <0x0 0x32d0000 0x0 0x10000>;
783		clocks = <&bpmp TEGRA186_CLK_PWM6>;
784		clock-names = "pwm";
785		resets = <&bpmp TEGRA186_RESET_PWM6>;
786		reset-names = "pwm";
787		status = "disabled";
788		#pwm-cells = <2>;
789	};
790
791	pwm7: pwm@32e0000 {
792		compatible = "nvidia,tegra186-pwm";
793		reg = <0x0 0x32e0000 0x0 0x10000>;
794		clocks = <&bpmp TEGRA186_CLK_PWM7>;
795		clock-names = "pwm";
796		resets = <&bpmp TEGRA186_RESET_PWM7>;
797		reset-names = "pwm";
798		status = "disabled";
799		#pwm-cells = <2>;
800	};
801
802	pwm8: pwm@32f0000 {
803		compatible = "nvidia,tegra186-pwm";
804		reg = <0x0 0x32f0000 0x0 0x10000>;
805		clocks = <&bpmp TEGRA186_CLK_PWM8>;
806		clock-names = "pwm";
807		resets = <&bpmp TEGRA186_RESET_PWM8>;
808		reset-names = "pwm";
809		status = "disabled";
810		#pwm-cells = <2>;
811	};
812
813	sdmmc1: mmc@3400000 {
814		compatible = "nvidia,tegra186-sdhci";
815		reg = <0x0 0x03400000 0x0 0x10000>;
816		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
817		clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
818			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
819		clock-names = "sdhci", "tmclk";
820		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
821		reset-names = "sdhci";
822		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
823				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
824		interconnect-names = "dma-mem", "write";
825		iommus = <&smmu TEGRA186_SID_SDMMC1>;
826		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
827		pinctrl-0 = <&sdmmc1_3v3>;
828		pinctrl-1 = <&sdmmc1_1v8>;
829		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
830		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
831		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
832		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
833		nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
834		nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
835		nvidia,default-tap = <0x5>;
836		nvidia,default-trim = <0xb>;
837		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
838				  <&bpmp TEGRA186_CLK_PLLP_OUT0>;
839		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
840		status = "disabled";
841	};
842
843	sdmmc2: mmc@3420000 {
844		compatible = "nvidia,tegra186-sdhci";
845		reg = <0x0 0x03420000 0x0 0x10000>;
846		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
847		clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
848			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
849		clock-names = "sdhci", "tmclk";
850		resets = <&bpmp TEGRA186_RESET_SDMMC2>;
851		reset-names = "sdhci";
852		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
853				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
854		interconnect-names = "dma-mem", "write";
855		iommus = <&smmu TEGRA186_SID_SDMMC2>;
856		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
857		pinctrl-0 = <&sdmmc2_3v3>;
858		pinctrl-1 = <&sdmmc2_1v8>;
859		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
860		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
861		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
862		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
863		nvidia,default-tap = <0x5>;
864		nvidia,default-trim = <0xb>;
865		status = "disabled";
866	};
867
868	sdmmc3: mmc@3440000 {
869		compatible = "nvidia,tegra186-sdhci";
870		reg = <0x0 0x03440000 0x0 0x10000>;
871		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
872		clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
873			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
874		clock-names = "sdhci", "tmclk";
875		resets = <&bpmp TEGRA186_RESET_SDMMC3>;
876		reset-names = "sdhci";
877		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
878				<&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
879		interconnect-names = "dma-mem", "write";
880		iommus = <&smmu TEGRA186_SID_SDMMC3>;
881		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
882		pinctrl-0 = <&sdmmc3_3v3>;
883		pinctrl-1 = <&sdmmc3_1v8>;
884		nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
885		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
886		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
887		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
888		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
889		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
890		nvidia,default-tap = <0x5>;
891		nvidia,default-trim = <0xb>;
892		status = "disabled";
893	};
894
895	sdmmc4: mmc@3460000 {
896		compatible = "nvidia,tegra186-sdhci";
897		reg = <0x0 0x03460000 0x0 0x10000>;
898		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
899		clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
900			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
901		clock-names = "sdhci", "tmclk";
902		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
903				  <&bpmp TEGRA186_CLK_PLLC4_VCO>;
904		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
905		resets = <&bpmp TEGRA186_RESET_SDMMC4>;
906		reset-names = "sdhci";
907		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
908				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
909		interconnect-names = "dma-mem", "write";
910		iommus = <&smmu TEGRA186_SID_SDMMC4>;
911		nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
912		nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
913		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
914		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
915		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
916		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
917		nvidia,default-tap = <0x9>;
918		nvidia,default-trim = <0x5>;
919		nvidia,dqs-trim = <63>;
920		mmc-hs400-1_8v;
921		supports-cqe;
922		status = "disabled";
923	};
924
925	hda@3510000 {
926		compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
927		reg = <0x0 0x03510000 0x0 0x10000>;
928		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
929		clocks = <&bpmp TEGRA186_CLK_HDA>,
930			 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
931			 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
932		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
933		resets = <&bpmp TEGRA186_RESET_HDA>,
934			 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
935			 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
936		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
937		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
938		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
939				<&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
940		interconnect-names = "dma-mem", "write";
941		iommus = <&smmu TEGRA186_SID_HDA>;
942		status = "disabled";
943	};
944
945	padctl: padctl@3520000 {
946		compatible = "nvidia,tegra186-xusb-padctl";
947		reg = <0x0 0x03520000 0x0 0x1000>,
948		      <0x0 0x03540000 0x0 0x1000>;
949		reg-names = "padctl", "ao";
950		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
951
952		resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
953		reset-names = "padctl";
954
955		status = "disabled";
956
957		pads {
958			usb2 {
959				clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
960				clock-names = "trk";
961				status = "disabled";
962
963				lanes {
964					usb2-0 {
965						status = "disabled";
966						#phy-cells = <0>;
967					};
968
969					usb2-1 {
970						status = "disabled";
971						#phy-cells = <0>;
972					};
973
974					usb2-2 {
975						status = "disabled";
976						#phy-cells = <0>;
977					};
978				};
979			};
980
981			hsic {
982				clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
983				clock-names = "trk";
984				status = "disabled";
985
986				lanes {
987					hsic-0 {
988						status = "disabled";
989						#phy-cells = <0>;
990					};
991				};
992			};
993
994			usb3 {
995				status = "disabled";
996
997				lanes {
998					usb3-0 {
999						status = "disabled";
1000						#phy-cells = <0>;
1001					};
1002
1003					usb3-1 {
1004						status = "disabled";
1005						#phy-cells = <0>;
1006					};
1007
1008					usb3-2 {
1009						status = "disabled";
1010						#phy-cells = <0>;
1011					};
1012				};
1013			};
1014		};
1015
1016		ports {
1017			usb2-0 {
1018				status = "disabled";
1019			};
1020
1021			usb2-1 {
1022				status = "disabled";
1023			};
1024
1025			usb2-2 {
1026				status = "disabled";
1027			};
1028
1029			hsic-0 {
1030				status = "disabled";
1031			};
1032
1033			usb3-0 {
1034				status = "disabled";
1035			};
1036
1037			usb3-1 {
1038				status = "disabled";
1039			};
1040
1041			usb3-2 {
1042				status = "disabled";
1043			};
1044		};
1045	};
1046
1047	usb@3530000 {
1048		compatible = "nvidia,tegra186-xusb";
1049		reg = <0x0 0x03530000 0x0 0x8000>,
1050		      <0x0 0x03538000 0x0 0x1000>;
1051		reg-names = "hcd", "fpci";
1052		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1053			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1054		clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
1055			 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
1056			 <&bpmp TEGRA186_CLK_XUSB_SS>,
1057			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1058			 <&bpmp TEGRA186_CLK_CLK_M>,
1059			 <&bpmp TEGRA186_CLK_XUSB_FS>,
1060			 <&bpmp TEGRA186_CLK_PLLU>,
1061			 <&bpmp TEGRA186_CLK_CLK_M>,
1062			 <&bpmp TEGRA186_CLK_PLLE>;
1063		clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
1064			      "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
1065			      "pll_u_480m", "clk_m", "pll_e";
1066		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1067				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1068		power-domain-names = "xusb_host", "xusb_ss";
1069		interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1070				<&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1071		interconnect-names = "dma-mem", "write";
1072		iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
1073		#address-cells = <1>;
1074		#size-cells = <0>;
1075		status = "disabled";
1076
1077		nvidia,xusb-padctl = <&padctl>;
1078	};
1079
1080	usb@3550000 {
1081		compatible = "nvidia,tegra186-xudc";
1082		reg = <0x0 0x03550000 0x0 0x8000>,
1083		      <0x0 0x03558000 0x0 0x1000>;
1084		reg-names = "base", "fpci";
1085		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1086		clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
1087			 <&bpmp TEGRA186_CLK_XUSB_SS>,
1088			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1089			 <&bpmp TEGRA186_CLK_XUSB_FS>;
1090		clock-names = "dev", "ss", "ss_src", "fs_src";
1091		interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>,
1092				<&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>;
1093		interconnect-names = "dma-mem", "write";
1094		iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
1095		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1096				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1097		power-domain-names = "dev", "ss";
1098		nvidia,xusb-padctl = <&padctl>;
1099		status = "disabled";
1100	};
1101
1102	fuse@3820000 {
1103		compatible = "nvidia,tegra186-efuse";
1104		reg = <0x0 0x03820000 0x0 0x10000>;
1105		clocks = <&bpmp TEGRA186_CLK_FUSE>;
1106		clock-names = "fuse";
1107	};
1108
1109	gic: interrupt-controller@3881000 {
1110		compatible = "arm,gic-400";
1111		#interrupt-cells = <3>;
1112		interrupt-controller;
1113		reg = <0x0 0x03881000 0x0 0x1000>,
1114		      <0x0 0x03882000 0x0 0x2000>,
1115		      <0x0 0x03884000 0x0 0x2000>,
1116		      <0x0 0x03886000 0x0 0x2000>;
1117		interrupts = <GIC_PPI 9
1118			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1119		interrupt-parent = <&gic>;
1120	};
1121
1122	cec@3960000 {
1123		compatible = "nvidia,tegra186-cec";
1124		reg = <0x0 0x03960000 0x0 0x10000>;
1125		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1126		clocks = <&bpmp TEGRA186_CLK_CEC>;
1127		clock-names = "cec";
1128		status = "disabled";
1129	};
1130
1131	hsp_top0: hsp@3c00000 {
1132		compatible = "nvidia,tegra186-hsp";
1133		reg = <0x0 0x03c00000 0x0 0xa0000>;
1134		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1135		interrupt-names = "doorbell";
1136		#mbox-cells = <2>;
1137		status = "disabled";
1138	};
1139
1140	gen2_i2c: i2c@c240000 {
1141		compatible = "nvidia,tegra186-i2c";
1142		reg = <0x0 0x0c240000 0x0 0x10000>;
1143		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1144		#address-cells = <1>;
1145		#size-cells = <0>;
1146		clocks = <&bpmp TEGRA186_CLK_I2C2>;
1147		clock-names = "div-clk";
1148		resets = <&bpmp TEGRA186_RESET_I2C2>;
1149		reset-names = "i2c";
1150		status = "disabled";
1151	};
1152
1153	gen8_i2c: i2c@c250000 {
1154		compatible = "nvidia,tegra186-i2c";
1155		reg = <0x0 0x0c250000 0x0 0x10000>;
1156		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1157		#address-cells = <1>;
1158		#size-cells = <0>;
1159		clocks = <&bpmp TEGRA186_CLK_I2C8>;
1160		clock-names = "div-clk";
1161		resets = <&bpmp TEGRA186_RESET_I2C8>;
1162		reset-names = "i2c";
1163		status = "disabled";
1164	};
1165
1166	uartc: serial@c280000 {
1167		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1168		reg = <0x0 0x0c280000 0x0 0x40>;
1169		reg-shift = <2>;
1170		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1171		clocks = <&bpmp TEGRA186_CLK_UARTC>;
1172		clock-names = "serial";
1173		resets = <&bpmp TEGRA186_RESET_UARTC>;
1174		reset-names = "serial";
1175		status = "disabled";
1176	};
1177
1178	uartg: serial@c290000 {
1179		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1180		reg = <0x0 0x0c290000 0x0 0x40>;
1181		reg-shift = <2>;
1182		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1183		clocks = <&bpmp TEGRA186_CLK_UARTG>;
1184		clock-names = "serial";
1185		resets = <&bpmp TEGRA186_RESET_UARTG>;
1186		reset-names = "serial";
1187		status = "disabled";
1188	};
1189
1190	rtc: rtc@c2a0000 {
1191		compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1192		reg = <0 0x0c2a0000 0 0x10000>;
1193		interrupt-parent = <&pmc>;
1194		interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1195		clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1196		clock-names = "rtc";
1197		status = "disabled";
1198	};
1199
1200	gpio_aon: gpio@c2f0000 {
1201		compatible = "nvidia,tegra186-gpio-aon";
1202		reg-names = "security", "gpio";
1203		reg = <0x0 0xc2f0000 0x0 0x1000>,
1204		      <0x0 0xc2f1000 0x0 0x1000>;
1205		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1206		gpio-controller;
1207		#gpio-cells = <2>;
1208		interrupt-controller;
1209		#interrupt-cells = <2>;
1210	};
1211
1212	pwm4: pwm@c340000 {
1213		compatible = "nvidia,tegra186-pwm";
1214		reg = <0x0 0xc340000 0x0 0x10000>;
1215		clocks = <&bpmp TEGRA186_CLK_PWM4>;
1216		clock-names = "pwm";
1217		resets = <&bpmp TEGRA186_RESET_PWM4>;
1218		reset-names = "pwm";
1219		status = "disabled";
1220		#pwm-cells = <2>;
1221	};
1222
1223	pmc: pmc@c360000 {
1224		compatible = "nvidia,tegra186-pmc";
1225		reg = <0 0x0c360000 0 0x10000>,
1226		      <0 0x0c370000 0 0x10000>,
1227		      <0 0x0c380000 0 0x10000>,
1228		      <0 0x0c390000 0 0x10000>;
1229		reg-names = "pmc", "wake", "aotag", "scratch";
1230
1231		#interrupt-cells = <2>;
1232		interrupt-controller;
1233
1234		sdmmc1_3v3: sdmmc1-3v3 {
1235			pins = "sdmmc1-hv";
1236			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1237		};
1238
1239		sdmmc1_1v8: sdmmc1-1v8 {
1240			pins = "sdmmc1-hv";
1241			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1242		};
1243
1244		sdmmc2_3v3: sdmmc2-3v3 {
1245			pins = "sdmmc2-hv";
1246			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1247		};
1248
1249		sdmmc2_1v8: sdmmc2-1v8 {
1250			pins = "sdmmc2-hv";
1251			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1252		};
1253
1254		sdmmc3_3v3: sdmmc3-3v3 {
1255			pins = "sdmmc3-hv";
1256			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1257		};
1258
1259		sdmmc3_1v8: sdmmc3-1v8 {
1260			pins = "sdmmc3-hv";
1261			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1262		};
1263	};
1264
1265	ccplex@e000000 {
1266		compatible = "nvidia,tegra186-ccplex-cluster";
1267		reg = <0x0 0x0e000000 0x0 0x400000>;
1268
1269		nvidia,bpmp = <&bpmp>;
1270	};
1271
1272	pcie@10003000 {
1273		compatible = "nvidia,tegra186-pcie";
1274		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1275		device_type = "pci";
1276		reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1277		      <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1278		      <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1279		reg-names = "pads", "afi", "cs";
1280
1281		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1282			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1283		interrupt-names = "intr", "msi";
1284
1285		#interrupt-cells = <1>;
1286		interrupt-map-mask = <0 0 0 0>;
1287		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1288
1289		bus-range = <0x00 0xff>;
1290		#address-cells = <3>;
1291		#size-cells = <2>;
1292
1293		ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1294			 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1295			 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1296			 <0x01000000 0 0x0        0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1297			 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1298			 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1299
1300		clocks = <&bpmp TEGRA186_CLK_PCIE>,
1301			 <&bpmp TEGRA186_CLK_AFI>,
1302			 <&bpmp TEGRA186_CLK_PLLE>;
1303		clock-names = "pex", "afi", "pll_e";
1304
1305		resets = <&bpmp TEGRA186_RESET_PCIE>,
1306			 <&bpmp TEGRA186_RESET_AFI>,
1307			 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1308		reset-names = "pex", "afi", "pcie_x";
1309
1310		interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
1311				<&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
1312		interconnect-names = "dma-mem", "write";
1313
1314		iommus = <&smmu TEGRA186_SID_AFI>;
1315		iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1316		iommu-map-mask = <0x0>;
1317
1318		status = "disabled";
1319
1320		pci@1,0 {
1321			device_type = "pci";
1322			assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1323			reg = <0x000800 0 0 0 0>;
1324			status = "disabled";
1325
1326			#address-cells = <3>;
1327			#size-cells = <2>;
1328			ranges;
1329
1330			nvidia,num-lanes = <2>;
1331		};
1332
1333		pci@2,0 {
1334			device_type = "pci";
1335			assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1336			reg = <0x001000 0 0 0 0>;
1337			status = "disabled";
1338
1339			#address-cells = <3>;
1340			#size-cells = <2>;
1341			ranges;
1342
1343			nvidia,num-lanes = <1>;
1344		};
1345
1346		pci@3,0 {
1347			device_type = "pci";
1348			assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1349			reg = <0x001800 0 0 0 0>;
1350			status = "disabled";
1351
1352			#address-cells = <3>;
1353			#size-cells = <2>;
1354			ranges;
1355
1356			nvidia,num-lanes = <1>;
1357		};
1358	};
1359
1360	smmu: iommu@12000000 {
1361		compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
1362		reg = <0 0x12000000 0 0x800000>;
1363		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1364			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1365			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1366			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1367			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1368			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1369			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1370			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1371			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1372			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1373			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1374			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1375			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1376			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1377			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1378			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1379			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1380			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1381			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1382			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1383			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1384			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1385			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1386			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1387			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1388			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1389			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1390			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1391			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1392			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1393			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1394			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1395			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1396			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1397			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1398			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1399			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1400			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1401			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1402			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1403			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1404			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1405			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1406			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1407			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1408			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1409			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1410			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1411			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1412			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1413			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1414			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1415			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1416			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1417			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1418			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1419			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1420			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1421			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1422			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1423			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1424			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1425			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1426			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1427			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1428		stream-match-mask = <0x7f80>;
1429		#global-interrupts = <1>;
1430		#iommu-cells = <1>;
1431
1432		nvidia,memory-controller = <&mc>;
1433	};
1434
1435	host1x@13e00000 {
1436		compatible = "nvidia,tegra186-host1x";
1437		reg = <0x0 0x13e00000 0x0 0x10000>,
1438		      <0x0 0x13e10000 0x0 0x10000>;
1439		reg-names = "hypervisor", "vm";
1440		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1441		             <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1442		interrupt-names = "syncpt", "host1x";
1443		clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1444		clock-names = "host1x";
1445		resets = <&bpmp TEGRA186_RESET_HOST1X>;
1446		reset-names = "host1x";
1447
1448		#address-cells = <1>;
1449		#size-cells = <1>;
1450
1451		ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1452
1453		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
1454		interconnect-names = "dma-mem";
1455
1456		iommus = <&smmu TEGRA186_SID_HOST1X>;
1457
1458		dpaux1: dpaux@15040000 {
1459			compatible = "nvidia,tegra186-dpaux";
1460			reg = <0x15040000 0x10000>;
1461			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1462			clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1463				 <&bpmp TEGRA186_CLK_PLLDP>;
1464			clock-names = "dpaux", "parent";
1465			resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1466			reset-names = "dpaux";
1467			status = "disabled";
1468
1469			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1470
1471			state_dpaux1_aux: pinmux-aux {
1472				groups = "dpaux-io";
1473				function = "aux";
1474			};
1475
1476			state_dpaux1_i2c: pinmux-i2c {
1477				groups = "dpaux-io";
1478				function = "i2c";
1479			};
1480
1481			state_dpaux1_off: pinmux-off {
1482				groups = "dpaux-io";
1483				function = "off";
1484			};
1485
1486			i2c-bus {
1487				#address-cells = <1>;
1488				#size-cells = <0>;
1489			};
1490		};
1491
1492		display-hub@15200000 {
1493			compatible = "nvidia,tegra186-display";
1494			reg = <0x15200000 0x00040000>;
1495			resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1496				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1497				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1498				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1499				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1500				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1501				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1502			reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1503				      "wgrp3", "wgrp4", "wgrp5";
1504			clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1505				 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1506				 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1507			clock-names = "disp", "dsc", "hub";
1508			status = "disabled";
1509
1510			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1511
1512			#address-cells = <1>;
1513			#size-cells = <1>;
1514
1515			ranges = <0x15200000 0x15200000 0x40000>;
1516
1517			display@15200000 {
1518				compatible = "nvidia,tegra186-dc";
1519				reg = <0x15200000 0x10000>;
1520				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1521				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1522				clock-names = "dc";
1523				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1524				reset-names = "dc";
1525
1526				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1527				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1528						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1529				interconnect-names = "dma-mem", "read-1";
1530				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1531
1532				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1533				nvidia,head = <0>;
1534			};
1535
1536			display@15210000 {
1537				compatible = "nvidia,tegra186-dc";
1538				reg = <0x15210000 0x10000>;
1539				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1540				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1541				clock-names = "dc";
1542				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1543				reset-names = "dc";
1544
1545				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1546				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1547						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1548				interconnect-names = "dma-mem", "read-1";
1549				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1550
1551				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1552				nvidia,head = <1>;
1553			};
1554
1555			display@15220000 {
1556				compatible = "nvidia,tegra186-dc";
1557				reg = <0x15220000 0x10000>;
1558				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1559				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1560				clock-names = "dc";
1561				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1562				reset-names = "dc";
1563
1564				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1565				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1566						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1567				interconnect-names = "dma-mem", "read-1";
1568				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1569
1570				nvidia,outputs = <&sor0 &sor1>;
1571				nvidia,head = <2>;
1572			};
1573		};
1574
1575		dsia: dsi@15300000 {
1576			compatible = "nvidia,tegra186-dsi";
1577			reg = <0x15300000 0x10000>;
1578			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1579			clocks = <&bpmp TEGRA186_CLK_DSI>,
1580				 <&bpmp TEGRA186_CLK_DSIA_LP>,
1581				 <&bpmp TEGRA186_CLK_PLLD>;
1582			clock-names = "dsi", "lp", "parent";
1583			resets = <&bpmp TEGRA186_RESET_DSI>;
1584			reset-names = "dsi";
1585			status = "disabled";
1586
1587			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1588		};
1589
1590		vic@15340000 {
1591			compatible = "nvidia,tegra186-vic";
1592			reg = <0x15340000 0x40000>;
1593			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1594			clocks = <&bpmp TEGRA186_CLK_VIC>;
1595			clock-names = "vic";
1596			resets = <&bpmp TEGRA186_RESET_VIC>;
1597			reset-names = "vic";
1598
1599			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1600			interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
1601					<&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
1602			interconnect-names = "dma-mem", "write";
1603			iommus = <&smmu TEGRA186_SID_VIC>;
1604		};
1605
1606		nvjpg@15380000 {
1607			compatible = "nvidia,tegra186-nvjpg";
1608			reg = <0x15380000 0x40000>;
1609			clocks = <&bpmp TEGRA186_CLK_NVJPG>;
1610			clock-names = "nvjpg";
1611			resets = <&bpmp TEGRA186_RESET_NVJPG>;
1612			reset-names = "nvjpg";
1613
1614			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
1615			interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
1616					<&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
1617			interconnect-names = "dma-mem", "write";
1618			iommus = <&smmu TEGRA186_SID_NVJPG>;
1619		};
1620
1621		dsib: dsi@15400000 {
1622			compatible = "nvidia,tegra186-dsi";
1623			reg = <0x15400000 0x10000>;
1624			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1625			clocks = <&bpmp TEGRA186_CLK_DSIB>,
1626				 <&bpmp TEGRA186_CLK_DSIB_LP>,
1627				 <&bpmp TEGRA186_CLK_PLLD>;
1628			clock-names = "dsi", "lp", "parent";
1629			resets = <&bpmp TEGRA186_RESET_DSIB>;
1630			reset-names = "dsi";
1631			status = "disabled";
1632
1633			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1634		};
1635
1636		nvdec@15480000 {
1637			compatible = "nvidia,tegra186-nvdec";
1638			reg = <0x15480000 0x40000>;
1639			clocks = <&bpmp TEGRA186_CLK_NVDEC>;
1640			clock-names = "nvdec";
1641			resets = <&bpmp TEGRA186_RESET_NVDEC>;
1642			reset-names = "nvdec";
1643
1644			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1645			interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
1646					<&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
1647					<&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
1648			interconnect-names = "dma-mem", "read-1", "write";
1649			iommus = <&smmu TEGRA186_SID_NVDEC>;
1650		};
1651
1652		nvenc@154c0000 {
1653			compatible = "nvidia,tegra186-nvenc";
1654			reg = <0x154c0000 0x40000>;
1655			clocks = <&bpmp TEGRA186_CLK_NVENC>;
1656			clock-names = "nvenc";
1657			resets = <&bpmp TEGRA186_RESET_NVENC>;
1658			reset-names = "nvenc";
1659
1660			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
1661			interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
1662					<&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
1663			interconnect-names = "dma-mem", "write";
1664			iommus = <&smmu TEGRA186_SID_NVENC>;
1665		};
1666
1667		sor0: sor@15540000 {
1668			compatible = "nvidia,tegra186-sor";
1669			reg = <0x15540000 0x10000>;
1670			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1671			clocks = <&bpmp TEGRA186_CLK_SOR0>,
1672				 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1673				 <&bpmp TEGRA186_CLK_PLLD2>,
1674				 <&bpmp TEGRA186_CLK_PLLDP>,
1675				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1676				 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1677			clock-names = "sor", "out", "parent", "dp", "safe",
1678				      "pad";
1679			resets = <&bpmp TEGRA186_RESET_SOR0>;
1680			reset-names = "sor";
1681			pinctrl-0 = <&state_dpaux_aux>;
1682			pinctrl-1 = <&state_dpaux_i2c>;
1683			pinctrl-2 = <&state_dpaux_off>;
1684			pinctrl-names = "aux", "i2c", "off";
1685			status = "disabled";
1686
1687			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1688			nvidia,interface = <0>;
1689		};
1690
1691		sor1: sor@15580000 {
1692			compatible = "nvidia,tegra186-sor";
1693			reg = <0x15580000 0x10000>;
1694			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1695			clocks = <&bpmp TEGRA186_CLK_SOR1>,
1696				 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1697				 <&bpmp TEGRA186_CLK_PLLD3>,
1698				 <&bpmp TEGRA186_CLK_PLLDP>,
1699				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1700				 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1701			clock-names = "sor", "out", "parent", "dp", "safe",
1702				      "pad";
1703			resets = <&bpmp TEGRA186_RESET_SOR1>;
1704			reset-names = "sor";
1705			pinctrl-0 = <&state_dpaux1_aux>;
1706			pinctrl-1 = <&state_dpaux1_i2c>;
1707			pinctrl-2 = <&state_dpaux1_off>;
1708			pinctrl-names = "aux", "i2c", "off";
1709			status = "disabled";
1710
1711			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1712			nvidia,interface = <1>;
1713		};
1714
1715		dpaux: dpaux@155c0000 {
1716			compatible = "nvidia,tegra186-dpaux";
1717			reg = <0x155c0000 0x10000>;
1718			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1719			clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1720				 <&bpmp TEGRA186_CLK_PLLDP>;
1721			clock-names = "dpaux", "parent";
1722			resets = <&bpmp TEGRA186_RESET_DPAUX>;
1723			reset-names = "dpaux";
1724			status = "disabled";
1725
1726			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1727
1728			state_dpaux_aux: pinmux-aux {
1729				groups = "dpaux-io";
1730				function = "aux";
1731			};
1732
1733			state_dpaux_i2c: pinmux-i2c {
1734				groups = "dpaux-io";
1735				function = "i2c";
1736			};
1737
1738			state_dpaux_off: pinmux-off {
1739				groups = "dpaux-io";
1740				function = "off";
1741			};
1742
1743			i2c-bus {
1744				#address-cells = <1>;
1745				#size-cells = <0>;
1746			};
1747		};
1748
1749		padctl@15880000 {
1750			compatible = "nvidia,tegra186-dsi-padctl";
1751			reg = <0x15880000 0x10000>;
1752			resets = <&bpmp TEGRA186_RESET_DSI>;
1753			reset-names = "dsi";
1754			status = "disabled";
1755		};
1756
1757		dsic: dsi@15900000 {
1758			compatible = "nvidia,tegra186-dsi";
1759			reg = <0x15900000 0x10000>;
1760			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1761			clocks = <&bpmp TEGRA186_CLK_DSIC>,
1762				 <&bpmp TEGRA186_CLK_DSIC_LP>,
1763				 <&bpmp TEGRA186_CLK_PLLD>;
1764			clock-names = "dsi", "lp", "parent";
1765			resets = <&bpmp TEGRA186_RESET_DSIC>;
1766			reset-names = "dsi";
1767			status = "disabled";
1768
1769			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1770		};
1771
1772		dsid: dsi@15940000 {
1773			compatible = "nvidia,tegra186-dsi";
1774			reg = <0x15940000 0x10000>;
1775			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1776			clocks = <&bpmp TEGRA186_CLK_DSID>,
1777				 <&bpmp TEGRA186_CLK_DSID_LP>,
1778				 <&bpmp TEGRA186_CLK_PLLD>;
1779			clock-names = "dsi", "lp", "parent";
1780			resets = <&bpmp TEGRA186_RESET_DSID>;
1781			reset-names = "dsi";
1782			status = "disabled";
1783
1784			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1785		};
1786	};
1787
1788	gpu@17000000 {
1789		compatible = "nvidia,gp10b";
1790		reg = <0x0 0x17000000 0x0 0x1000000>,
1791		      <0x0 0x18000000 0x0 0x1000000>;
1792		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1793			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1794		interrupt-names = "stall", "nonstall";
1795
1796		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1797			 <&bpmp TEGRA186_CLK_GPU>;
1798		clock-names = "gpu", "pwr";
1799		resets = <&bpmp TEGRA186_RESET_GPU>;
1800		reset-names = "gpu";
1801		status = "disabled";
1802
1803		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1804		interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
1805				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
1806				<&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
1807				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
1808		interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1809	};
1810
1811	sram@30000000 {
1812		compatible = "nvidia,tegra186-sysram", "mmio-sram";
1813		reg = <0x0 0x30000000 0x0 0x50000>;
1814		#address-cells = <1>;
1815		#size-cells = <1>;
1816		ranges = <0x0 0x0 0x30000000 0x50000>;
1817
1818		cpu_bpmp_tx: sram@4e000 {
1819			reg = <0x4e000 0x1000>;
1820			label = "cpu-bpmp-tx";
1821			pool;
1822		};
1823
1824		cpu_bpmp_rx: sram@4f000 {
1825			reg = <0x4f000 0x1000>;
1826			label = "cpu-bpmp-rx";
1827			pool;
1828		};
1829	};
1830
1831	sata@3507000 {
1832		compatible = "nvidia,tegra186-ahci";
1833		reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
1834		      <0x0 0x03500000 0x0 0x00007000>, /* SATA */
1835		      <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
1836		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1837
1838		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
1839		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,
1840				<&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;
1841		interconnect-names = "dma-mem", "write";
1842		iommus = <&smmu TEGRA186_SID_SATA>;
1843
1844		clocks = <&bpmp TEGRA186_CLK_SATA>,
1845			 <&bpmp TEGRA186_CLK_SATA_OOB>;
1846		clock-names = "sata", "sata-oob";
1847		assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
1848				  <&bpmp TEGRA186_CLK_SATA_OOB>;
1849		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
1850					 <&bpmp TEGRA186_CLK_PLLP>;
1851		assigned-clock-rates = <102000000>,
1852				       <204000000>;
1853		resets = <&bpmp TEGRA186_RESET_SATA>,
1854			<&bpmp TEGRA186_RESET_SATACOLD>;
1855		reset-names = "sata", "sata-cold";
1856		status = "disabled";
1857	};
1858
1859	bpmp: bpmp {
1860		compatible = "nvidia,tegra186-bpmp";
1861		interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
1862				<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
1863				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
1864				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
1865		interconnect-names = "read", "write", "dma-mem", "dma-write";
1866		iommus = <&smmu TEGRA186_SID_BPMP>;
1867		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1868				    TEGRA_HSP_DB_MASTER_BPMP>;
1869		shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
1870		#clock-cells = <1>;
1871		#reset-cells = <1>;
1872		#power-domain-cells = <1>;
1873
1874		bpmp_i2c: i2c {
1875			compatible = "nvidia,tegra186-bpmp-i2c";
1876			nvidia,bpmp-bus-id = <5>;
1877			#address-cells = <1>;
1878			#size-cells = <0>;
1879			status = "disabled";
1880		};
1881
1882		bpmp_thermal: thermal {
1883			compatible = "nvidia,tegra186-bpmp-thermal";
1884			#thermal-sensor-cells = <1>;
1885		};
1886	};
1887
1888	cpus {
1889		#address-cells = <1>;
1890		#size-cells = <0>;
1891
1892		denver_0: cpu@0 {
1893			compatible = "nvidia,tegra186-denver";
1894			device_type = "cpu";
1895			i-cache-size = <0x20000>;
1896			i-cache-line-size = <64>;
1897			i-cache-sets = <512>;
1898			d-cache-size = <0x10000>;
1899			d-cache-line-size = <64>;
1900			d-cache-sets = <256>;
1901			next-level-cache = <&L2_DENVER>;
1902			reg = <0x000>;
1903		};
1904
1905		denver_1: cpu@1 {
1906			compatible = "nvidia,tegra186-denver";
1907			device_type = "cpu";
1908			i-cache-size = <0x20000>;
1909			i-cache-line-size = <64>;
1910			i-cache-sets = <512>;
1911			d-cache-size = <0x10000>;
1912			d-cache-line-size = <64>;
1913			d-cache-sets = <256>;
1914			next-level-cache = <&L2_DENVER>;
1915			reg = <0x001>;
1916		};
1917
1918		ca57_0: cpu@2 {
1919			compatible = "arm,cortex-a57";
1920			device_type = "cpu";
1921			i-cache-size = <0xC000>;
1922			i-cache-line-size = <64>;
1923			i-cache-sets = <256>;
1924			d-cache-size = <0x8000>;
1925			d-cache-line-size = <64>;
1926			d-cache-sets = <256>;
1927			next-level-cache = <&L2_A57>;
1928			reg = <0x100>;
1929		};
1930
1931		ca57_1: cpu@3 {
1932			compatible = "arm,cortex-a57";
1933			device_type = "cpu";
1934			i-cache-size = <0xC000>;
1935			i-cache-line-size = <64>;
1936			i-cache-sets = <256>;
1937			d-cache-size = <0x8000>;
1938			d-cache-line-size = <64>;
1939			d-cache-sets = <256>;
1940			next-level-cache = <&L2_A57>;
1941			reg = <0x101>;
1942		};
1943
1944		ca57_2: cpu@4 {
1945			compatible = "arm,cortex-a57";
1946			device_type = "cpu";
1947			i-cache-size = <0xC000>;
1948			i-cache-line-size = <64>;
1949			i-cache-sets = <256>;
1950			d-cache-size = <0x8000>;
1951			d-cache-line-size = <64>;
1952			d-cache-sets = <256>;
1953			next-level-cache = <&L2_A57>;
1954			reg = <0x102>;
1955		};
1956
1957		ca57_3: cpu@5 {
1958			compatible = "arm,cortex-a57";
1959			device_type = "cpu";
1960			i-cache-size = <0xC000>;
1961			i-cache-line-size = <64>;
1962			i-cache-sets = <256>;
1963			d-cache-size = <0x8000>;
1964			d-cache-line-size = <64>;
1965			d-cache-sets = <256>;
1966			next-level-cache = <&L2_A57>;
1967			reg = <0x103>;
1968		};
1969
1970		L2_DENVER: l2-cache0 {
1971			compatible = "cache";
1972			cache-unified;
1973			cache-level = <2>;
1974			cache-size = <0x200000>;
1975			cache-line-size = <64>;
1976			cache-sets = <2048>;
1977		};
1978
1979		L2_A57: l2-cache1 {
1980			compatible = "cache";
1981			cache-unified;
1982			cache-level = <2>;
1983			cache-size = <0x200000>;
1984			cache-line-size = <64>;
1985			cache-sets = <2048>;
1986		};
1987	};
1988
1989	pmu_denver {
1990		compatible = "nvidia,denver-pmu";
1991		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1992			     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1993		interrupt-affinity = <&denver_0 &denver_1>;
1994	};
1995
1996	pmu_a57 {
1997		compatible = "arm,cortex-a57-pmu";
1998		interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1999			     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
2000			     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
2001			     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
2002		interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
2003	};
2004
2005	sound {
2006		status = "disabled";
2007
2008		clocks = <&bpmp TEGRA186_CLK_PLLA>,
2009			 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2010		clock-names = "pll_a", "plla_out0";
2011		assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
2012				  <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
2013				  <&bpmp TEGRA186_CLK_AUD_MCLK>;
2014		assigned-clock-parents = <0>,
2015					 <&bpmp TEGRA186_CLK_PLLA>,
2016					 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2017		/*
2018		 * PLLA supports dynamic ramp. Below initial rate is chosen
2019		 * for this to work and oscillate between base rates required
2020		 * for 8x and 11.025x sample rate streams.
2021		 */
2022		assigned-clock-rates = <258000000>;
2023
2024		iommus = <&smmu TEGRA186_SID_APE>;
2025	};
2026
2027	thermal-zones {
2028		/* Cortex-A57 cluster */
2029		cpu-thermal {
2030			polling-delay = <0>;
2031			polling-delay-passive = <1000>;
2032
2033			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
2034
2035			trips {
2036				critical {
2037					temperature = <101000>;
2038					hysteresis = <0>;
2039					type = "critical";
2040				};
2041			};
2042
2043			cooling-maps {
2044			};
2045		};
2046
2047		/* Denver cluster */
2048		aux-thermal {
2049			polling-delay = <0>;
2050			polling-delay-passive = <1000>;
2051
2052			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
2053
2054			trips {
2055				critical {
2056					temperature = <101000>;
2057					hysteresis = <0>;
2058					type = "critical";
2059				};
2060			};
2061
2062			cooling-maps {
2063			};
2064		};
2065
2066		gpu-thermal {
2067			polling-delay = <0>;
2068			polling-delay-passive = <1000>;
2069
2070			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
2071
2072			trips {
2073				critical {
2074					temperature = <101000>;
2075					hysteresis = <0>;
2076					type = "critical";
2077				};
2078			};
2079
2080			cooling-maps {
2081			};
2082		};
2083
2084		pll-thermal {
2085			polling-delay = <0>;
2086			polling-delay-passive = <1000>;
2087
2088			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
2089
2090			trips {
2091				critical {
2092					temperature = <101000>;
2093					hysteresis = <0>;
2094					type = "critical";
2095				};
2096			};
2097
2098			cooling-maps {
2099			};
2100		};
2101
2102		ao-thermal {
2103			polling-delay = <0>;
2104			polling-delay-passive = <1000>;
2105
2106			thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2107
2108			trips {
2109				critical {
2110					temperature = <101000>;
2111					hysteresis = <0>;
2112					type = "critical";
2113				};
2114			};
2115
2116			cooling-maps {
2117			};
2118		};
2119	};
2120
2121	timer {
2122		compatible = "arm,armv8-timer";
2123		interrupts = <GIC_PPI 13
2124				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2125			     <GIC_PPI 14
2126				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2127			     <GIC_PPI 11
2128				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2129			     <GIC_PPI 10
2130				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2131		interrupt-parent = <&gic>;
2132		always-on;
2133	};
2134};
2135