Revision tags: v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3 |
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#
47cf40af |
| 04-Oct-2019 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: Prepare the introduction of CP115
CP110 and CP115 are almost the same in terms of features and have a very limited set of differences. Let's create an armada-cp11x.dtsi file whi
arm64: dts: marvell: Prepare the introduction of CP115
CP110 and CP115 are almost the same in terms of features and have a very limited set of differences. Let's create an armada-cp11x.dtsi file which will be used to instantiate both CP110 and CP115 nodes.
The only changes between the two armada-cp11{0,x}.dtsi files are the following naming in macros: s/CP110/CP11X/.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
2bc26088 |
| 04-Oct-2019 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment
Fix this tiny typo before renaming/changing this file.
Fixes: 72a3713fadfd ("arm64: dts: marvell: de-duplicate CP110
arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment
Fix this tiny typo before renaming/changing this file.
Fixes: 72a3713fadfd ("arm64: dts: marvell: de-duplicate CP110 description") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6 |
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#
d04abe99 |
| 31-Jul-2019 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k based boards.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.co
arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k based boards.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
93ab25e6 |
| 31-Jul-2019 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: Add CP110 COMPHY clocks
Declare the three clocks feeding the COMPHY block.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clem
arm64: dts: marvell: Add CP110 COMPHY clocks
Declare the three clocks feeding the COMPHY block.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11 |
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#
200f5c40 |
| 17-Jun-2019 |
Russell King <rmk+kernel@armlinux.org.uk> |
arm64: dts: marvell: add missing #interrupt-cells property
The GPIO interrupt controllers are missing their required specified in DT.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Review
arm64: dts: marvell: add missing #interrupt-cells property
The GPIO interrupt controllers are missing their required specified in DT.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9 |
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#
47041b97 |
| 12-Dec-2018 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: add interrupt support to cp110 thermal node
Add interrupt properties in the thermal node as well as a critical trip point in the thermal-zone.
Signed-off-by: Miquel Raynal <miq
arm64: dts: marvell: add interrupt support to cp110 thermal node
Add interrupt properties in the thermal node as well as a critical trip point in the thermal-zone.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12 |
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#
b0e11e58 |
| 03-Oct-2018 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: add CP110 ICU SEI subnode
The ICU handles several interrupt groups, each of them being a subpart of the ICU node.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signe
arm64: dts: marvell: add CP110 ICU SEI subnode
The ICU handles several interrupt groups, each of them being a subpart of the ICU node.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
f21bb56e |
| 03-Oct-2018 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: use new bindings for CP110 interrupts
Create an ICU subnode for the NSR interrupts. This subnode becomes the CP110 interrupt parent, removing the need for the ICU_GRP_NSR parame
arm64: dts: marvell: use new bindings for CP110 interrupts
Create an ICU subnode for the NSR interrupts. This subnode becomes the CP110 interrupt parent, removing the need for the ICU_GRP_NSR parameter. Move all DT110 nodes to use these new bindings.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v4.18.11, v4.18.10 |
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#
dd0da407 |
| 24-Sep-2018 |
Antoine Tenart <antoine.tenart@bootlin.com> |
arm64: dts: marvell: armada-cp110: describe more PPv2 interrupts
This patch describes 3 additional interrupts per PPv2 port. Those interrupts will be used later in future versions of the Marvell PPv
arm64: dts: marvell: armada-cp110: describe more PPv2 interrupts
This patch describes 3 additional interrupts per PPv2 port. Those interrupts will be used later in future versions of the Marvell PPv2 driver, and now the device tree description matches the hardware capabilities.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
eeee84f7 |
| 24-Sep-2018 |
Antoine Tenart <antoine.tenart@bootlin.com> |
arm64: dts: marvell: armada-cp110: change the PPv2 IRQ names
This patch changes the PPv2 IRQ names in the CP110 device tree to match a corresponding change in the Marvell PPv2 driver. The reason thi
arm64: dts: marvell: armada-cp110: change the PPv2 IRQ names
This patch changes the PPv2 IRQ names in the CP110 device tree to match a corresponding change in the Marvell PPv2 driver. The reason this was updated is the IRQ where names after Tx/Rx interrupts, but this is not true and can be configured. A following patch will add more of them and the names wouldn't make sense.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v4.18.9, v4.18.7, v4.18.6 |
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#
f656c801 |
| 30-Aug-2018 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: add thermal-zone node in cp110 DTSI file
Add a thermal-zone node and fill in all the sensors available in a cp110 (only one in the thermal IP).
Signed-off-by: Miquel Raynal <mi
arm64: dts: marvell: add thermal-zone node in cp110 DTSI file
Add a thermal-zone node and fill in all the sensors available in a cp110 (only one in the thermal IP).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
0863e01c |
| 30-Aug-2018 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: move AP806/CP110 thermal nodes into a new syscon
New bindings impose to declare the thermal IP from within a new syscon.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com
arm64: dts: marvell: move AP806/CP110 thermal nodes into a new syscon
New bindings impose to declare the thermal IP from within a new syscon.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4 |
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#
9598918b |
| 28-Jun-2018 |
Antoine Tenart <antoine.tenart@bootlin.com> |
arm64: dts: marvell: armada-cp110: update the crypto engine compatible
New compatibles are now supported by the Inside Secure SafeXcel driver. As they are more specific than the old ones, they shoul
arm64: dts: marvell: armada-cp110: update the crypto engine compatible
New compatibles are now supported by the Inside Secure SafeXcel driver. As they are more specific than the old ones, they should be used whenever possible. This patch updates the Marvell cp110 device tree accordingly.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v4.17.3, v4.17.2, v4.17.1, v4.17 |
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#
2f872ddc |
| 22-May-2018 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: fix CP110 ICU node size
ICU size in CP110 is not 0x10 but at least 0x440 bytes long (from the specification).
Fixes: 6ef84a827c37 ("arm64: dts: marvell: enable GICP and ICU on
arm64: dts: marvell: fix CP110 ICU node size
ICU size in CP110 is not 0x10 but at least 0x440 bytes long (from the specification).
Fixes: 6ef84a827c37 ("arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
f43194c1 |
| 25-Apr-2018 |
Maxime Chevallier <maxime.chevallier@bootlin.com> |
ARM64: dts: marvell: armada-cp110: Add mg_core_clk for ethernet node
Marvell PPv2.2 controller present on CP-110 need the extra "mg_core_clk" clock to avoid system hangs when powering some network i
ARM64: dts: marvell: armada-cp110: Add mg_core_clk for ethernet node
Marvell PPv2.2 controller present on CP-110 need the extra "mg_core_clk" clock to avoid system hangs when powering some network interfaces up.
This issue appeared after a recent clock rework on Armada 7K/8K platforms.
This commit adds the new clock and updates the documentation accordingly.
[gregory.clement: use the real first commit to fix and add the cc:stable flag] Fixes: e3af9f7c6ece ("RM64: dts: marvell: armada-cp110: Fix clock resources for various node") Cc: <stable@vger.kernel.org> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
a0573448 |
| 25-Apr-2018 |
Maxime Chevallier <maxime.chevallier@bootlin.com> |
ARM64: dts: marvell: armada-cp110: Add clocks for the xmdio node
The Marvell XSMI controller needs 3 clocks to operate correctly : - The MG clock (clk 5) - The MG Core clock (clk 6) - The GOP clo
ARM64: dts: marvell: armada-cp110: Add clocks for the xmdio node
The Marvell XSMI controller needs 3 clocks to operate correctly : - The MG clock (clk 5) - The MG Core clock (clk 6) - The GOP clock (clk 18)
This commit adds them, to avoid system hangs when using these interfaces.
[gregory.clement: use the real first commit to fix and add the cc:stable flag] Fixes: f66b2aff46ea ("arm64: dts: marvell: add xmdio nodes for 7k/8k") Cc: <stable@vger.kernel.org> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Revision tags: v4.16 |
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#
02ba4ce6 |
| 31-Mar-2018 |
Mark Kettenis <kettenis@openbsd.org> |
arm64: dts: marvell: mark CP110 ahci as dma-coherent
The hardware is clearly DMA coherent and not marking it as such leads to cache coherency problems, at least with the OpenBSD kernel.
Signed-off-
arm64: dts: marvell: mark CP110 ahci as dma-coherent
The hardware is clearly DMA coherent and not marking it as such leads to cache coherency problems, at least with the OpenBSD kernel.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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b15c9d35 |
| 14-Mar-2018 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe nodes
This extra clock is needed to access the registers of the PCIe host controller used on CP110 component of the Armada 7K/8K S
ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe nodes
This extra clock is needed to access the registers of the PCIe host controller used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as well as in the driver): "PCI: armada8k: Fix clock resource by adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
ef04faf1 |
| 14-Mar-2018 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND node
This extra clock is needed to access the registers of the NAND controller used on CP110 component of the Armada 7K/8K SoCs.
ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND node
This extra clock is needed to access the registers of the NAND controller used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as well as in the driver): "mtd: nand: marvell: Fix clock resource by adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
3c7f7f15 |
| 14-Mar-2018 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto node
This extra clock is needed to access the registers of the safexcel EIP97 used on CP110 component of the Armada 7K/8K SoCs.
ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto node
This extra clock is needed to access the registers of the safexcel EIP97 used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as well as in the driver): "crypto: inside-secure - fix clock resource by adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
cc4d5aed |
| 14-Mar-2018 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
ARM64: dts: marvell: armada-cp110: Add registers clock for the trng node
This extra clock is needed to access the registers of the harware RNG used on CP110 component of the Armada 7K/8K SoCs.
This
ARM64: dts: marvell: armada-cp110: Add registers clock for the trng node
This extra clock is needed to access the registers of the harware RNG used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as well as in the driver): "hwrng: omap - Fix clock resource by adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
f1ebfab9 |
| 14-Mar-2018 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine nodes
This extra clock is needed to access the registers of the XOR engine controller used on CP110 component of the Armada 7K/8
ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine nodes
This extra clock is needed to access the registers of the XOR engine controller used on CP110 component of the Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as well as in the driver): "dmaengine: mv_xor_v2: Fix clock resource by adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
f03ad7f6 |
| 14-Mar-2018 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
ARM64: dts: marvell: armada-cp110: Add registers clock for USB host nodes
This extra clock is needed to access the registers of the USB host controller used on Armada 7K/8K SoCs.
This follow the ch
ARM64: dts: marvell: armada-cp110: Add registers clock for USB host nodes
This extra clock is needed to access the registers of the USB host controller used on Armada 7K/8K SoCs.
This follow the changes already made in the binding documentation (as well as in the driver): "usb: host: xhci-plat: Fix clock resource by adding a register clock"
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
597667d8 |
| 01-Mar-2018 |
Gregory CLEMENT <gregory.clement@bootlin.com> |
ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodes
This extra clock is needed to access the registers of the UARTs used on CP110 component of the Armada 7K/8K SoCs.
Signed-off
ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodes
This extra clock is needed to access the registers of the UARTs used on CP110 component of the Armada 7K/8K SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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#
1e09a73f |
| 19-Feb-2018 |
Miquel Raynal <miquel.raynal@bootlin.com> |
arm64: dts: marvell: use reworked NAND controller driver on Armada 7K
Use the new bindings of the reworked Marvell NAND controller driver. Also adapt the nand controller node organization to disting
arm64: dts: marvell: use reworked NAND controller driver on Armada 7K
Use the new bindings of the reworked Marvell NAND controller driver. Also adapt the nand controller node organization to distinguish which property is relevant for the controller, and which one is NAND chip specific. Expose the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as the driver activates the arbiter by default for all boards (either needed or harmless).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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