1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada CP110.
6 */
7
8#include <dt-bindings/interrupt-controller/mvebu-icu.h>
9
10#include "armada-common.dtsi"
11
12#define CP110_PCIEx_IO_BASE(iface)	(CP110_PCIE_IO_BASE + (iface *  0x10000))
13#define CP110_PCIEx_MEM_BASE(iface)	(CP110_PCIE_MEM_BASE + (iface *  0x1000000))
14#define CP110_PCIEx_CONF_BASE(iface)	(CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
15
16/ {
17	/*
18	 * The contents of the node are defined below, in order to
19	 * save one indentation level
20	 */
21	CP110_NAME: CP110_NAME { };
22};
23
24&CP110_NAME {
25	#address-cells = <2>;
26	#size-cells = <2>;
27	compatible = "simple-bus";
28	interrupt-parent = <&CP110_LABEL(icu)>;
29	ranges;
30
31	config-space@CP110_BASE {
32		#address-cells = <1>;
33		#size-cells = <1>;
34		compatible = "simple-bus";
35		ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
36
37		CP110_LABEL(ethernet): ethernet@0 {
38			compatible = "marvell,armada-7k-pp22";
39			reg = <0x0 0x100000>, <0x129000 0xb000>;
40			clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
41				 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 18>;
42			clock-names = "pp_clk", "gop_clk",
43				      "mg_clk", "axi_clk";
44			marvell,system-controller = <&CP110_LABEL(syscon0)>;
45			status = "disabled";
46			dma-coherent;
47
48			CP110_LABEL(eth0): eth0 {
49				interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
50					<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
51					<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
52					<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
53					<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
54					<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
55				interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
56					"tx-cpu3", "rx-shared", "link";
57				port-id = <0>;
58				gop-port-id = <0>;
59				status = "disabled";
60			};
61
62			CP110_LABEL(eth1): eth1 {
63				interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
64					<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
65					<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
66					<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
67					<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
68					<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
69				interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
70					"tx-cpu3", "rx-shared", "link";
71				port-id = <1>;
72				gop-port-id = <2>;
73				status = "disabled";
74			};
75
76			CP110_LABEL(eth2): eth2 {
77				interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
78					<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
79					<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
80					<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
81					<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
82					<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
83				interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
84					"tx-cpu3", "rx-shared", "link";
85				port-id = <2>;
86				gop-port-id = <3>;
87				status = "disabled";
88			};
89		};
90
91		CP110_LABEL(comphy): phy@120000 {
92			compatible = "marvell,comphy-cp110";
93			reg = <0x120000 0x6000>;
94			marvell,system-controller = <&CP110_LABEL(syscon0)>;
95			#address-cells = <1>;
96			#size-cells = <0>;
97
98			CP110_LABEL(comphy0): phy@0 {
99				reg = <0>;
100				#phy-cells = <1>;
101			};
102
103			CP110_LABEL(comphy1): phy@1 {
104				reg = <1>;
105				#phy-cells = <1>;
106			};
107
108			CP110_LABEL(comphy2): phy@2 {
109				reg = <2>;
110				#phy-cells = <1>;
111			};
112
113			CP110_LABEL(comphy3): phy@3 {
114				reg = <3>;
115				#phy-cells = <1>;
116			};
117
118			CP110_LABEL(comphy4): phy@4 {
119				reg = <4>;
120				#phy-cells = <1>;
121			};
122
123			CP110_LABEL(comphy5): phy@5 {
124				reg = <5>;
125				#phy-cells = <1>;
126			};
127		};
128
129		CP110_LABEL(mdio): mdio@12a200 {
130			#address-cells = <1>;
131			#size-cells = <0>;
132			compatible = "marvell,orion-mdio";
133			reg = <0x12a200 0x10>;
134			clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
135				 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
136			status = "disabled";
137		};
138
139		CP110_LABEL(xmdio): mdio@12a600 {
140			#address-cells = <1>;
141			#size-cells = <0>;
142			compatible = "marvell,xmdio";
143			reg = <0x12a600 0x10>;
144			status = "disabled";
145		};
146
147		CP110_LABEL(icu): interrupt-controller@1e0000 {
148			compatible = "marvell,cp110-icu";
149			reg = <0x1e0000 0x10>;
150			#interrupt-cells = <3>;
151			interrupt-controller;
152			msi-parent = <&gicp>;
153		};
154
155		CP110_LABEL(rtc): rtc@284000 {
156			compatible = "marvell,armada-8k-rtc";
157			reg = <0x284000 0x20>, <0x284080 0x24>;
158			reg-names = "rtc", "rtc-soc";
159			interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
160		};
161
162		CP110_LABEL(thermal): thermal@400078 {
163			compatible = "marvell,armada-cp110-thermal";
164			reg = <0x400078 0x4>,
165			<0x400070 0x8>;
166		};
167
168		CP110_LABEL(syscon0): system-controller@440000 {
169			compatible = "syscon", "simple-mfd";
170			reg = <0x440000 0x2000>;
171
172			CP110_LABEL(clk): clock {
173				compatible = "marvell,cp110-clock";
174				#clock-cells = <2>;
175			};
176
177			CP110_LABEL(gpio1): gpio@100 {
178				compatible = "marvell,armada-8k-gpio";
179				offset = <0x100>;
180				ngpios = <32>;
181				gpio-controller;
182				#gpio-cells = <2>;
183				gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
184				interrupt-controller;
185				interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
186					<ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
187					<ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
188					<ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
189				status = "disabled";
190			};
191
192			CP110_LABEL(gpio2): gpio@140 {
193				compatible = "marvell,armada-8k-gpio";
194				offset = <0x140>;
195				ngpios = <31>;
196				gpio-controller;
197				#gpio-cells = <2>;
198				gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
199				interrupt-controller;
200				interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
201					<ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
202					<ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
203					<ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
204				status = "disabled";
205			};
206		};
207
208		CP110_LABEL(usb3_0): usb3@500000 {
209			compatible = "marvell,armada-8k-xhci",
210			"generic-xhci";
211			reg = <0x500000 0x4000>;
212			dma-coherent;
213			interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
214			clock-names = "core", "reg";
215			clocks = <&CP110_LABEL(clk) 1 22>,
216				 <&CP110_LABEL(clk) 1 16>;
217			status = "disabled";
218		};
219
220		CP110_LABEL(usb3_1): usb3@510000 {
221			compatible = "marvell,armada-8k-xhci",
222			"generic-xhci";
223			reg = <0x510000 0x4000>;
224			dma-coherent;
225			interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
226			clock-names = "core", "reg";
227			clocks = <&CP110_LABEL(clk) 1 23>,
228				 <&CP110_LABEL(clk) 1 16>;
229			status = "disabled";
230		};
231
232		CP110_LABEL(sata0): sata@540000 {
233			compatible = "marvell,armada-8k-ahci",
234			"generic-ahci";
235			reg = <0x540000 0x30000>;
236			interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
237			clocks = <&CP110_LABEL(clk) 1 15>,
238				 <&CP110_LABEL(clk) 1 16>;
239			status = "disabled";
240		};
241
242		CP110_LABEL(xor0): xor@6a0000 {
243			compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
244			reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
245			dma-coherent;
246			msi-parent = <&gic_v2m0>;
247			clock-names = "core", "reg";
248			clocks = <&CP110_LABEL(clk) 1 8>,
249				 <&CP110_LABEL(clk) 1 14>;
250		};
251
252		CP110_LABEL(xor1): xor@6c0000 {
253			compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
254			reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
255			dma-coherent;
256			msi-parent = <&gic_v2m0>;
257			clock-names = "core", "reg";
258			clocks = <&CP110_LABEL(clk) 1 7>,
259				 <&CP110_LABEL(clk) 1 14>;
260		};
261
262		CP110_LABEL(spi0): spi@700600 {
263			compatible = "marvell,armada-380-spi";
264			reg = <0x700600 0x50>;
265			#address-cells = <0x1>;
266			#size-cells = <0x0>;
267			clock-names = "core", "axi";
268			clocks = <&CP110_LABEL(clk) 1 21>,
269				 <&CP110_LABEL(clk) 1 17>;
270			status = "disabled";
271		};
272
273		CP110_LABEL(spi1): spi@700680 {
274			compatible = "marvell,armada-380-spi";
275			reg = <0x700680 0x50>;
276			#address-cells = <1>;
277			#size-cells = <0>;
278			clock-names = "core", "axi";
279			clocks = <&CP110_LABEL(clk) 1 21>,
280				 <&CP110_LABEL(clk) 1 17>;
281			status = "disabled";
282		};
283
284		CP110_LABEL(i2c0): i2c@701000 {
285			compatible = "marvell,mv78230-i2c";
286			reg = <0x701000 0x20>;
287			#address-cells = <1>;
288			#size-cells = <0>;
289			interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
290			clock-names = "core", "reg";
291			clocks = <&CP110_LABEL(clk) 1 21>,
292				 <&CP110_LABEL(clk) 1 17>;
293			status = "disabled";
294		};
295
296		CP110_LABEL(i2c1): i2c@701100 {
297			compatible = "marvell,mv78230-i2c";
298			reg = <0x701100 0x20>;
299			#address-cells = <1>;
300			#size-cells = <0>;
301			interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
302			clock-names = "core", "reg";
303			clocks = <&CP110_LABEL(clk) 1 21>,
304				 <&CP110_LABEL(clk) 1 17>;
305			status = "disabled";
306		};
307
308		CP110_LABEL(uart0): serial@702000 {
309			compatible = "snps,dw-apb-uart";
310			reg = <0x702000 0x100>;
311			reg-shift = <2>;
312			interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
313			reg-io-width = <1>;
314			clock-names = "baudclk", "apb_pclk";
315			clocks = <&CP110_LABEL(clk) 1 21>,
316				 <&CP110_LABEL(clk) 1 17>;
317			status = "disabled";
318		};
319
320		CP110_LABEL(uart1): serial@702100 {
321			compatible = "snps,dw-apb-uart";
322			reg = <0x702100 0x100>;
323			reg-shift = <2>;
324			interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
325			reg-io-width = <1>;
326			clock-names = "baudclk", "apb_pclk";
327			clocks = <&CP110_LABEL(clk) 1 21>,
328				 <&CP110_LABEL(clk) 1 17>;
329			status = "disabled";
330		};
331
332		CP110_LABEL(uart2): serial@702200 {
333			compatible = "snps,dw-apb-uart";
334			reg = <0x702200 0x100>;
335			reg-shift = <2>;
336			interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
337			reg-io-width = <1>;
338			clock-names = "baudclk", "apb_pclk";
339			clocks = <&CP110_LABEL(clk) 1 21>,
340				 <&CP110_LABEL(clk) 1 17>;
341			status = "disabled";
342		};
343
344		CP110_LABEL(uart3): serial@702300 {
345			compatible = "snps,dw-apb-uart";
346			reg = <0x702300 0x100>;
347			reg-shift = <2>;
348			interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
349			reg-io-width = <1>;
350			clock-names = "baudclk", "apb_pclk";
351			clocks = <&CP110_LABEL(clk) 1 21>,
352				 <&CP110_LABEL(clk) 1 17>;
353			status = "disabled";
354		};
355
356		CP110_LABEL(nand_controller): nand@720000 {
357			/*
358			* Due to the limitation of the pins available
359			* this controller is only usable on the CPM
360			* for A7K and on the CPS for A8K.
361			*/
362			compatible = "marvell,armada-8k-nand-controller",
363				"marvell,armada370-nand-controller";
364			reg = <0x720000 0x54>;
365			#address-cells = <1>;
366			#size-cells = <0>;
367			interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
368			clock-names = "core", "reg";
369			clocks = <&CP110_LABEL(clk) 1 2>,
370				 <&CP110_LABEL(clk) 1 17>;
371			marvell,system-controller = <&CP110_LABEL(syscon0)>;
372			status = "disabled";
373		};
374
375		CP110_LABEL(trng): trng@760000 {
376			compatible = "marvell,armada-8k-rng",
377			"inside-secure,safexcel-eip76";
378			reg = <0x760000 0x7d>;
379			interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
380			clock-names = "core", "reg";
381			clocks = <&CP110_LABEL(clk) 1 25>,
382				 <&CP110_LABEL(clk) 1 17>;
383			status = "okay";
384		};
385
386		CP110_LABEL(sdhci0): sdhci@780000 {
387			compatible = "marvell,armada-cp110-sdhci";
388			reg = <0x780000 0x300>;
389			interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
390			clock-names = "core", "axi";
391			clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
392			dma-coherent;
393			status = "disabled";
394		};
395
396		CP110_LABEL(crypto): crypto@800000 {
397			compatible = "inside-secure,safexcel-eip197";
398			reg = <0x800000 0x200000>;
399			interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
400				<ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
401				<ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
402				<ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
403				<ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
404				<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
405			interrupt-names = "mem", "ring0", "ring1",
406				"ring2", "ring3", "eip";
407			clock-names = "core", "reg";
408			clocks = <&CP110_LABEL(clk) 1 26>,
409				 <&CP110_LABEL(clk) 1 17>;
410			dma-coherent;
411		};
412	};
413
414	CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
415		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
416		reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
417		      <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
418		reg-names = "ctrl", "config";
419		#address-cells = <3>;
420		#size-cells = <2>;
421		#interrupt-cells = <1>;
422		device_type = "pci";
423		dma-coherent;
424		msi-parent = <&gic_v2m0>;
425
426		bus-range = <0 0xff>;
427		ranges =
428		/* downstream I/O */
429		<0x81000000 0 CP110_PCIEx_IO_BASE(0) 0  CP110_PCIEx_IO_BASE(0) 0 0x10000
430		/* non-prefetchable memory */
431		0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0  CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
432		interrupt-map-mask = <0 0 0 0>;
433		interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
434		interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
435		num-lanes = <1>;
436		clock-names = "core", "reg";
437		clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
438		status = "disabled";
439	};
440
441	CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
442		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
443		reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
444		      <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
445		reg-names = "ctrl", "config";
446		#address-cells = <3>;
447		#size-cells = <2>;
448		#interrupt-cells = <1>;
449		device_type = "pci";
450		dma-coherent;
451		msi-parent = <&gic_v2m0>;
452
453		bus-range = <0 0xff>;
454		ranges =
455		/* downstream I/O */
456		<0x81000000 0 CP110_PCIEx_IO_BASE(1) 0  CP110_PCIEx_IO_BASE(1) 0 0x10000
457		/* non-prefetchable memory */
458		0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0  CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
459		interrupt-map-mask = <0 0 0 0>;
460		interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
461		interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
462
463		num-lanes = <1>;
464		clock-names = "core", "reg";
465		clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
466		status = "disabled";
467	};
468
469	CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
470		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
471		reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
472		      <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
473		reg-names = "ctrl", "config";
474		#address-cells = <3>;
475		#size-cells = <2>;
476		#interrupt-cells = <1>;
477		device_type = "pci";
478		dma-coherent;
479		msi-parent = <&gic_v2m0>;
480
481		bus-range = <0 0xff>;
482		ranges =
483		/* downstream I/O */
484		<0x81000000 0 CP110_PCIEx_IO_BASE(2) 0  CP110_PCIEx_IO_BASE(2) 0 0x10000
485		/* non-prefetchable memory */
486		0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0  CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
487		interrupt-map-mask = <0 0 0 0>;
488		interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
489		interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
490
491		num-lanes = <1>;
492		clock-names = "core", "reg";
493		clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
494		status = "disabled";
495	};
496};
497