1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada CP110. 6 */ 7 8#include <dt-bindings/interrupt-controller/mvebu-icu.h> 9#include <dt-bindings/thermal/thermal.h> 10 11#include "armada-common.dtsi" 12 13#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000)) 14#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000)) 15#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000) 16 17/ { 18 /* 19 * The contents of the node are defined below, in order to 20 * save one indentation level 21 */ 22 CP110_NAME: CP110_NAME { }; 23 24 /* 25 * CPs only have one sensor in the thermal IC. 26 * 27 * The cooling maps are empty as there are no cooling devices. 28 */ 29 thermal-zones { 30 CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) { 31 polling-delay-passive = <1000>; 32 polling-delay = <1000>; 33 34 thermal-sensors = <&CP110_LABEL(thermal) 0>; 35 36 trips { }; 37 cooling-maps { }; 38 }; 39 }; 40}; 41 42&CP110_NAME { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 compatible = "simple-bus"; 46 interrupt-parent = <&CP110_LABEL(icu_nsr)>; 47 ranges; 48 49 config-space@CP110_BASE { 50 #address-cells = <1>; 51 #size-cells = <1>; 52 compatible = "simple-bus"; 53 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; 54 55 CP110_LABEL(ethernet): ethernet@0 { 56 compatible = "marvell,armada-7k-pp22"; 57 reg = <0x0 0x100000>, <0x129000 0xb000>; 58 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>, 59 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>, 60 <&CP110_LABEL(clk) 1 18>; 61 clock-names = "pp_clk", "gop_clk", 62 "mg_clk", "mg_core_clk", "axi_clk"; 63 marvell,system-controller = <&CP110_LABEL(syscon0)>; 64 status = "disabled"; 65 dma-coherent; 66 67 CP110_LABEL(eth0): eth0 { 68 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>, 69 <43 IRQ_TYPE_LEVEL_HIGH>, 70 <47 IRQ_TYPE_LEVEL_HIGH>, 71 <51 IRQ_TYPE_LEVEL_HIGH>, 72 <55 IRQ_TYPE_LEVEL_HIGH>, 73 <59 IRQ_TYPE_LEVEL_HIGH>, 74 <63 IRQ_TYPE_LEVEL_HIGH>, 75 <67 IRQ_TYPE_LEVEL_HIGH>, 76 <71 IRQ_TYPE_LEVEL_HIGH>, 77 <129 IRQ_TYPE_LEVEL_HIGH>; 78 interrupt-names = "hif0", "hif1", "hif2", 79 "hif3", "hif4", "hif5", "hif6", "hif7", 80 "hif8", "link"; 81 port-id = <0>; 82 gop-port-id = <0>; 83 status = "disabled"; 84 }; 85 86 CP110_LABEL(eth1): eth1 { 87 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>, 88 <44 IRQ_TYPE_LEVEL_HIGH>, 89 <48 IRQ_TYPE_LEVEL_HIGH>, 90 <52 IRQ_TYPE_LEVEL_HIGH>, 91 <56 IRQ_TYPE_LEVEL_HIGH>, 92 <60 IRQ_TYPE_LEVEL_HIGH>, 93 <64 IRQ_TYPE_LEVEL_HIGH>, 94 <68 IRQ_TYPE_LEVEL_HIGH>, 95 <72 IRQ_TYPE_LEVEL_HIGH>, 96 <128 IRQ_TYPE_LEVEL_HIGH>; 97 interrupt-names = "hif0", "hif1", "hif2", 98 "hif3", "hif4", "hif5", "hif6", "hif7", 99 "hif8", "link"; 100 port-id = <1>; 101 gop-port-id = <2>; 102 status = "disabled"; 103 }; 104 105 CP110_LABEL(eth2): eth2 { 106 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>, 107 <45 IRQ_TYPE_LEVEL_HIGH>, 108 <49 IRQ_TYPE_LEVEL_HIGH>, 109 <53 IRQ_TYPE_LEVEL_HIGH>, 110 <57 IRQ_TYPE_LEVEL_HIGH>, 111 <61 IRQ_TYPE_LEVEL_HIGH>, 112 <65 IRQ_TYPE_LEVEL_HIGH>, 113 <69 IRQ_TYPE_LEVEL_HIGH>, 114 <73 IRQ_TYPE_LEVEL_HIGH>, 115 <127 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-names = "hif0", "hif1", "hif2", 117 "hif3", "hif4", "hif5", "hif6", "hif7", 118 "hif8", "link"; 119 port-id = <2>; 120 gop-port-id = <3>; 121 status = "disabled"; 122 }; 123 }; 124 125 CP110_LABEL(comphy): phy@120000 { 126 compatible = "marvell,comphy-cp110"; 127 reg = <0x120000 0x6000>; 128 marvell,system-controller = <&CP110_LABEL(syscon0)>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 132 CP110_LABEL(comphy0): phy@0 { 133 reg = <0>; 134 #phy-cells = <1>; 135 }; 136 137 CP110_LABEL(comphy1): phy@1 { 138 reg = <1>; 139 #phy-cells = <1>; 140 }; 141 142 CP110_LABEL(comphy2): phy@2 { 143 reg = <2>; 144 #phy-cells = <1>; 145 }; 146 147 CP110_LABEL(comphy3): phy@3 { 148 reg = <3>; 149 #phy-cells = <1>; 150 }; 151 152 CP110_LABEL(comphy4): phy@4 { 153 reg = <4>; 154 #phy-cells = <1>; 155 }; 156 157 CP110_LABEL(comphy5): phy@5 { 158 reg = <5>; 159 #phy-cells = <1>; 160 }; 161 }; 162 163 CP110_LABEL(mdio): mdio@12a200 { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 compatible = "marvell,orion-mdio"; 167 reg = <0x12a200 0x10>; 168 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>, 169 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 170 status = "disabled"; 171 }; 172 173 CP110_LABEL(xmdio): mdio@12a600 { 174 #address-cells = <1>; 175 #size-cells = <0>; 176 compatible = "marvell,xmdio"; 177 reg = <0x12a600 0x10>; 178 clocks = <&CP110_LABEL(clk) 1 5>, 179 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 180 status = "disabled"; 181 }; 182 183 CP110_LABEL(icu): interrupt-controller@1e0000 { 184 compatible = "marvell,cp110-icu"; 185 reg = <0x1e0000 0x440>; 186 #address-cells = <1>; 187 #size-cells = <1>; 188 189 CP110_LABEL(icu_nsr): interrupt-controller@10 { 190 compatible = "marvell,cp110-icu-nsr"; 191 reg = <0x10 0x20>; 192 #interrupt-cells = <2>; 193 interrupt-controller; 194 msi-parent = <&gicp>; 195 }; 196 }; 197 198 CP110_LABEL(rtc): rtc@284000 { 199 compatible = "marvell,armada-8k-rtc"; 200 reg = <0x284000 0x20>, <0x284080 0x24>; 201 reg-names = "rtc", "rtc-soc"; 202 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; 203 }; 204 205 CP110_LABEL(syscon0): system-controller@440000 { 206 compatible = "syscon", "simple-mfd"; 207 reg = <0x440000 0x2000>; 208 209 CP110_LABEL(clk): clock { 210 compatible = "marvell,cp110-clock"; 211 #clock-cells = <2>; 212 }; 213 214 CP110_LABEL(gpio1): gpio@100 { 215 compatible = "marvell,armada-8k-gpio"; 216 offset = <0x100>; 217 ngpios = <32>; 218 gpio-controller; 219 #gpio-cells = <2>; 220 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; 221 interrupt-controller; 222 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, 223 <85 IRQ_TYPE_LEVEL_HIGH>, 224 <84 IRQ_TYPE_LEVEL_HIGH>, 225 <83 IRQ_TYPE_LEVEL_HIGH>; 226 status = "disabled"; 227 }; 228 229 CP110_LABEL(gpio2): gpio@140 { 230 compatible = "marvell,armada-8k-gpio"; 231 offset = <0x140>; 232 ngpios = <31>; 233 gpio-controller; 234 #gpio-cells = <2>; 235 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>; 236 interrupt-controller; 237 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, 238 <81 IRQ_TYPE_LEVEL_HIGH>, 239 <80 IRQ_TYPE_LEVEL_HIGH>, 240 <79 IRQ_TYPE_LEVEL_HIGH>; 241 status = "disabled"; 242 }; 243 }; 244 245 CP110_LABEL(syscon1): system-controller@400000 { 246 compatible = "syscon", "simple-mfd"; 247 reg = <0x400000 0x1000>; 248 #address-cells = <1>; 249 #size-cells = <1>; 250 251 CP110_LABEL(thermal): thermal-sensor@70 { 252 compatible = "marvell,armada-cp110-thermal"; 253 reg = <0x70 0x10>; 254 #thermal-sensor-cells = <1>; 255 }; 256 }; 257 258 CP110_LABEL(usb3_0): usb3@500000 { 259 compatible = "marvell,armada-8k-xhci", 260 "generic-xhci"; 261 reg = <0x500000 0x4000>; 262 dma-coherent; 263 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; 264 clock-names = "core", "reg"; 265 clocks = <&CP110_LABEL(clk) 1 22>, 266 <&CP110_LABEL(clk) 1 16>; 267 status = "disabled"; 268 }; 269 270 CP110_LABEL(usb3_1): usb3@510000 { 271 compatible = "marvell,armada-8k-xhci", 272 "generic-xhci"; 273 reg = <0x510000 0x4000>; 274 dma-coherent; 275 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; 276 clock-names = "core", "reg"; 277 clocks = <&CP110_LABEL(clk) 1 23>, 278 <&CP110_LABEL(clk) 1 16>; 279 status = "disabled"; 280 }; 281 282 CP110_LABEL(sata0): sata@540000 { 283 compatible = "marvell,armada-8k-ahci", 284 "generic-ahci"; 285 reg = <0x540000 0x30000>; 286 dma-coherent; 287 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&CP110_LABEL(clk) 1 15>, 289 <&CP110_LABEL(clk) 1 16>; 290 status = "disabled"; 291 }; 292 293 CP110_LABEL(xor0): xor@6a0000 { 294 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 295 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; 296 dma-coherent; 297 msi-parent = <&gic_v2m0>; 298 clock-names = "core", "reg"; 299 clocks = <&CP110_LABEL(clk) 1 8>, 300 <&CP110_LABEL(clk) 1 14>; 301 }; 302 303 CP110_LABEL(xor1): xor@6c0000 { 304 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 305 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; 306 dma-coherent; 307 msi-parent = <&gic_v2m0>; 308 clock-names = "core", "reg"; 309 clocks = <&CP110_LABEL(clk) 1 7>, 310 <&CP110_LABEL(clk) 1 14>; 311 }; 312 313 CP110_LABEL(spi0): spi@700600 { 314 compatible = "marvell,armada-380-spi"; 315 reg = <0x700600 0x50>; 316 #address-cells = <0x1>; 317 #size-cells = <0x0>; 318 clock-names = "core", "axi"; 319 clocks = <&CP110_LABEL(clk) 1 21>, 320 <&CP110_LABEL(clk) 1 17>; 321 status = "disabled"; 322 }; 323 324 CP110_LABEL(spi1): spi@700680 { 325 compatible = "marvell,armada-380-spi"; 326 reg = <0x700680 0x50>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 clock-names = "core", "axi"; 330 clocks = <&CP110_LABEL(clk) 1 21>, 331 <&CP110_LABEL(clk) 1 17>; 332 status = "disabled"; 333 }; 334 335 CP110_LABEL(i2c0): i2c@701000 { 336 compatible = "marvell,mv78230-i2c"; 337 reg = <0x701000 0x20>; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>; 341 clock-names = "core", "reg"; 342 clocks = <&CP110_LABEL(clk) 1 21>, 343 <&CP110_LABEL(clk) 1 17>; 344 status = "disabled"; 345 }; 346 347 CP110_LABEL(i2c1): i2c@701100 { 348 compatible = "marvell,mv78230-i2c"; 349 reg = <0x701100 0x20>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>; 353 clock-names = "core", "reg"; 354 clocks = <&CP110_LABEL(clk) 1 21>, 355 <&CP110_LABEL(clk) 1 17>; 356 status = "disabled"; 357 }; 358 359 CP110_LABEL(uart0): serial@702000 { 360 compatible = "snps,dw-apb-uart"; 361 reg = <0x702000 0x100>; 362 reg-shift = <2>; 363 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>; 364 reg-io-width = <1>; 365 clock-names = "baudclk", "apb_pclk"; 366 clocks = <&CP110_LABEL(clk) 1 21>, 367 <&CP110_LABEL(clk) 1 17>; 368 status = "disabled"; 369 }; 370 371 CP110_LABEL(uart1): serial@702100 { 372 compatible = "snps,dw-apb-uart"; 373 reg = <0x702100 0x100>; 374 reg-shift = <2>; 375 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; 376 reg-io-width = <1>; 377 clock-names = "baudclk", "apb_pclk"; 378 clocks = <&CP110_LABEL(clk) 1 21>, 379 <&CP110_LABEL(clk) 1 17>; 380 status = "disabled"; 381 }; 382 383 CP110_LABEL(uart2): serial@702200 { 384 compatible = "snps,dw-apb-uart"; 385 reg = <0x702200 0x100>; 386 reg-shift = <2>; 387 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>; 388 reg-io-width = <1>; 389 clock-names = "baudclk", "apb_pclk"; 390 clocks = <&CP110_LABEL(clk) 1 21>, 391 <&CP110_LABEL(clk) 1 17>; 392 status = "disabled"; 393 }; 394 395 CP110_LABEL(uart3): serial@702300 { 396 compatible = "snps,dw-apb-uart"; 397 reg = <0x702300 0x100>; 398 reg-shift = <2>; 399 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; 400 reg-io-width = <1>; 401 clock-names = "baudclk", "apb_pclk"; 402 clocks = <&CP110_LABEL(clk) 1 21>, 403 <&CP110_LABEL(clk) 1 17>; 404 status = "disabled"; 405 }; 406 407 CP110_LABEL(nand_controller): nand@720000 { 408 /* 409 * Due to the limitation of the pins available 410 * this controller is only usable on the CPM 411 * for A7K and on the CPS for A8K. 412 */ 413 compatible = "marvell,armada-8k-nand-controller", 414 "marvell,armada370-nand-controller"; 415 reg = <0x720000 0x54>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; 419 clock-names = "core", "reg"; 420 clocks = <&CP110_LABEL(clk) 1 2>, 421 <&CP110_LABEL(clk) 1 17>; 422 marvell,system-controller = <&CP110_LABEL(syscon0)>; 423 status = "disabled"; 424 }; 425 426 CP110_LABEL(trng): trng@760000 { 427 compatible = "marvell,armada-8k-rng", 428 "inside-secure,safexcel-eip76"; 429 reg = <0x760000 0x7d>; 430 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; 431 clock-names = "core", "reg"; 432 clocks = <&CP110_LABEL(clk) 1 25>, 433 <&CP110_LABEL(clk) 1 17>; 434 status = "okay"; 435 }; 436 437 CP110_LABEL(sdhci0): sdhci@780000 { 438 compatible = "marvell,armada-cp110-sdhci"; 439 reg = <0x780000 0x300>; 440 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 441 clock-names = "core", "axi"; 442 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>; 443 dma-coherent; 444 status = "disabled"; 445 }; 446 447 CP110_LABEL(crypto): crypto@800000 { 448 compatible = "inside-secure,safexcel-eip197b"; 449 reg = <0x800000 0x200000>; 450 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>, 451 <88 IRQ_TYPE_LEVEL_HIGH>, 452 <89 IRQ_TYPE_LEVEL_HIGH>, 453 <90 IRQ_TYPE_LEVEL_HIGH>, 454 <91 IRQ_TYPE_LEVEL_HIGH>, 455 <92 IRQ_TYPE_LEVEL_HIGH>; 456 interrupt-names = "mem", "ring0", "ring1", 457 "ring2", "ring3", "eip"; 458 clock-names = "core", "reg"; 459 clocks = <&CP110_LABEL(clk) 1 26>, 460 <&CP110_LABEL(clk) 1 17>; 461 dma-coherent; 462 }; 463 }; 464 465 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { 466 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 467 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, 468 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; 469 reg-names = "ctrl", "config"; 470 #address-cells = <3>; 471 #size-cells = <2>; 472 #interrupt-cells = <1>; 473 device_type = "pci"; 474 dma-coherent; 475 msi-parent = <&gic_v2m0>; 476 477 bus-range = <0 0xff>; 478 ranges = 479 /* downstream I/O */ 480 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000 481 /* non-prefetchable memory */ 482 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>; 483 interrupt-map-mask = <0 0 0 0>; 484 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>; 485 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 486 num-lanes = <1>; 487 clock-names = "core", "reg"; 488 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>; 489 status = "disabled"; 490 }; 491 492 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { 493 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 494 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, 495 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; 496 reg-names = "ctrl", "config"; 497 #address-cells = <3>; 498 #size-cells = <2>; 499 #interrupt-cells = <1>; 500 device_type = "pci"; 501 dma-coherent; 502 msi-parent = <&gic_v2m0>; 503 504 bus-range = <0 0xff>; 505 ranges = 506 /* downstream I/O */ 507 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000 508 /* non-prefetchable memory */ 509 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>; 510 interrupt-map-mask = <0 0 0 0>; 511 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>; 512 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 513 514 num-lanes = <1>; 515 clock-names = "core", "reg"; 516 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>; 517 status = "disabled"; 518 }; 519 520 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { 521 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 522 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, 523 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; 524 reg-names = "ctrl", "config"; 525 #address-cells = <3>; 526 #size-cells = <2>; 527 #interrupt-cells = <1>; 528 device_type = "pci"; 529 dma-coherent; 530 msi-parent = <&gic_v2m0>; 531 532 bus-range = <0 0xff>; 533 ranges = 534 /* downstream I/O */ 535 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000 536 /* non-prefetchable memory */ 537 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>; 538 interrupt-map-mask = <0 0 0 0>; 539 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>; 540 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 541 542 num-lanes = <1>; 543 clock-names = "core", "reg"; 544 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>; 545 status = "disabled"; 546 }; 547}; 548