1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada CP110. 6 */ 7 8#include <dt-bindings/interrupt-controller/mvebu-icu.h> 9#include <dt-bindings/thermal/thermal.h> 10 11#include "armada-common.dtsi" 12 13#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000)) 14#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000)) 15#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000) 16 17/ { 18 /* 19 * The contents of the node are defined below, in order to 20 * save one indentation level 21 */ 22 CP110_NAME: CP110_NAME { }; 23 24 /* 25 * CPs only have one sensor in the thermal IC. 26 * 27 * The cooling maps are empty as there are no cooling devices. 28 */ 29 thermal-zones { 30 CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) { 31 polling-delay-passive = <1000>; 32 polling-delay = <1000>; 33 34 thermal-sensors = <&CP110_LABEL(thermal) 0>; 35 36 trips { }; 37 cooling-maps { }; 38 }; 39 }; 40}; 41 42&CP110_NAME { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 compatible = "simple-bus"; 46 interrupt-parent = <&CP110_LABEL(icu)>; 47 ranges; 48 49 config-space@CP110_BASE { 50 #address-cells = <1>; 51 #size-cells = <1>; 52 compatible = "simple-bus"; 53 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; 54 55 CP110_LABEL(ethernet): ethernet@0 { 56 compatible = "marvell,armada-7k-pp22"; 57 reg = <0x0 0x100000>, <0x129000 0xb000>; 58 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>, 59 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>, 60 <&CP110_LABEL(clk) 1 18>; 61 clock-names = "pp_clk", "gop_clk", 62 "mg_clk", "mg_core_clk", "axi_clk"; 63 marvell,system-controller = <&CP110_LABEL(syscon0)>; 64 status = "disabled"; 65 dma-coherent; 66 67 CP110_LABEL(eth0): eth0 { 68 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>, 69 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>, 70 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>, 71 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>, 72 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>, 73 <ICU_GRP_NSR 59 IRQ_TYPE_LEVEL_HIGH>, 74 <ICU_GRP_NSR 63 IRQ_TYPE_LEVEL_HIGH>, 75 <ICU_GRP_NSR 67 IRQ_TYPE_LEVEL_HIGH>, 76 <ICU_GRP_NSR 71 IRQ_TYPE_LEVEL_HIGH>, 77 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>; 78 interrupt-names = "hif0", "hif1", "hif2", 79 "hif3", "hif4", "hif5", "hif6", "hif7", 80 "hif8", "link"; 81 port-id = <0>; 82 gop-port-id = <0>; 83 status = "disabled"; 84 }; 85 86 CP110_LABEL(eth1): eth1 { 87 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>, 88 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>, 89 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>, 90 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>, 91 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>, 92 <ICU_GRP_NSR 60 IRQ_TYPE_LEVEL_HIGH>, 93 <ICU_GRP_NSR 64 IRQ_TYPE_LEVEL_HIGH>, 94 <ICU_GRP_NSR 68 IRQ_TYPE_LEVEL_HIGH>, 95 <ICU_GRP_NSR 72 IRQ_TYPE_LEVEL_HIGH>, 96 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>; 97 interrupt-names = "hif0", "hif1", "hif2", 98 "hif3", "hif4", "hif5", "hif6", "hif7", 99 "hif8", "link"; 100 port-id = <1>; 101 gop-port-id = <2>; 102 status = "disabled"; 103 }; 104 105 CP110_LABEL(eth2): eth2 { 106 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>, 107 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>, 108 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>, 109 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>, 110 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>, 111 <ICU_GRP_NSR 61 IRQ_TYPE_LEVEL_HIGH>, 112 <ICU_GRP_NSR 65 IRQ_TYPE_LEVEL_HIGH>, 113 <ICU_GRP_NSR 69 IRQ_TYPE_LEVEL_HIGH>, 114 <ICU_GRP_NSR 73 IRQ_TYPE_LEVEL_HIGH>, 115 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-names = "hif0", "hif1", "hif2", 117 "hif3", "hif4", "hif5", "hif6", "hif7", 118 "hif8", "link"; 119 port-id = <2>; 120 gop-port-id = <3>; 121 status = "disabled"; 122 }; 123 }; 124 125 CP110_LABEL(comphy): phy@120000 { 126 compatible = "marvell,comphy-cp110"; 127 reg = <0x120000 0x6000>; 128 marvell,system-controller = <&CP110_LABEL(syscon0)>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 132 CP110_LABEL(comphy0): phy@0 { 133 reg = <0>; 134 #phy-cells = <1>; 135 }; 136 137 CP110_LABEL(comphy1): phy@1 { 138 reg = <1>; 139 #phy-cells = <1>; 140 }; 141 142 CP110_LABEL(comphy2): phy@2 { 143 reg = <2>; 144 #phy-cells = <1>; 145 }; 146 147 CP110_LABEL(comphy3): phy@3 { 148 reg = <3>; 149 #phy-cells = <1>; 150 }; 151 152 CP110_LABEL(comphy4): phy@4 { 153 reg = <4>; 154 #phy-cells = <1>; 155 }; 156 157 CP110_LABEL(comphy5): phy@5 { 158 reg = <5>; 159 #phy-cells = <1>; 160 }; 161 }; 162 163 CP110_LABEL(mdio): mdio@12a200 { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 compatible = "marvell,orion-mdio"; 167 reg = <0x12a200 0x10>; 168 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>, 169 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 170 status = "disabled"; 171 }; 172 173 CP110_LABEL(xmdio): mdio@12a600 { 174 #address-cells = <1>; 175 #size-cells = <0>; 176 compatible = "marvell,xmdio"; 177 reg = <0x12a600 0x10>; 178 clocks = <&CP110_LABEL(clk) 1 5>, 179 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 180 status = "disabled"; 181 }; 182 183 CP110_LABEL(icu): interrupt-controller@1e0000 { 184 compatible = "marvell,cp110-icu"; 185 reg = <0x1e0000 0x440>; 186 #interrupt-cells = <3>; 187 interrupt-controller; 188 msi-parent = <&gicp>; 189 }; 190 191 CP110_LABEL(rtc): rtc@284000 { 192 compatible = "marvell,armada-8k-rtc"; 193 reg = <0x284000 0x20>, <0x284080 0x24>; 194 reg-names = "rtc", "rtc-soc"; 195 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; 196 }; 197 198 CP110_LABEL(syscon0): system-controller@440000 { 199 compatible = "syscon", "simple-mfd"; 200 reg = <0x440000 0x2000>; 201 202 CP110_LABEL(clk): clock { 203 compatible = "marvell,cp110-clock"; 204 #clock-cells = <2>; 205 }; 206 207 CP110_LABEL(gpio1): gpio@100 { 208 compatible = "marvell,armada-8k-gpio"; 209 offset = <0x100>; 210 ngpios = <32>; 211 gpio-controller; 212 #gpio-cells = <2>; 213 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; 214 interrupt-controller; 215 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>, 216 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>, 217 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>, 218 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>; 219 status = "disabled"; 220 }; 221 222 CP110_LABEL(gpio2): gpio@140 { 223 compatible = "marvell,armada-8k-gpio"; 224 offset = <0x140>; 225 ngpios = <31>; 226 gpio-controller; 227 #gpio-cells = <2>; 228 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>; 229 interrupt-controller; 230 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>, 231 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>, 232 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>, 233 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>; 234 status = "disabled"; 235 }; 236 }; 237 238 CP110_LABEL(syscon1): system-controller@400000 { 239 compatible = "syscon", "simple-mfd"; 240 reg = <0x400000 0x1000>; 241 #address-cells = <1>; 242 #size-cells = <1>; 243 244 CP110_LABEL(thermal): thermal-sensor@70 { 245 compatible = "marvell,armada-cp110-thermal"; 246 reg = <0x70 0x10>; 247 #thermal-sensor-cells = <1>; 248 }; 249 }; 250 251 CP110_LABEL(usb3_0): usb3@500000 { 252 compatible = "marvell,armada-8k-xhci", 253 "generic-xhci"; 254 reg = <0x500000 0x4000>; 255 dma-coherent; 256 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; 257 clock-names = "core", "reg"; 258 clocks = <&CP110_LABEL(clk) 1 22>, 259 <&CP110_LABEL(clk) 1 16>; 260 status = "disabled"; 261 }; 262 263 CP110_LABEL(usb3_1): usb3@510000 { 264 compatible = "marvell,armada-8k-xhci", 265 "generic-xhci"; 266 reg = <0x510000 0x4000>; 267 dma-coherent; 268 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>; 269 clock-names = "core", "reg"; 270 clocks = <&CP110_LABEL(clk) 1 23>, 271 <&CP110_LABEL(clk) 1 16>; 272 status = "disabled"; 273 }; 274 275 CP110_LABEL(sata0): sata@540000 { 276 compatible = "marvell,armada-8k-ahci", 277 "generic-ahci"; 278 reg = <0x540000 0x30000>; 279 dma-coherent; 280 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&CP110_LABEL(clk) 1 15>, 282 <&CP110_LABEL(clk) 1 16>; 283 status = "disabled"; 284 }; 285 286 CP110_LABEL(xor0): xor@6a0000 { 287 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 288 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; 289 dma-coherent; 290 msi-parent = <&gic_v2m0>; 291 clock-names = "core", "reg"; 292 clocks = <&CP110_LABEL(clk) 1 8>, 293 <&CP110_LABEL(clk) 1 14>; 294 }; 295 296 CP110_LABEL(xor1): xor@6c0000 { 297 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 298 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; 299 dma-coherent; 300 msi-parent = <&gic_v2m0>; 301 clock-names = "core", "reg"; 302 clocks = <&CP110_LABEL(clk) 1 7>, 303 <&CP110_LABEL(clk) 1 14>; 304 }; 305 306 CP110_LABEL(spi0): spi@700600 { 307 compatible = "marvell,armada-380-spi"; 308 reg = <0x700600 0x50>; 309 #address-cells = <0x1>; 310 #size-cells = <0x0>; 311 clock-names = "core", "axi"; 312 clocks = <&CP110_LABEL(clk) 1 21>, 313 <&CP110_LABEL(clk) 1 17>; 314 status = "disabled"; 315 }; 316 317 CP110_LABEL(spi1): spi@700680 { 318 compatible = "marvell,armada-380-spi"; 319 reg = <0x700680 0x50>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 clock-names = "core", "axi"; 323 clocks = <&CP110_LABEL(clk) 1 21>, 324 <&CP110_LABEL(clk) 1 17>; 325 status = "disabled"; 326 }; 327 328 CP110_LABEL(i2c0): i2c@701000 { 329 compatible = "marvell,mv78230-i2c"; 330 reg = <0x701000 0x20>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>; 334 clock-names = "core", "reg"; 335 clocks = <&CP110_LABEL(clk) 1 21>, 336 <&CP110_LABEL(clk) 1 17>; 337 status = "disabled"; 338 }; 339 340 CP110_LABEL(i2c1): i2c@701100 { 341 compatible = "marvell,mv78230-i2c"; 342 reg = <0x701100 0x20>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>; 346 clock-names = "core", "reg"; 347 clocks = <&CP110_LABEL(clk) 1 21>, 348 <&CP110_LABEL(clk) 1 17>; 349 status = "disabled"; 350 }; 351 352 CP110_LABEL(uart0): serial@702000 { 353 compatible = "snps,dw-apb-uart"; 354 reg = <0x702000 0x100>; 355 reg-shift = <2>; 356 interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>; 357 reg-io-width = <1>; 358 clock-names = "baudclk", "apb_pclk"; 359 clocks = <&CP110_LABEL(clk) 1 21>, 360 <&CP110_LABEL(clk) 1 17>; 361 status = "disabled"; 362 }; 363 364 CP110_LABEL(uart1): serial@702100 { 365 compatible = "snps,dw-apb-uart"; 366 reg = <0x702100 0x100>; 367 reg-shift = <2>; 368 interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>; 369 reg-io-width = <1>; 370 clock-names = "baudclk", "apb_pclk"; 371 clocks = <&CP110_LABEL(clk) 1 21>, 372 <&CP110_LABEL(clk) 1 17>; 373 status = "disabled"; 374 }; 375 376 CP110_LABEL(uart2): serial@702200 { 377 compatible = "snps,dw-apb-uart"; 378 reg = <0x702200 0x100>; 379 reg-shift = <2>; 380 interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>; 381 reg-io-width = <1>; 382 clock-names = "baudclk", "apb_pclk"; 383 clocks = <&CP110_LABEL(clk) 1 21>, 384 <&CP110_LABEL(clk) 1 17>; 385 status = "disabled"; 386 }; 387 388 CP110_LABEL(uart3): serial@702300 { 389 compatible = "snps,dw-apb-uart"; 390 reg = <0x702300 0x100>; 391 reg-shift = <2>; 392 interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>; 393 reg-io-width = <1>; 394 clock-names = "baudclk", "apb_pclk"; 395 clocks = <&CP110_LABEL(clk) 1 21>, 396 <&CP110_LABEL(clk) 1 17>; 397 status = "disabled"; 398 }; 399 400 CP110_LABEL(nand_controller): nand@720000 { 401 /* 402 * Due to the limitation of the pins available 403 * this controller is only usable on the CPM 404 * for A7K and on the CPS for A8K. 405 */ 406 compatible = "marvell,armada-8k-nand-controller", 407 "marvell,armada370-nand-controller"; 408 reg = <0x720000 0x54>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; 412 clock-names = "core", "reg"; 413 clocks = <&CP110_LABEL(clk) 1 2>, 414 <&CP110_LABEL(clk) 1 17>; 415 marvell,system-controller = <&CP110_LABEL(syscon0)>; 416 status = "disabled"; 417 }; 418 419 CP110_LABEL(trng): trng@760000 { 420 compatible = "marvell,armada-8k-rng", 421 "inside-secure,safexcel-eip76"; 422 reg = <0x760000 0x7d>; 423 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>; 424 clock-names = "core", "reg"; 425 clocks = <&CP110_LABEL(clk) 1 25>, 426 <&CP110_LABEL(clk) 1 17>; 427 status = "okay"; 428 }; 429 430 CP110_LABEL(sdhci0): sdhci@780000 { 431 compatible = "marvell,armada-cp110-sdhci"; 432 reg = <0x780000 0x300>; 433 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>; 434 clock-names = "core", "axi"; 435 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>; 436 dma-coherent; 437 status = "disabled"; 438 }; 439 440 CP110_LABEL(crypto): crypto@800000 { 441 compatible = "inside-secure,safexcel-eip197b"; 442 reg = <0x800000 0x200000>; 443 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>, 444 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>, 445 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>, 446 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>, 447 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>, 448 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>; 449 interrupt-names = "mem", "ring0", "ring1", 450 "ring2", "ring3", "eip"; 451 clock-names = "core", "reg"; 452 clocks = <&CP110_LABEL(clk) 1 26>, 453 <&CP110_LABEL(clk) 1 17>; 454 dma-coherent; 455 }; 456 }; 457 458 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { 459 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 460 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, 461 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; 462 reg-names = "ctrl", "config"; 463 #address-cells = <3>; 464 #size-cells = <2>; 465 #interrupt-cells = <1>; 466 device_type = "pci"; 467 dma-coherent; 468 msi-parent = <&gic_v2m0>; 469 470 bus-range = <0 0xff>; 471 ranges = 472 /* downstream I/O */ 473 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000 474 /* non-prefetchable memory */ 475 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>; 476 interrupt-map-mask = <0 0 0 0>; 477 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 478 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 479 num-lanes = <1>; 480 clock-names = "core", "reg"; 481 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>; 482 status = "disabled"; 483 }; 484 485 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { 486 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 487 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, 488 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; 489 reg-names = "ctrl", "config"; 490 #address-cells = <3>; 491 #size-cells = <2>; 492 #interrupt-cells = <1>; 493 device_type = "pci"; 494 dma-coherent; 495 msi-parent = <&gic_v2m0>; 496 497 bus-range = <0 0xff>; 498 ranges = 499 /* downstream I/O */ 500 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000 501 /* non-prefetchable memory */ 502 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>; 503 interrupt-map-mask = <0 0 0 0>; 504 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 505 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 506 507 num-lanes = <1>; 508 clock-names = "core", "reg"; 509 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>; 510 status = "disabled"; 511 }; 512 513 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { 514 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 515 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, 516 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; 517 reg-names = "ctrl", "config"; 518 #address-cells = <3>; 519 #size-cells = <2>; 520 #interrupt-cells = <1>; 521 device_type = "pci"; 522 dma-coherent; 523 msi-parent = <&gic_v2m0>; 524 525 bus-range = <0 0xff>; 526 ranges = 527 /* downstream I/O */ 528 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000 529 /* non-prefetchable memory */ 530 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>; 531 interrupt-map-mask = <0 0 0 0>; 532 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 533 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 534 535 num-lanes = <1>; 536 clock-names = "core", "reg"; 537 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>; 538 status = "disabled"; 539 }; 540}; 541