1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada CP110. 6 */ 7 8#include <dt-bindings/interrupt-controller/mvebu-icu.h> 9 10#include "armada-common.dtsi" 11 12#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000)) 13#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000)) 14#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000) 15 16/ { 17 /* 18 * The contents of the node are defined below, in order to 19 * save one indentation level 20 */ 21 CP110_NAME: CP110_NAME { }; 22}; 23 24&CP110_NAME { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 compatible = "simple-bus"; 28 interrupt-parent = <&CP110_LABEL(icu)>; 29 ranges; 30 31 config-space@CP110_BASE { 32 #address-cells = <1>; 33 #size-cells = <1>; 34 compatible = "simple-bus"; 35 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; 36 37 CP110_LABEL(ethernet): ethernet@0 { 38 compatible = "marvell,armada-7k-pp22"; 39 reg = <0x0 0x100000>, <0x129000 0xb000>; 40 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>, 41 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 18>; 42 clock-names = "pp_clk", "gop_clk", 43 "mg_clk", "axi_clk"; 44 marvell,system-controller = <&CP110_LABEL(syscon0)>; 45 status = "disabled"; 46 dma-coherent; 47 48 CP110_LABEL(eth0): eth0 { 49 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>, 50 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>, 51 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>, 52 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>, 53 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>, 54 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>; 55 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 56 "tx-cpu3", "rx-shared", "link"; 57 port-id = <0>; 58 gop-port-id = <0>; 59 status = "disabled"; 60 }; 61 62 CP110_LABEL(eth1): eth1 { 63 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>, 64 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>, 65 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>, 66 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>, 67 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>, 68 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 70 "tx-cpu3", "rx-shared", "link"; 71 port-id = <1>; 72 gop-port-id = <2>; 73 status = "disabled"; 74 }; 75 76 CP110_LABEL(eth2): eth2 { 77 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>, 78 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>, 79 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>, 80 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>, 81 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>, 82 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 84 "tx-cpu3", "rx-shared", "link"; 85 port-id = <2>; 86 gop-port-id = <3>; 87 status = "disabled"; 88 }; 89 }; 90 91 CP110_LABEL(comphy): phy@120000 { 92 compatible = "marvell,comphy-cp110"; 93 reg = <0x120000 0x6000>; 94 marvell,system-controller = <&CP110_LABEL(syscon0)>; 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 CP110_LABEL(comphy0): phy@0 { 99 reg = <0>; 100 #phy-cells = <1>; 101 }; 102 103 CP110_LABEL(comphy1): phy@1 { 104 reg = <1>; 105 #phy-cells = <1>; 106 }; 107 108 CP110_LABEL(comphy2): phy@2 { 109 reg = <2>; 110 #phy-cells = <1>; 111 }; 112 113 CP110_LABEL(comphy3): phy@3 { 114 reg = <3>; 115 #phy-cells = <1>; 116 }; 117 118 CP110_LABEL(comphy4): phy@4 { 119 reg = <4>; 120 #phy-cells = <1>; 121 }; 122 123 CP110_LABEL(comphy5): phy@5 { 124 reg = <5>; 125 #phy-cells = <1>; 126 }; 127 }; 128 129 CP110_LABEL(mdio): mdio@12a200 { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 compatible = "marvell,orion-mdio"; 133 reg = <0x12a200 0x10>; 134 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>, 135 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 136 status = "disabled"; 137 }; 138 139 CP110_LABEL(xmdio): mdio@12a600 { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 compatible = "marvell,xmdio"; 143 reg = <0x12a600 0x10>; 144 status = "disabled"; 145 }; 146 147 CP110_LABEL(icu): interrupt-controller@1e0000 { 148 compatible = "marvell,cp110-icu"; 149 reg = <0x1e0000 0x10>; 150 #interrupt-cells = <3>; 151 interrupt-controller; 152 msi-parent = <&gicp>; 153 }; 154 155 CP110_LABEL(rtc): rtc@284000 { 156 compatible = "marvell,armada-8k-rtc"; 157 reg = <0x284000 0x20>, <0x284080 0x24>; 158 reg-names = "rtc", "rtc-soc"; 159 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; 160 }; 161 162 CP110_LABEL(thermal): thermal@400078 { 163 compatible = "marvell,armada-cp110-thermal"; 164 reg = <0x400078 0x4>, 165 <0x400070 0x8>; 166 }; 167 168 CP110_LABEL(syscon0): system-controller@440000 { 169 compatible = "syscon", "simple-mfd"; 170 reg = <0x440000 0x2000>; 171 172 CP110_LABEL(clk): clock { 173 compatible = "marvell,cp110-clock"; 174 #clock-cells = <2>; 175 }; 176 177 CP110_LABEL(gpio1): gpio@100 { 178 compatible = "marvell,armada-8k-gpio"; 179 offset = <0x100>; 180 ngpios = <32>; 181 gpio-controller; 182 #gpio-cells = <2>; 183 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; 184 interrupt-controller; 185 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>, 186 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>, 187 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>, 188 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>; 189 status = "disabled"; 190 }; 191 192 CP110_LABEL(gpio2): gpio@140 { 193 compatible = "marvell,armada-8k-gpio"; 194 offset = <0x140>; 195 ngpios = <31>; 196 gpio-controller; 197 #gpio-cells = <2>; 198 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>; 199 interrupt-controller; 200 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>, 201 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>, 202 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>, 203 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>; 204 status = "disabled"; 205 }; 206 }; 207 208 CP110_LABEL(usb3_0): usb3@500000 { 209 compatible = "marvell,armada-8k-xhci", 210 "generic-xhci"; 211 reg = <0x500000 0x4000>; 212 dma-coherent; 213 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; 214 clock-names = "core", "reg"; 215 clocks = <&CP110_LABEL(clk) 1 22>, 216 <&CP110_LABEL(clk) 1 16>; 217 status = "disabled"; 218 }; 219 220 CP110_LABEL(usb3_1): usb3@510000 { 221 compatible = "marvell,armada-8k-xhci", 222 "generic-xhci"; 223 reg = <0x510000 0x4000>; 224 dma-coherent; 225 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>; 226 clock-names = "core", "reg"; 227 clocks = <&CP110_LABEL(clk) 1 23>, 228 <&CP110_LABEL(clk) 1 16>; 229 status = "disabled"; 230 }; 231 232 CP110_LABEL(sata0): sata@540000 { 233 compatible = "marvell,armada-8k-ahci", 234 "generic-ahci"; 235 reg = <0x540000 0x30000>; 236 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&CP110_LABEL(clk) 1 15>, 238 <&CP110_LABEL(clk) 1 16>; 239 status = "disabled"; 240 }; 241 242 CP110_LABEL(xor0): xor@6a0000 { 243 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 244 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; 245 dma-coherent; 246 msi-parent = <&gic_v2m0>; 247 clocks = <&CP110_LABEL(clk) 1 8>; 248 }; 249 250 CP110_LABEL(xor1): xor@6c0000 { 251 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 252 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; 253 dma-coherent; 254 msi-parent = <&gic_v2m0>; 255 clocks = <&CP110_LABEL(clk) 1 7>; 256 }; 257 258 CP110_LABEL(spi0): spi@700600 { 259 compatible = "marvell,armada-380-spi"; 260 reg = <0x700600 0x50>; 261 #address-cells = <0x1>; 262 #size-cells = <0x0>; 263 clock-names = "core", "axi"; 264 clocks = <&CP110_LABEL(clk) 1 21>, 265 <&CP110_LABEL(clk) 1 17>; 266 status = "disabled"; 267 }; 268 269 CP110_LABEL(spi1): spi@700680 { 270 compatible = "marvell,armada-380-spi"; 271 reg = <0x700680 0x50>; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 clock-names = "core", "axi"; 275 clocks = <&CP110_LABEL(clk) 1 21>, 276 <&CP110_LABEL(clk) 1 17>; 277 status = "disabled"; 278 }; 279 280 CP110_LABEL(i2c0): i2c@701000 { 281 compatible = "marvell,mv78230-i2c"; 282 reg = <0x701000 0x20>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>; 286 clock-names = "core", "reg"; 287 clocks = <&CP110_LABEL(clk) 1 21>, 288 <&CP110_LABEL(clk) 1 17>; 289 status = "disabled"; 290 }; 291 292 CP110_LABEL(i2c1): i2c@701100 { 293 compatible = "marvell,mv78230-i2c"; 294 reg = <0x701100 0x20>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>; 298 clock-names = "core", "reg"; 299 clocks = <&CP110_LABEL(clk) 1 21>, 300 <&CP110_LABEL(clk) 1 17>; 301 status = "disabled"; 302 }; 303 304 CP110_LABEL(uart0): serial@702000 { 305 compatible = "snps,dw-apb-uart"; 306 reg = <0x702000 0x100>; 307 reg-shift = <2>; 308 interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>; 309 reg-io-width = <1>; 310 clock-names = "baudclk", "apb_pclk"; 311 clocks = <&CP110_LABEL(clk) 1 21>, 312 <&CP110_LABEL(clk) 1 17>; 313 status = "disabled"; 314 }; 315 316 CP110_LABEL(uart1): serial@702100 { 317 compatible = "snps,dw-apb-uart"; 318 reg = <0x702100 0x100>; 319 reg-shift = <2>; 320 interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>; 321 reg-io-width = <1>; 322 clock-names = "baudclk", "apb_pclk"; 323 clocks = <&CP110_LABEL(clk) 1 21>, 324 <&CP110_LABEL(clk) 1 17>; 325 status = "disabled"; 326 }; 327 328 CP110_LABEL(uart2): serial@702200 { 329 compatible = "snps,dw-apb-uart"; 330 reg = <0x702200 0x100>; 331 reg-shift = <2>; 332 interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>; 333 reg-io-width = <1>; 334 clock-names = "baudclk", "apb_pclk"; 335 clocks = <&CP110_LABEL(clk) 1 21>, 336 <&CP110_LABEL(clk) 1 17>; 337 status = "disabled"; 338 }; 339 340 CP110_LABEL(uart3): serial@702300 { 341 compatible = "snps,dw-apb-uart"; 342 reg = <0x702300 0x100>; 343 reg-shift = <2>; 344 interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>; 345 reg-io-width = <1>; 346 clock-names = "baudclk", "apb_pclk"; 347 clocks = <&CP110_LABEL(clk) 1 21>, 348 <&CP110_LABEL(clk) 1 17>; 349 status = "disabled"; 350 }; 351 352 CP110_LABEL(nand_controller): nand@720000 { 353 /* 354 * Due to the limitation of the pins available 355 * this controller is only usable on the CPM 356 * for A7K and on the CPS for A8K. 357 */ 358 compatible = "marvell,armada-8k-nand-controller", 359 "marvell,armada370-nand-controller"; 360 reg = <0x720000 0x54>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&CP110_LABEL(clk) 1 2>; 365 marvell,system-controller = <&CP110_LABEL(syscon0)>; 366 status = "disabled"; 367 }; 368 369 CP110_LABEL(trng): trng@760000 { 370 compatible = "marvell,armada-8k-rng", 371 "inside-secure,safexcel-eip76"; 372 reg = <0x760000 0x7d>; 373 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&CP110_LABEL(clk) 1 25>; 375 status = "okay"; 376 }; 377 378 CP110_LABEL(sdhci0): sdhci@780000 { 379 compatible = "marvell,armada-cp110-sdhci"; 380 reg = <0x780000 0x300>; 381 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>; 382 clock-names = "core", "axi"; 383 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>; 384 dma-coherent; 385 status = "disabled"; 386 }; 387 388 CP110_LABEL(crypto): crypto@800000 { 389 compatible = "inside-secure,safexcel-eip197"; 390 reg = <0x800000 0x200000>; 391 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>, 392 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>, 393 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>, 394 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>, 395 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>, 396 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>; 397 interrupt-names = "mem", "ring0", "ring1", 398 "ring2", "ring3", "eip"; 399 clocks = <&CP110_LABEL(clk) 1 26>; 400 dma-coherent; 401 }; 402 }; 403 404 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { 405 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 406 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, 407 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; 408 reg-names = "ctrl", "config"; 409 #address-cells = <3>; 410 #size-cells = <2>; 411 #interrupt-cells = <1>; 412 device_type = "pci"; 413 dma-coherent; 414 msi-parent = <&gic_v2m0>; 415 416 bus-range = <0 0xff>; 417 ranges = 418 /* downstream I/O */ 419 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000 420 /* non-prefetchable memory */ 421 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>; 422 interrupt-map-mask = <0 0 0 0>; 423 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 424 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 425 num-lanes = <1>; 426 clocks = <&CP110_LABEL(clk) 1 13>; 427 status = "disabled"; 428 }; 429 430 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { 431 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 432 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, 433 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; 434 reg-names = "ctrl", "config"; 435 #address-cells = <3>; 436 #size-cells = <2>; 437 #interrupt-cells = <1>; 438 device_type = "pci"; 439 dma-coherent; 440 msi-parent = <&gic_v2m0>; 441 442 bus-range = <0 0xff>; 443 ranges = 444 /* downstream I/O */ 445 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000 446 /* non-prefetchable memory */ 447 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>; 448 interrupt-map-mask = <0 0 0 0>; 449 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 450 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 451 452 num-lanes = <1>; 453 clocks = <&CP110_LABEL(clk) 1 11>; 454 status = "disabled"; 455 }; 456 457 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { 458 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 459 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, 460 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; 461 reg-names = "ctrl", "config"; 462 #address-cells = <3>; 463 #size-cells = <2>; 464 #interrupt-cells = <1>; 465 device_type = "pci"; 466 dma-coherent; 467 msi-parent = <&gic_v2m0>; 468 469 bus-range = <0 0xff>; 470 ranges = 471 /* downstream I/O */ 472 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000 473 /* non-prefetchable memory */ 474 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>; 475 interrupt-map-mask = <0 0 0 0>; 476 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 477 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 478 479 num-lanes = <1>; 480 clocks = <&CP110_LABEL(clk) 1 12>; 481 status = "disabled"; 482 }; 483}; 484