1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada CP110. 6 */ 7 8#include <dt-bindings/interrupt-controller/mvebu-icu.h> 9 10#include "armada-common.dtsi" 11 12#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000)) 13#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000)) 14#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000) 15 16/ { 17 /* 18 * The contents of the node are defined below, in order to 19 * save one indentation level 20 */ 21 CP110_NAME: CP110_NAME { }; 22}; 23 24&CP110_NAME { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 compatible = "simple-bus"; 28 interrupt-parent = <&CP110_LABEL(icu)>; 29 ranges; 30 31 config-space@CP110_BASE { 32 #address-cells = <1>; 33 #size-cells = <1>; 34 compatible = "simple-bus"; 35 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; 36 37 CP110_LABEL(ethernet): ethernet@0 { 38 compatible = "marvell,armada-7k-pp22"; 39 reg = <0x0 0x100000>, <0x129000 0xb000>; 40 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>, 41 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 18>; 42 clock-names = "pp_clk", "gop_clk", 43 "mg_clk", "axi_clk"; 44 marvell,system-controller = <&CP110_LABEL(syscon0)>; 45 status = "disabled"; 46 dma-coherent; 47 48 CP110_LABEL(eth0): eth0 { 49 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>, 50 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>, 51 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>, 52 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>, 53 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>, 54 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>; 55 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 56 "tx-cpu3", "rx-shared", "link"; 57 port-id = <0>; 58 gop-port-id = <0>; 59 status = "disabled"; 60 }; 61 62 CP110_LABEL(eth1): eth1 { 63 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>, 64 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>, 65 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>, 66 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>, 67 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>, 68 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 70 "tx-cpu3", "rx-shared", "link"; 71 port-id = <1>; 72 gop-port-id = <2>; 73 status = "disabled"; 74 }; 75 76 CP110_LABEL(eth2): eth2 { 77 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>, 78 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>, 79 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>, 80 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>, 81 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>, 82 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 84 "tx-cpu3", "rx-shared", "link"; 85 port-id = <2>; 86 gop-port-id = <3>; 87 status = "disabled"; 88 }; 89 }; 90 91 CP110_LABEL(comphy): phy@120000 { 92 compatible = "marvell,comphy-cp110"; 93 reg = <0x120000 0x6000>; 94 marvell,system-controller = <&CP110_LABEL(syscon0)>; 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 CP110_LABEL(comphy0): phy@0 { 99 reg = <0>; 100 #phy-cells = <1>; 101 }; 102 103 CP110_LABEL(comphy1): phy@1 { 104 reg = <1>; 105 #phy-cells = <1>; 106 }; 107 108 CP110_LABEL(comphy2): phy@2 { 109 reg = <2>; 110 #phy-cells = <1>; 111 }; 112 113 CP110_LABEL(comphy3): phy@3 { 114 reg = <3>; 115 #phy-cells = <1>; 116 }; 117 118 CP110_LABEL(comphy4): phy@4 { 119 reg = <4>; 120 #phy-cells = <1>; 121 }; 122 123 CP110_LABEL(comphy5): phy@5 { 124 reg = <5>; 125 #phy-cells = <1>; 126 }; 127 }; 128 129 CP110_LABEL(mdio): mdio@12a200 { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 compatible = "marvell,orion-mdio"; 133 reg = <0x12a200 0x10>; 134 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>, 135 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 136 status = "disabled"; 137 }; 138 139 CP110_LABEL(xmdio): mdio@12a600 { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 compatible = "marvell,xmdio"; 143 reg = <0x12a600 0x10>; 144 clocks = <&CP110_LABEL(clk) 1 5>, 145 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 146 status = "disabled"; 147 }; 148 149 CP110_LABEL(icu): interrupt-controller@1e0000 { 150 compatible = "marvell,cp110-icu"; 151 reg = <0x1e0000 0x10>; 152 #interrupt-cells = <3>; 153 interrupt-controller; 154 msi-parent = <&gicp>; 155 }; 156 157 CP110_LABEL(rtc): rtc@284000 { 158 compatible = "marvell,armada-8k-rtc"; 159 reg = <0x284000 0x20>, <0x284080 0x24>; 160 reg-names = "rtc", "rtc-soc"; 161 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; 162 }; 163 164 CP110_LABEL(thermal): thermal@400078 { 165 compatible = "marvell,armada-cp110-thermal"; 166 reg = <0x400078 0x4>, 167 <0x400070 0x8>; 168 }; 169 170 CP110_LABEL(syscon0): system-controller@440000 { 171 compatible = "syscon", "simple-mfd"; 172 reg = <0x440000 0x2000>; 173 174 CP110_LABEL(clk): clock { 175 compatible = "marvell,cp110-clock"; 176 #clock-cells = <2>; 177 }; 178 179 CP110_LABEL(gpio1): gpio@100 { 180 compatible = "marvell,armada-8k-gpio"; 181 offset = <0x100>; 182 ngpios = <32>; 183 gpio-controller; 184 #gpio-cells = <2>; 185 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; 186 interrupt-controller; 187 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>, 188 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>, 189 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>, 190 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>; 191 status = "disabled"; 192 }; 193 194 CP110_LABEL(gpio2): gpio@140 { 195 compatible = "marvell,armada-8k-gpio"; 196 offset = <0x140>; 197 ngpios = <31>; 198 gpio-controller; 199 #gpio-cells = <2>; 200 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>; 201 interrupt-controller; 202 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>, 203 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>, 204 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>, 205 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>; 206 status = "disabled"; 207 }; 208 }; 209 210 CP110_LABEL(usb3_0): usb3@500000 { 211 compatible = "marvell,armada-8k-xhci", 212 "generic-xhci"; 213 reg = <0x500000 0x4000>; 214 dma-coherent; 215 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; 216 clock-names = "core", "reg"; 217 clocks = <&CP110_LABEL(clk) 1 22>, 218 <&CP110_LABEL(clk) 1 16>; 219 status = "disabled"; 220 }; 221 222 CP110_LABEL(usb3_1): usb3@510000 { 223 compatible = "marvell,armada-8k-xhci", 224 "generic-xhci"; 225 reg = <0x510000 0x4000>; 226 dma-coherent; 227 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>; 228 clock-names = "core", "reg"; 229 clocks = <&CP110_LABEL(clk) 1 23>, 230 <&CP110_LABEL(clk) 1 16>; 231 status = "disabled"; 232 }; 233 234 CP110_LABEL(sata0): sata@540000 { 235 compatible = "marvell,armada-8k-ahci", 236 "generic-ahci"; 237 reg = <0x540000 0x30000>; 238 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&CP110_LABEL(clk) 1 15>, 240 <&CP110_LABEL(clk) 1 16>; 241 status = "disabled"; 242 }; 243 244 CP110_LABEL(xor0): xor@6a0000 { 245 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 246 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; 247 dma-coherent; 248 msi-parent = <&gic_v2m0>; 249 clock-names = "core", "reg"; 250 clocks = <&CP110_LABEL(clk) 1 8>, 251 <&CP110_LABEL(clk) 1 14>; 252 }; 253 254 CP110_LABEL(xor1): xor@6c0000 { 255 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 256 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; 257 dma-coherent; 258 msi-parent = <&gic_v2m0>; 259 clock-names = "core", "reg"; 260 clocks = <&CP110_LABEL(clk) 1 7>, 261 <&CP110_LABEL(clk) 1 14>; 262 }; 263 264 CP110_LABEL(spi0): spi@700600 { 265 compatible = "marvell,armada-380-spi"; 266 reg = <0x700600 0x50>; 267 #address-cells = <0x1>; 268 #size-cells = <0x0>; 269 clock-names = "core", "axi"; 270 clocks = <&CP110_LABEL(clk) 1 21>, 271 <&CP110_LABEL(clk) 1 17>; 272 status = "disabled"; 273 }; 274 275 CP110_LABEL(spi1): spi@700680 { 276 compatible = "marvell,armada-380-spi"; 277 reg = <0x700680 0x50>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 clock-names = "core", "axi"; 281 clocks = <&CP110_LABEL(clk) 1 21>, 282 <&CP110_LABEL(clk) 1 17>; 283 status = "disabled"; 284 }; 285 286 CP110_LABEL(i2c0): i2c@701000 { 287 compatible = "marvell,mv78230-i2c"; 288 reg = <0x701000 0x20>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>; 292 clock-names = "core", "reg"; 293 clocks = <&CP110_LABEL(clk) 1 21>, 294 <&CP110_LABEL(clk) 1 17>; 295 status = "disabled"; 296 }; 297 298 CP110_LABEL(i2c1): i2c@701100 { 299 compatible = "marvell,mv78230-i2c"; 300 reg = <0x701100 0x20>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>; 304 clock-names = "core", "reg"; 305 clocks = <&CP110_LABEL(clk) 1 21>, 306 <&CP110_LABEL(clk) 1 17>; 307 status = "disabled"; 308 }; 309 310 CP110_LABEL(uart0): serial@702000 { 311 compatible = "snps,dw-apb-uart"; 312 reg = <0x702000 0x100>; 313 reg-shift = <2>; 314 interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>; 315 reg-io-width = <1>; 316 clock-names = "baudclk", "apb_pclk"; 317 clocks = <&CP110_LABEL(clk) 1 21>, 318 <&CP110_LABEL(clk) 1 17>; 319 status = "disabled"; 320 }; 321 322 CP110_LABEL(uart1): serial@702100 { 323 compatible = "snps,dw-apb-uart"; 324 reg = <0x702100 0x100>; 325 reg-shift = <2>; 326 interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>; 327 reg-io-width = <1>; 328 clock-names = "baudclk", "apb_pclk"; 329 clocks = <&CP110_LABEL(clk) 1 21>, 330 <&CP110_LABEL(clk) 1 17>; 331 status = "disabled"; 332 }; 333 334 CP110_LABEL(uart2): serial@702200 { 335 compatible = "snps,dw-apb-uart"; 336 reg = <0x702200 0x100>; 337 reg-shift = <2>; 338 interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>; 339 reg-io-width = <1>; 340 clock-names = "baudclk", "apb_pclk"; 341 clocks = <&CP110_LABEL(clk) 1 21>, 342 <&CP110_LABEL(clk) 1 17>; 343 status = "disabled"; 344 }; 345 346 CP110_LABEL(uart3): serial@702300 { 347 compatible = "snps,dw-apb-uart"; 348 reg = <0x702300 0x100>; 349 reg-shift = <2>; 350 interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>; 351 reg-io-width = <1>; 352 clock-names = "baudclk", "apb_pclk"; 353 clocks = <&CP110_LABEL(clk) 1 21>, 354 <&CP110_LABEL(clk) 1 17>; 355 status = "disabled"; 356 }; 357 358 CP110_LABEL(nand_controller): nand@720000 { 359 /* 360 * Due to the limitation of the pins available 361 * this controller is only usable on the CPM 362 * for A7K and on the CPS for A8K. 363 */ 364 compatible = "marvell,armada-8k-nand-controller", 365 "marvell,armada370-nand-controller"; 366 reg = <0x720000 0x54>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; 370 clock-names = "core", "reg"; 371 clocks = <&CP110_LABEL(clk) 1 2>, 372 <&CP110_LABEL(clk) 1 17>; 373 marvell,system-controller = <&CP110_LABEL(syscon0)>; 374 status = "disabled"; 375 }; 376 377 CP110_LABEL(trng): trng@760000 { 378 compatible = "marvell,armada-8k-rng", 379 "inside-secure,safexcel-eip76"; 380 reg = <0x760000 0x7d>; 381 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>; 382 clock-names = "core", "reg"; 383 clocks = <&CP110_LABEL(clk) 1 25>, 384 <&CP110_LABEL(clk) 1 17>; 385 status = "okay"; 386 }; 387 388 CP110_LABEL(sdhci0): sdhci@780000 { 389 compatible = "marvell,armada-cp110-sdhci"; 390 reg = <0x780000 0x300>; 391 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>; 392 clock-names = "core", "axi"; 393 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>; 394 dma-coherent; 395 status = "disabled"; 396 }; 397 398 CP110_LABEL(crypto): crypto@800000 { 399 compatible = "inside-secure,safexcel-eip197"; 400 reg = <0x800000 0x200000>; 401 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>, 402 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>, 403 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>, 404 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>, 405 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>, 406 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>; 407 interrupt-names = "mem", "ring0", "ring1", 408 "ring2", "ring3", "eip"; 409 clock-names = "core", "reg"; 410 clocks = <&CP110_LABEL(clk) 1 26>, 411 <&CP110_LABEL(clk) 1 17>; 412 dma-coherent; 413 }; 414 }; 415 416 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { 417 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 418 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, 419 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; 420 reg-names = "ctrl", "config"; 421 #address-cells = <3>; 422 #size-cells = <2>; 423 #interrupt-cells = <1>; 424 device_type = "pci"; 425 dma-coherent; 426 msi-parent = <&gic_v2m0>; 427 428 bus-range = <0 0xff>; 429 ranges = 430 /* downstream I/O */ 431 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000 432 /* non-prefetchable memory */ 433 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>; 434 interrupt-map-mask = <0 0 0 0>; 435 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 436 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 437 num-lanes = <1>; 438 clock-names = "core", "reg"; 439 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>; 440 status = "disabled"; 441 }; 442 443 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { 444 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 445 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, 446 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; 447 reg-names = "ctrl", "config"; 448 #address-cells = <3>; 449 #size-cells = <2>; 450 #interrupt-cells = <1>; 451 device_type = "pci"; 452 dma-coherent; 453 msi-parent = <&gic_v2m0>; 454 455 bus-range = <0 0xff>; 456 ranges = 457 /* downstream I/O */ 458 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000 459 /* non-prefetchable memory */ 460 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>; 461 interrupt-map-mask = <0 0 0 0>; 462 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 463 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 464 465 num-lanes = <1>; 466 clock-names = "core", "reg"; 467 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>; 468 status = "disabled"; 469 }; 470 471 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { 472 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 473 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, 474 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; 475 reg-names = "ctrl", "config"; 476 #address-cells = <3>; 477 #size-cells = <2>; 478 #interrupt-cells = <1>; 479 device_type = "pci"; 480 dma-coherent; 481 msi-parent = <&gic_v2m0>; 482 483 bus-range = <0 0xff>; 484 ranges = 485 /* downstream I/O */ 486 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000 487 /* non-prefetchable memory */ 488 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>; 489 interrupt-map-mask = <0 0 0 0>; 490 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 491 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 492 493 num-lanes = <1>; 494 clock-names = "core", "reg"; 495 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>; 496 status = "disabled"; 497 }; 498}; 499