1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada CP110. 6 */ 7 8#include <dt-bindings/interrupt-controller/mvebu-icu.h> 9 10#include "armada-common.dtsi" 11 12#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000)) 13#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000)) 14#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000) 15 16/ { 17 /* 18 * The contents of the node are defined below, in order to 19 * save one indentation level 20 */ 21 CP110_NAME: CP110_NAME { }; 22}; 23 24&CP110_NAME { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 compatible = "simple-bus"; 28 interrupt-parent = <&CP110_LABEL(icu)>; 29 ranges; 30 31 config-space@CP110_BASE { 32 #address-cells = <1>; 33 #size-cells = <1>; 34 compatible = "simple-bus"; 35 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>; 36 37 CP110_LABEL(ethernet): ethernet@0 { 38 compatible = "marvell,armada-7k-pp22"; 39 reg = <0x0 0x100000>, <0x129000 0xb000>; 40 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>, 41 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>, 42 <&CP110_LABEL(clk) 1 18>; 43 clock-names = "pp_clk", "gop_clk", 44 "mg_clk", "mg_core_clk", "axi_clk"; 45 marvell,system-controller = <&CP110_LABEL(syscon0)>; 46 status = "disabled"; 47 dma-coherent; 48 49 CP110_LABEL(eth0): eth0 { 50 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>, 51 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>, 52 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>, 53 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>, 54 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>, 55 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>; 56 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 57 "tx-cpu3", "rx-shared", "link"; 58 port-id = <0>; 59 gop-port-id = <0>; 60 status = "disabled"; 61 }; 62 63 CP110_LABEL(eth1): eth1 { 64 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>, 65 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>, 66 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>, 67 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>, 68 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>, 69 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>; 70 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 71 "tx-cpu3", "rx-shared", "link"; 72 port-id = <1>; 73 gop-port-id = <2>; 74 status = "disabled"; 75 }; 76 77 CP110_LABEL(eth2): eth2 { 78 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>, 79 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>, 80 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>, 81 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>, 82 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>, 83 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", 85 "tx-cpu3", "rx-shared", "link"; 86 port-id = <2>; 87 gop-port-id = <3>; 88 status = "disabled"; 89 }; 90 }; 91 92 CP110_LABEL(comphy): phy@120000 { 93 compatible = "marvell,comphy-cp110"; 94 reg = <0x120000 0x6000>; 95 marvell,system-controller = <&CP110_LABEL(syscon0)>; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 CP110_LABEL(comphy0): phy@0 { 100 reg = <0>; 101 #phy-cells = <1>; 102 }; 103 104 CP110_LABEL(comphy1): phy@1 { 105 reg = <1>; 106 #phy-cells = <1>; 107 }; 108 109 CP110_LABEL(comphy2): phy@2 { 110 reg = <2>; 111 #phy-cells = <1>; 112 }; 113 114 CP110_LABEL(comphy3): phy@3 { 115 reg = <3>; 116 #phy-cells = <1>; 117 }; 118 119 CP110_LABEL(comphy4): phy@4 { 120 reg = <4>; 121 #phy-cells = <1>; 122 }; 123 124 CP110_LABEL(comphy5): phy@5 { 125 reg = <5>; 126 #phy-cells = <1>; 127 }; 128 }; 129 130 CP110_LABEL(mdio): mdio@12a200 { 131 #address-cells = <1>; 132 #size-cells = <0>; 133 compatible = "marvell,orion-mdio"; 134 reg = <0x12a200 0x10>; 135 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>, 136 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 137 status = "disabled"; 138 }; 139 140 CP110_LABEL(xmdio): mdio@12a600 { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 compatible = "marvell,xmdio"; 144 reg = <0x12a600 0x10>; 145 clocks = <&CP110_LABEL(clk) 1 5>, 146 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>; 147 status = "disabled"; 148 }; 149 150 CP110_LABEL(icu): interrupt-controller@1e0000 { 151 compatible = "marvell,cp110-icu"; 152 reg = <0x1e0000 0x440>; 153 #interrupt-cells = <3>; 154 interrupt-controller; 155 msi-parent = <&gicp>; 156 }; 157 158 CP110_LABEL(rtc): rtc@284000 { 159 compatible = "marvell,armada-8k-rtc"; 160 reg = <0x284000 0x20>, <0x284080 0x24>; 161 reg-names = "rtc", "rtc-soc"; 162 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; 163 }; 164 165 CP110_LABEL(syscon0): system-controller@440000 { 166 compatible = "syscon", "simple-mfd"; 167 reg = <0x440000 0x2000>; 168 169 CP110_LABEL(clk): clock { 170 compatible = "marvell,cp110-clock"; 171 #clock-cells = <2>; 172 }; 173 174 CP110_LABEL(gpio1): gpio@100 { 175 compatible = "marvell,armada-8k-gpio"; 176 offset = <0x100>; 177 ngpios = <32>; 178 gpio-controller; 179 #gpio-cells = <2>; 180 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>; 181 interrupt-controller; 182 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>, 183 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>, 184 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>, 185 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>; 186 status = "disabled"; 187 }; 188 189 CP110_LABEL(gpio2): gpio@140 { 190 compatible = "marvell,armada-8k-gpio"; 191 offset = <0x140>; 192 ngpios = <31>; 193 gpio-controller; 194 #gpio-cells = <2>; 195 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>; 196 interrupt-controller; 197 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>, 198 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>, 199 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>, 200 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>; 201 status = "disabled"; 202 }; 203 }; 204 205 CP110_LABEL(syscon1): system-controller@400000 { 206 compatible = "syscon", "simple-mfd"; 207 reg = <0x400000 0x1000>; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 211 CP110_LABEL(thermal): thermal-sensor@70 { 212 compatible = "marvell,armada-cp110-thermal"; 213 reg = <0x70 0x10>; 214 }; 215 }; 216 217 CP110_LABEL(usb3_0): usb3@500000 { 218 compatible = "marvell,armada-8k-xhci", 219 "generic-xhci"; 220 reg = <0x500000 0x4000>; 221 dma-coherent; 222 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; 223 clock-names = "core", "reg"; 224 clocks = <&CP110_LABEL(clk) 1 22>, 225 <&CP110_LABEL(clk) 1 16>; 226 status = "disabled"; 227 }; 228 229 CP110_LABEL(usb3_1): usb3@510000 { 230 compatible = "marvell,armada-8k-xhci", 231 "generic-xhci"; 232 reg = <0x510000 0x4000>; 233 dma-coherent; 234 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>; 235 clock-names = "core", "reg"; 236 clocks = <&CP110_LABEL(clk) 1 23>, 237 <&CP110_LABEL(clk) 1 16>; 238 status = "disabled"; 239 }; 240 241 CP110_LABEL(sata0): sata@540000 { 242 compatible = "marvell,armada-8k-ahci", 243 "generic-ahci"; 244 reg = <0x540000 0x30000>; 245 dma-coherent; 246 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&CP110_LABEL(clk) 1 15>, 248 <&CP110_LABEL(clk) 1 16>; 249 status = "disabled"; 250 }; 251 252 CP110_LABEL(xor0): xor@6a0000 { 253 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 254 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; 255 dma-coherent; 256 msi-parent = <&gic_v2m0>; 257 clock-names = "core", "reg"; 258 clocks = <&CP110_LABEL(clk) 1 8>, 259 <&CP110_LABEL(clk) 1 14>; 260 }; 261 262 CP110_LABEL(xor1): xor@6c0000 { 263 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 264 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; 265 dma-coherent; 266 msi-parent = <&gic_v2m0>; 267 clock-names = "core", "reg"; 268 clocks = <&CP110_LABEL(clk) 1 7>, 269 <&CP110_LABEL(clk) 1 14>; 270 }; 271 272 CP110_LABEL(spi0): spi@700600 { 273 compatible = "marvell,armada-380-spi"; 274 reg = <0x700600 0x50>; 275 #address-cells = <0x1>; 276 #size-cells = <0x0>; 277 clock-names = "core", "axi"; 278 clocks = <&CP110_LABEL(clk) 1 21>, 279 <&CP110_LABEL(clk) 1 17>; 280 status = "disabled"; 281 }; 282 283 CP110_LABEL(spi1): spi@700680 { 284 compatible = "marvell,armada-380-spi"; 285 reg = <0x700680 0x50>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 clock-names = "core", "axi"; 289 clocks = <&CP110_LABEL(clk) 1 21>, 290 <&CP110_LABEL(clk) 1 17>; 291 status = "disabled"; 292 }; 293 294 CP110_LABEL(i2c0): i2c@701000 { 295 compatible = "marvell,mv78230-i2c"; 296 reg = <0x701000 0x20>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>; 300 clock-names = "core", "reg"; 301 clocks = <&CP110_LABEL(clk) 1 21>, 302 <&CP110_LABEL(clk) 1 17>; 303 status = "disabled"; 304 }; 305 306 CP110_LABEL(i2c1): i2c@701100 { 307 compatible = "marvell,mv78230-i2c"; 308 reg = <0x701100 0x20>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>; 312 clock-names = "core", "reg"; 313 clocks = <&CP110_LABEL(clk) 1 21>, 314 <&CP110_LABEL(clk) 1 17>; 315 status = "disabled"; 316 }; 317 318 CP110_LABEL(uart0): serial@702000 { 319 compatible = "snps,dw-apb-uart"; 320 reg = <0x702000 0x100>; 321 reg-shift = <2>; 322 interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>; 323 reg-io-width = <1>; 324 clock-names = "baudclk", "apb_pclk"; 325 clocks = <&CP110_LABEL(clk) 1 21>, 326 <&CP110_LABEL(clk) 1 17>; 327 status = "disabled"; 328 }; 329 330 CP110_LABEL(uart1): serial@702100 { 331 compatible = "snps,dw-apb-uart"; 332 reg = <0x702100 0x100>; 333 reg-shift = <2>; 334 interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>; 335 reg-io-width = <1>; 336 clock-names = "baudclk", "apb_pclk"; 337 clocks = <&CP110_LABEL(clk) 1 21>, 338 <&CP110_LABEL(clk) 1 17>; 339 status = "disabled"; 340 }; 341 342 CP110_LABEL(uart2): serial@702200 { 343 compatible = "snps,dw-apb-uart"; 344 reg = <0x702200 0x100>; 345 reg-shift = <2>; 346 interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>; 347 reg-io-width = <1>; 348 clock-names = "baudclk", "apb_pclk"; 349 clocks = <&CP110_LABEL(clk) 1 21>, 350 <&CP110_LABEL(clk) 1 17>; 351 status = "disabled"; 352 }; 353 354 CP110_LABEL(uart3): serial@702300 { 355 compatible = "snps,dw-apb-uart"; 356 reg = <0x702300 0x100>; 357 reg-shift = <2>; 358 interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>; 359 reg-io-width = <1>; 360 clock-names = "baudclk", "apb_pclk"; 361 clocks = <&CP110_LABEL(clk) 1 21>, 362 <&CP110_LABEL(clk) 1 17>; 363 status = "disabled"; 364 }; 365 366 CP110_LABEL(nand_controller): nand@720000 { 367 /* 368 * Due to the limitation of the pins available 369 * this controller is only usable on the CPM 370 * for A7K and on the CPS for A8K. 371 */ 372 compatible = "marvell,armada-8k-nand-controller", 373 "marvell,armada370-nand-controller"; 374 reg = <0x720000 0x54>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>; 378 clock-names = "core", "reg"; 379 clocks = <&CP110_LABEL(clk) 1 2>, 380 <&CP110_LABEL(clk) 1 17>; 381 marvell,system-controller = <&CP110_LABEL(syscon0)>; 382 status = "disabled"; 383 }; 384 385 CP110_LABEL(trng): trng@760000 { 386 compatible = "marvell,armada-8k-rng", 387 "inside-secure,safexcel-eip76"; 388 reg = <0x760000 0x7d>; 389 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>; 390 clock-names = "core", "reg"; 391 clocks = <&CP110_LABEL(clk) 1 25>, 392 <&CP110_LABEL(clk) 1 17>; 393 status = "okay"; 394 }; 395 396 CP110_LABEL(sdhci0): sdhci@780000 { 397 compatible = "marvell,armada-cp110-sdhci"; 398 reg = <0x780000 0x300>; 399 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>; 400 clock-names = "core", "axi"; 401 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>; 402 dma-coherent; 403 status = "disabled"; 404 }; 405 406 CP110_LABEL(crypto): crypto@800000 { 407 compatible = "inside-secure,safexcel-eip197b"; 408 reg = <0x800000 0x200000>; 409 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>, 410 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>, 411 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>, 412 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>, 413 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>, 414 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>; 415 interrupt-names = "mem", "ring0", "ring1", 416 "ring2", "ring3", "eip"; 417 clock-names = "core", "reg"; 418 clocks = <&CP110_LABEL(clk) 1 26>, 419 <&CP110_LABEL(clk) 1 17>; 420 dma-coherent; 421 }; 422 }; 423 424 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE { 425 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 426 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>, 427 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>; 428 reg-names = "ctrl", "config"; 429 #address-cells = <3>; 430 #size-cells = <2>; 431 #interrupt-cells = <1>; 432 device_type = "pci"; 433 dma-coherent; 434 msi-parent = <&gic_v2m0>; 435 436 bus-range = <0 0xff>; 437 ranges = 438 /* downstream I/O */ 439 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000 440 /* non-prefetchable memory */ 441 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>; 442 interrupt-map-mask = <0 0 0 0>; 443 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 444 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 445 num-lanes = <1>; 446 clock-names = "core", "reg"; 447 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>; 448 status = "disabled"; 449 }; 450 451 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE { 452 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 453 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>, 454 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>; 455 reg-names = "ctrl", "config"; 456 #address-cells = <3>; 457 #size-cells = <2>; 458 #interrupt-cells = <1>; 459 device_type = "pci"; 460 dma-coherent; 461 msi-parent = <&gic_v2m0>; 462 463 bus-range = <0 0xff>; 464 ranges = 465 /* downstream I/O */ 466 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000 467 /* non-prefetchable memory */ 468 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>; 469 interrupt-map-mask = <0 0 0 0>; 470 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 471 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 472 473 num-lanes = <1>; 474 clock-names = "core", "reg"; 475 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>; 476 status = "disabled"; 477 }; 478 479 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE { 480 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 481 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>, 482 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>; 483 reg-names = "ctrl", "config"; 484 #address-cells = <3>; 485 #size-cells = <2>; 486 #interrupt-cells = <1>; 487 device_type = "pci"; 488 dma-coherent; 489 msi-parent = <&gic_v2m0>; 490 491 bus-range = <0 0xff>; 492 ranges = 493 /* downstream I/O */ 494 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000 495 /* non-prefetchable memory */ 496 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>; 497 interrupt-map-mask = <0 0 0 0>; 498 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 499 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 500 501 num-lanes = <1>; 502 clock-names = "core", "reg"; 503 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>; 504 status = "disabled"; 505 }; 506}; 507