arm64: dts: imx8qxp: Add VPU subsystem file

[ Upstream commit 6bcd8b2fa2a9826fb6a849a9bfd7bdef145cabb6 ]

imx8qxp re-uses imx8qm VPU subsystem file, but it has different base
addresses. Also imx8qxp

arm64: dts: imx8qxp: Add VPU subsystem file

[ Upstream commit 6bcd8b2fa2a9826fb6a849a9bfd7bdef145cabb6 ]

imx8qxp re-uses imx8qm VPU subsystem file, but it has different base
addresses. Also imx8qxp has only two VPU cores, delete vpu_vore2 and
mu2_m0 accordingly.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stable-dep-of: eed2d8e8d005 ("arm64: dts: imx8-ss-vpu: Fix imx8qm VPU IRQs")
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: dts: imx8qm: Fix VPU core alias name

Alias names use dashes instead of underscores, fix this.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawn

arm64: dts: imx8qm: Fix VPU core alias name

Alias names use dashes instead of underscores, fix this.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: Update cache properties for freescale

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and S

arm64: dts: Update cache properties for freescale

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Chester Lin <clin@suse.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: freescale: imx8qxp: Fix the keys node name

The proper name is 'keys', not 'scu-keys'.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Sig

arm64: dts: freescale: imx8qxp: Fix the keys node name

The proper name is 'keys', not 'scu-keys'.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: freescale: imx8: Fix the system-controller node name

The proper name is 'system-controller', not 'scu'.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Shawn Guo <shaw

arm64: dts: freescale: imx8: Fix the system-controller node name

The proper name is 'system-controller', not 'scu'.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: freescale: imx8qxp: Fix the ocotp node name

The proper name is 'ocotp', not 'imx8qx-ocotp'.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.

arm64: dts: freescale: imx8qxp: Fix the ocotp node name

The proper name is 'ocotp', not 'imx8qx-ocotp'.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: freescale: imx8qxp: Add fallback compatible for clock controller

Both i.MX8QM and i.MX8DXL use the fallback fsl,scu-clk compatible.
They rely on the same driver generic part as the i.MX8

arm64: dts: freescale: imx8qxp: Add fallback compatible for clock controller

Both i.MX8QM and i.MX8DXL use the fallback fsl,scu-clk compatible.
They rely on the same driver generic part as the i.MX8QXP, so
lets add it to i.MX8QXP too, for consitency.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: freescale: imx8: Fix power controller name

The proper name is power-controller, not imx8qx-pd.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp

arm64: dts: freescale: imx8: Fix power controller name

The proper name is power-controller, not imx8qx-pd.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: freescale: imx8qxp: Remove unnecessary clock related entries

XTAL clocks are not exposed by SCU to OS via OS<->SCU communication protocol,
so remove unnecessary entries.

Signed-off-by:

arm64: dts: freescale: imx8qxp: Remove unnecessary clock related entries

XTAL clocks are not exposed by SCU to OS via OS<->SCU communication protocol,
so remove unnecessary entries.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: freescale: imx8qxp: Fix thermal zone name for cpu0

The proper name is cpu0-thermal, not cpu-thermal0, so change it to that.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: S

arm64: dts: freescale: imx8qxp: Fix thermal zone name for cpu0

The proper name is cpu0-thermal, not cpu-thermal0, so change it to that.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: freescale: imx8q: add imx vpu codec entries

Add the Video Processing Unit node for IMX8Q SoC.

Signed-off-by: Ming Qian <ming.qian@nxp.com>
Signed-off-by: Shijie Qin <shijie.qin@nxp.com>

arm64: dts: freescale: imx8q: add imx vpu codec entries

Add the Video Processing Unit node for IMX8Q SoC.

Signed-off-by: Ming Qian <ming.qian@nxp.com>
Signed-off-by: Shijie Qin <shijie.qin@nxp.com>
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8qxp: add cache info

i.MX8QXP A35 Cluster has 32KB Icache, 32KB Dcache and 512KB L2 Cache
- Icache is 2-way set associative
- Dcache is 4-way set associative
- L2cache is 8-way set

arm64: dts: imx8qxp: add cache info

i.MX8QXP A35 Cluster has 32KB Icache, 32KB Dcache and 512KB L2 Cache
- Icache is 2-way set associative
- Dcache is 4-way set associative
- L2cache is 8-way set associative
- Line size are 64bytes

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8qxp: update pmu compatible

i.MX8QXP features four Cortex-A35 cores, use more accurate
compatible.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kerne

arm64: dts: imx8qxp: update pmu compatible

i.MX8QXP features four Cortex-A35 cores, use more accurate
compatible.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8: Add jpeg encoder/decoder nodes

Add dts for imaging subsytem, include jpeg nodes here.
Tested on imx8qxp/qm.

Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Reviewed-by: Don

arm64: dts: imx8: Add jpeg encoder/decoder nodes

Add dts for imaging subsytem, include jpeg nodes here.
Tested on imx8qxp/qm.

Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8: split adma ss into dma and audio ss

amda ss is consisted of dma and audio ss in qxp which are
also used in qm.
Let's split them into two ss for better code reuse.

Signed-off-by: D

arm64: dts: imx8: split adma ss into dma and audio ss

amda ss is consisted of dma and audio ss in qxp which are
also used in qm.
Let's split them into two ss for better code reuse.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8: switch to new lpcg clock binding

switch to new lpcg clock binding

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

arm64: dts: imx8: switch to two cell scu clock binding

switch to two cell scu clock binding

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

arm64: dts: imx8qxp: orginize dts in subsystems

MX8 SoC is comprised of a few HW subsystems while some of them can be
reused in the different SoCs. So let's re-orginize them into subsystems
in devic

arm64: dts: imx8qxp: orginize dts in subsystems

MX8 SoC is comprised of a few HW subsystems while some of them can be
reused in the different SoCs. So let's re-orginize them into subsystems
in device tree as well for the possible reuse of the common part.

Note, as there's still no devices of hsio subsys, so removed it
first instead of creating a subsys headfile with no devices.
They will be added back when new devices added.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8qxp: move scu pd node before scu clock node

SCU clock depends on SCU Power domain. Moving scu pd node before
scu clock can save a hundred of defer probes of all system devices
which

arm64: dts: imx8qxp: move scu pd node before scu clock node

SCU clock depends on SCU Power domain. Moving scu pd node before
scu clock can save a hundred of defer probes of all system devices
which depends on power domain and clocks.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8qxp: add fallback compatible string for scu pd

According to binding doc, add the fallback compatible string for
scu pd.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.r

arm64: dts: imx8qxp: add fallback compatible string for scu pd

According to binding doc, add the fallback compatible string for
scu pd.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8qxp: correct usdhc clock-names sequence

Per dt-bindings, the clock-names sequence should be ipg ahb per to pass
dtbs_check.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by:

arm64: dts: imx8qxp: correct usdhc clock-names sequence

Per dt-bindings, the clock-names sequence should be ipg ahb per to pass
dtbs_check.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8qxp: Add ethernet alias

Add ethernet alias, so bootloader code can use this to find the
primary ethernet device, and set the MAC address.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

arm64: dts: imx8qxp: Add ethernet alias

Add ethernet alias, so bootloader code can use this to find the
primary ethernet device, and set the MAC address.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8qxp: add i2c aliases

The devices could be enumerated properly with aliases.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

arm64: dts: imx8qxp: add alias for lsio MU

Add lsio mu alias for all lsio MUs that could communicate with SCU,
imx_scu_enable_general_irq_channel will parse the alias to get
the mu resource id, if u

arm64: dts: imx8qxp: add alias for lsio MU

Add lsio mu alias for all lsio MUs that could communicate with SCU,
imx_scu_enable_general_irq_channel will parse the alias to get
the mu resource id, if using other MU, not MU1, the `mu_resource_id`
is not what we expect, so add alias to fix this issue.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8qxp: support scu mailbox channel

With mailbox driver support i.MX8 SCU MU channel, we could
use it to avoid trigger interrupts for each TR/RR registers
in one MU, instead, only one R

arm64: dts: imx8qxp: support scu mailbox channel

With mailbox driver support i.MX8 SCU MU channel, we could
use it to avoid trigger interrupts for each TR/RR registers
in one MU, instead, only one RX interrupt for a recv and
one TX interrupt for a send.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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