1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2020 NXP
5 *	Dong Aisheng <aisheng.dong@nxp.com>
6 */
7
8#include <dt-bindings/clock/imx8-clock.h>
9#include <dt-bindings/firmware/imx/rsrc.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/pinctrl/pads-imx8qxp.h>
14#include <dt-bindings/thermal/thermal.h>
15
16/ {
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		ethernet0 = &fec1;
23		ethernet1 = &fec2;
24		gpio0 = &lsio_gpio0;
25		gpio1 = &lsio_gpio1;
26		gpio2 = &lsio_gpio2;
27		gpio3 = &lsio_gpio3;
28		gpio4 = &lsio_gpio4;
29		gpio5 = &lsio_gpio5;
30		gpio6 = &lsio_gpio6;
31		gpio7 = &lsio_gpio7;
32		i2c0 = &adma_i2c0;
33		i2c1 = &adma_i2c1;
34		i2c2 = &adma_i2c2;
35		i2c3 = &adma_i2c3;
36		mmc0 = &usdhc1;
37		mmc1 = &usdhc2;
38		mmc2 = &usdhc3;
39		mu0 = &lsio_mu0;
40		mu1 = &lsio_mu1;
41		mu2 = &lsio_mu2;
42		mu3 = &lsio_mu3;
43		mu4 = &lsio_mu4;
44		serial0 = &adma_lpuart0;
45		serial1 = &adma_lpuart1;
46		serial2 = &adma_lpuart2;
47		serial3 = &adma_lpuart3;
48	};
49
50	cpus {
51		#address-cells = <2>;
52		#size-cells = <0>;
53
54		/* We have 1 clusters with 4 Cortex-A35 cores */
55		A35_0: cpu@0 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a35";
58			reg = <0x0 0x0>;
59			enable-method = "psci";
60			next-level-cache = <&A35_L2>;
61			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
62			operating-points-v2 = <&a35_opp_table>;
63			#cooling-cells = <2>;
64		};
65
66		A35_1: cpu@1 {
67			device_type = "cpu";
68			compatible = "arm,cortex-a35";
69			reg = <0x0 0x1>;
70			enable-method = "psci";
71			next-level-cache = <&A35_L2>;
72			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
73			operating-points-v2 = <&a35_opp_table>;
74			#cooling-cells = <2>;
75		};
76
77		A35_2: cpu@2 {
78			device_type = "cpu";
79			compatible = "arm,cortex-a35";
80			reg = <0x0 0x2>;
81			enable-method = "psci";
82			next-level-cache = <&A35_L2>;
83			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
84			operating-points-v2 = <&a35_opp_table>;
85			#cooling-cells = <2>;
86		};
87
88		A35_3: cpu@3 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a35";
91			reg = <0x0 0x3>;
92			enable-method = "psci";
93			next-level-cache = <&A35_L2>;
94			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
95			operating-points-v2 = <&a35_opp_table>;
96			#cooling-cells = <2>;
97		};
98
99		A35_L2: l2-cache0 {
100			compatible = "cache";
101		};
102	};
103
104	a35_opp_table: opp-table {
105		compatible = "operating-points-v2";
106		opp-shared;
107
108		opp-900000000 {
109			opp-hz = /bits/ 64 <900000000>;
110			opp-microvolt = <1000000>;
111			clock-latency-ns = <150000>;
112		};
113
114		opp-1200000000 {
115			opp-hz = /bits/ 64 <1200000000>;
116			opp-microvolt = <1100000>;
117			clock-latency-ns = <150000>;
118			opp-suspend;
119		};
120	};
121
122	gic: interrupt-controller@51a00000 {
123		compatible = "arm,gic-v3";
124		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
125		      <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
126		#interrupt-cells = <3>;
127		interrupt-controller;
128		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
129	};
130
131	reserved-memory {
132		#address-cells = <2>;
133		#size-cells = <2>;
134		ranges;
135
136		dsp_reserved: dsp@92400000 {
137			reg = <0 0x92400000 0 0x2000000>;
138			no-map;
139		};
140	};
141
142	pmu {
143		compatible = "arm,armv8-pmuv3";
144		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
145	};
146
147	psci {
148		compatible = "arm,psci-1.0";
149		method = "smc";
150	};
151
152	scu {
153		compatible = "fsl,imx-scu";
154		mbox-names = "tx0",
155			     "rx0",
156			     "gip3";
157		mboxes = <&lsio_mu1 0 0
158			  &lsio_mu1 1 0
159			  &lsio_mu1 3 3>;
160
161		pd: imx8qx-pd {
162			compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
163			#power-domain-cells = <1>;
164		};
165
166		clk: clock-controller {
167			compatible = "fsl,imx8qxp-clk";
168			#clock-cells = <2>;
169			clocks = <&xtal32k &xtal24m>;
170			clock-names = "xtal_32KHz", "xtal_24Mhz";
171		};
172
173		iomuxc: pinctrl {
174			compatible = "fsl,imx8qxp-iomuxc";
175		};
176
177		ocotp: imx8qx-ocotp {
178			compatible = "fsl,imx8qxp-scu-ocotp";
179			#address-cells = <1>;
180			#size-cells = <1>;
181		};
182
183		scu_key: scu-key {
184			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
185			linux,keycodes = <KEY_POWER>;
186			status = "disabled";
187		};
188
189		rtc: rtc {
190			compatible = "fsl,imx8qxp-sc-rtc";
191		};
192
193		watchdog {
194			compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
195			timeout-sec = <60>;
196		};
197
198		tsens: thermal-sensor {
199			compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
200			#thermal-sensor-cells = <1>;
201		};
202	};
203
204	timer {
205		compatible = "arm,armv8-timer";
206		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
207			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
208			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
209			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
210	};
211
212	xtal32k: clock-xtal32k {
213		compatible = "fixed-clock";
214		#clock-cells = <0>;
215		clock-frequency = <32768>;
216		clock-output-names = "xtal_32KHz";
217	};
218
219	xtal24m: clock-xtal24m {
220		compatible = "fixed-clock";
221		#clock-cells = <0>;
222		clock-frequency = <24000000>;
223		clock-output-names = "xtal_24MHz";
224	};
225
226	thermal_zones: thermal-zones {
227		cpu-thermal0 {
228			polling-delay-passive = <250>;
229			polling-delay = <2000>;
230			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
231
232			trips {
233				cpu_alert0: trip0 {
234					temperature = <107000>;
235					hysteresis = <2000>;
236					type = "passive";
237				};
238
239				cpu_crit0: trip1 {
240					temperature = <127000>;
241					hysteresis = <2000>;
242					type = "critical";
243				};
244			};
245
246			cooling-maps {
247				map0 {
248					trip = <&cpu_alert0>;
249					cooling-device =
250						<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
251						<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
252						<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
253						<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
254				};
255			};
256		};
257	};
258
259	/* sorted in register address */
260	#include "imx8-ss-adma.dtsi"
261	#include "imx8-ss-conn.dtsi"
262	#include "imx8-ss-ddr.dtsi"
263	#include "imx8-ss-lsio.dtsi"
264};
265
266#include "imx8qxp-ss-adma.dtsi"
267#include "imx8qxp-ss-conn.dtsi"
268#include "imx8qxp-ss-lsio.dtsi"
269