1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/pinctrl/pads-imx8qxp.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &lsio_gpio0; 23 gpio1 = &lsio_gpio1; 24 gpio2 = &lsio_gpio2; 25 gpio3 = &lsio_gpio3; 26 gpio4 = &lsio_gpio4; 27 gpio5 = &lsio_gpio5; 28 gpio6 = &lsio_gpio6; 29 gpio7 = &lsio_gpio7; 30 i2c0 = &adma_i2c0; 31 i2c1 = &adma_i2c1; 32 i2c2 = &adma_i2c2; 33 i2c3 = &adma_i2c3; 34 mmc0 = &usdhc1; 35 mmc1 = &usdhc2; 36 mmc2 = &usdhc3; 37 mu0 = &lsio_mu0; 38 mu1 = &lsio_mu1; 39 mu2 = &lsio_mu2; 40 mu3 = &lsio_mu3; 41 mu4 = &lsio_mu4; 42 serial0 = &adma_lpuart0; 43 serial1 = &adma_lpuart1; 44 serial2 = &adma_lpuart2; 45 serial3 = &adma_lpuart3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 /* We have 1 clusters with 4 Cortex-A35 cores */ 53 A35_0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a35"; 56 reg = <0x0 0x0>; 57 enable-method = "psci"; 58 next-level-cache = <&A35_L2>; 59 clocks = <&clk IMX_A35_CLK>; 60 operating-points-v2 = <&a35_opp_table>; 61 #cooling-cells = <2>; 62 }; 63 64 A35_1: cpu@1 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a35"; 67 reg = <0x0 0x1>; 68 enable-method = "psci"; 69 next-level-cache = <&A35_L2>; 70 clocks = <&clk IMX_A35_CLK>; 71 operating-points-v2 = <&a35_opp_table>; 72 #cooling-cells = <2>; 73 }; 74 75 A35_2: cpu@2 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a35"; 78 reg = <0x0 0x2>; 79 enable-method = "psci"; 80 next-level-cache = <&A35_L2>; 81 clocks = <&clk IMX_A35_CLK>; 82 operating-points-v2 = <&a35_opp_table>; 83 #cooling-cells = <2>; 84 }; 85 86 A35_3: cpu@3 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a35"; 89 reg = <0x0 0x3>; 90 enable-method = "psci"; 91 next-level-cache = <&A35_L2>; 92 clocks = <&clk IMX_A35_CLK>; 93 operating-points-v2 = <&a35_opp_table>; 94 #cooling-cells = <2>; 95 }; 96 97 A35_L2: l2-cache0 { 98 compatible = "cache"; 99 }; 100 }; 101 102 a35_opp_table: opp-table { 103 compatible = "operating-points-v2"; 104 opp-shared; 105 106 opp-900000000 { 107 opp-hz = /bits/ 64 <900000000>; 108 opp-microvolt = <1000000>; 109 clock-latency-ns = <150000>; 110 }; 111 112 opp-1200000000 { 113 opp-hz = /bits/ 64 <1200000000>; 114 opp-microvolt = <1100000>; 115 clock-latency-ns = <150000>; 116 opp-suspend; 117 }; 118 }; 119 120 gic: interrupt-controller@51a00000 { 121 compatible = "arm,gic-v3"; 122 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 123 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 124 #interrupt-cells = <3>; 125 interrupt-controller; 126 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 127 }; 128 129 reserved-memory { 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 134 dsp_reserved: dsp@92400000 { 135 reg = <0 0x92400000 0 0x2000000>; 136 no-map; 137 }; 138 }; 139 140 pmu { 141 compatible = "arm,armv8-pmuv3"; 142 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 143 }; 144 145 psci { 146 compatible = "arm,psci-1.0"; 147 method = "smc"; 148 }; 149 150 scu { 151 compatible = "fsl,imx-scu"; 152 mbox-names = "tx0", 153 "rx0", 154 "gip3"; 155 mboxes = <&lsio_mu1 0 0 156 &lsio_mu1 1 0 157 &lsio_mu1 3 3>; 158 159 clk: clock-controller { 160 compatible = "fsl,imx8qxp-clk"; 161 #clock-cells = <1>; 162 clocks = <&xtal32k &xtal24m>; 163 clock-names = "xtal_32KHz", "xtal_24Mhz"; 164 }; 165 166 iomuxc: pinctrl { 167 compatible = "fsl,imx8qxp-iomuxc"; 168 }; 169 170 ocotp: imx8qx-ocotp { 171 compatible = "fsl,imx8qxp-scu-ocotp"; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 }; 175 176 pd: imx8qx-pd { 177 compatible = "fsl,imx8qxp-scu-pd"; 178 #power-domain-cells = <1>; 179 }; 180 181 scu_key: scu-key { 182 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 183 linux,keycodes = <KEY_POWER>; 184 status = "disabled"; 185 }; 186 187 rtc: rtc { 188 compatible = "fsl,imx8qxp-sc-rtc"; 189 }; 190 191 watchdog { 192 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 193 timeout-sec = <60>; 194 }; 195 196 tsens: thermal-sensor { 197 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 198 #thermal-sensor-cells = <1>; 199 }; 200 }; 201 202 timer { 203 compatible = "arm,armv8-timer"; 204 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 205 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 206 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 207 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 208 }; 209 210 xtal32k: clock-xtal32k { 211 compatible = "fixed-clock"; 212 #clock-cells = <0>; 213 clock-frequency = <32768>; 214 clock-output-names = "xtal_32KHz"; 215 }; 216 217 xtal24m: clock-xtal24m { 218 compatible = "fixed-clock"; 219 #clock-cells = <0>; 220 clock-frequency = <24000000>; 221 clock-output-names = "xtal_24MHz"; 222 }; 223 224 adma_subsys: bus@59000000 { 225 compatible = "simple-bus"; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 229 230 adma_lpcg: clock-controller@59000000 { 231 compatible = "fsl,imx8qxp-lpcg-adma"; 232 reg = <0x59000000 0x2000000>; 233 #clock-cells = <1>; 234 }; 235 236 adma_dsp: dsp@596e8000 { 237 compatible = "fsl,imx8qxp-dsp"; 238 reg = <0x596e8000 0x88000>; 239 clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, 240 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, 241 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; 242 clock-names = "ipg", "ocram", "core"; 243 power-domains = <&pd IMX_SC_R_MU_13A>, 244 <&pd IMX_SC_R_MU_13B>, 245 <&pd IMX_SC_R_DSP>, 246 <&pd IMX_SC_R_DSP_RAM>; 247 mbox-names = "txdb0", "txdb1", 248 "rxdb0", "rxdb1"; 249 mboxes = <&lsio_mu13 2 0>, 250 <&lsio_mu13 2 1>, 251 <&lsio_mu13 3 0>, 252 <&lsio_mu13 3 1>; 253 memory-region = <&dsp_reserved>; 254 status = "disabled"; 255 }; 256 257 adma_lpuart0: serial@5a060000 { 258 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 259 reg = <0x5a060000 0x1000>; 260 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, 262 <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 263 clock-names = "ipg", "baud"; 264 power-domains = <&pd IMX_SC_R_UART_0>; 265 status = "disabled"; 266 }; 267 268 adma_lpuart1: serial@5a070000 { 269 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 270 reg = <0x5a070000 0x1000>; 271 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, 273 <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 274 clock-names = "ipg", "baud"; 275 power-domains = <&pd IMX_SC_R_UART_1>; 276 status = "disabled"; 277 }; 278 279 adma_lpuart2: serial@5a080000 { 280 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 281 reg = <0x5a080000 0x1000>; 282 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, 284 <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 285 clock-names = "ipg", "baud"; 286 power-domains = <&pd IMX_SC_R_UART_2>; 287 status = "disabled"; 288 }; 289 290 adma_lpuart3: serial@5a090000 { 291 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 292 reg = <0x5a090000 0x1000>; 293 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, 295 <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 296 clock-names = "ipg", "baud"; 297 power-domains = <&pd IMX_SC_R_UART_3>; 298 status = "disabled"; 299 }; 300 301 adma_i2c0: i2c@5a800000 { 302 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 303 reg = <0x5a800000 0x4000>; 304 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 306 clock-names = "per"; 307 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 308 assigned-clock-rates = <24000000>; 309 power-domains = <&pd IMX_SC_R_I2C_0>; 310 status = "disabled"; 311 }; 312 313 adma_i2c1: i2c@5a810000 { 314 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 315 reg = <0x5a810000 0x4000>; 316 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 318 clock-names = "per"; 319 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 320 assigned-clock-rates = <24000000>; 321 power-domains = <&pd IMX_SC_R_I2C_1>; 322 status = "disabled"; 323 }; 324 325 adma_i2c2: i2c@5a820000 { 326 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 327 reg = <0x5a820000 0x4000>; 328 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 330 clock-names = "per"; 331 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 332 assigned-clock-rates = <24000000>; 333 power-domains = <&pd IMX_SC_R_I2C_2>; 334 status = "disabled"; 335 }; 336 337 adma_i2c3: i2c@5a830000 { 338 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 339 reg = <0x5a830000 0x4000>; 340 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 342 clock-names = "per"; 343 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 344 assigned-clock-rates = <24000000>; 345 power-domains = <&pd IMX_SC_R_I2C_3>; 346 status = "disabled"; 347 }; 348 }; 349 350 conn_subsys: bus@5b000000 { 351 compatible = "simple-bus"; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 355 356 conn_lpcg: clock-controller@5b200000 { 357 compatible = "fsl,imx8qxp-lpcg-conn"; 358 reg = <0x5b200000 0xb0000>; 359 #clock-cells = <1>; 360 }; 361 362 usdhc1: mmc@5b010000 { 363 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 364 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 365 reg = <0x5b010000 0x10000>; 366 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 367 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 368 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 369 clock-names = "ipg", "per", "ahb"; 370 power-domains = <&pd IMX_SC_R_SDHC_0>; 371 status = "disabled"; 372 }; 373 374 usdhc2: mmc@5b020000 { 375 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 376 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 377 reg = <0x5b020000 0x10000>; 378 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 379 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 380 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 381 clock-names = "ipg", "per", "ahb"; 382 power-domains = <&pd IMX_SC_R_SDHC_1>; 383 fsl,tuning-start-tap = <20>; 384 fsl,tuning-step= <2>; 385 status = "disabled"; 386 }; 387 388 usdhc3: mmc@5b030000 { 389 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 390 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 391 reg = <0x5b030000 0x10000>; 392 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 393 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 394 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 395 clock-names = "ipg", "per", "ahb"; 396 power-domains = <&pd IMX_SC_R_SDHC_2>; 397 status = "disabled"; 398 }; 399 400 fec1: ethernet@5b040000 { 401 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 402 reg = <0x5b040000 0x10000>; 403 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 408 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 409 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 410 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 411 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 412 fsl,num-tx-queues=<3>; 413 fsl,num-rx-queues=<3>; 414 power-domains = <&pd IMX_SC_R_ENET_0>; 415 status = "disabled"; 416 }; 417 418 fec2: ethernet@5b050000 { 419 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 420 reg = <0x5b050000 0x10000>; 421 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 426 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 427 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 428 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 429 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 430 fsl,num-tx-queues=<3>; 431 fsl,num-rx-queues=<3>; 432 power-domains = <&pd IMX_SC_R_ENET_1>; 433 status = "disabled"; 434 }; 435 }; 436 437 ddr_subsyss: bus@5c000000 { 438 compatible = "simple-bus"; 439 #address-cells = <1>; 440 #size-cells = <1>; 441 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; 442 443 ddr-pmu@5c020000 { 444 compatible = "fsl,imx8-ddr-pmu"; 445 reg = <0x5c020000 0x10000>; 446 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 447 }; 448 }; 449 450 lsio_subsys: bus@5d000000 { 451 compatible = "simple-bus"; 452 #address-cells = <1>; 453 #size-cells = <1>; 454 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 455 456 lsio_gpio0: gpio@5d080000 { 457 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 458 reg = <0x5d080000 0x10000>; 459 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 460 gpio-controller; 461 #gpio-cells = <2>; 462 interrupt-controller; 463 #interrupt-cells = <2>; 464 power-domains = <&pd IMX_SC_R_GPIO_0>; 465 }; 466 467 lsio_gpio1: gpio@5d090000 { 468 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 469 reg = <0x5d090000 0x10000>; 470 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 471 gpio-controller; 472 #gpio-cells = <2>; 473 interrupt-controller; 474 #interrupt-cells = <2>; 475 power-domains = <&pd IMX_SC_R_GPIO_1>; 476 }; 477 478 lsio_gpio2: gpio@5d0a0000 { 479 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 480 reg = <0x5d0a0000 0x10000>; 481 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 482 gpio-controller; 483 #gpio-cells = <2>; 484 interrupt-controller; 485 #interrupt-cells = <2>; 486 power-domains = <&pd IMX_SC_R_GPIO_2>; 487 }; 488 489 lsio_gpio3: gpio@5d0b0000 { 490 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 491 reg = <0x5d0b0000 0x10000>; 492 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 493 gpio-controller; 494 #gpio-cells = <2>; 495 interrupt-controller; 496 #interrupt-cells = <2>; 497 power-domains = <&pd IMX_SC_R_GPIO_3>; 498 }; 499 500 lsio_gpio4: gpio@5d0c0000 { 501 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 502 reg = <0x5d0c0000 0x10000>; 503 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 504 gpio-controller; 505 #gpio-cells = <2>; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 power-domains = <&pd IMX_SC_R_GPIO_4>; 509 }; 510 511 lsio_gpio5: gpio@5d0d0000 { 512 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 513 reg = <0x5d0d0000 0x10000>; 514 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 515 gpio-controller; 516 #gpio-cells = <2>; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 power-domains = <&pd IMX_SC_R_GPIO_5>; 520 }; 521 522 lsio_gpio6: gpio@5d0e0000 { 523 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 524 reg = <0x5d0e0000 0x10000>; 525 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 526 gpio-controller; 527 #gpio-cells = <2>; 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 power-domains = <&pd IMX_SC_R_GPIO_6>; 531 }; 532 533 lsio_gpio7: gpio@5d0f0000 { 534 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 535 reg = <0x5d0f0000 0x10000>; 536 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 537 gpio-controller; 538 #gpio-cells = <2>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 power-domains = <&pd IMX_SC_R_GPIO_7>; 542 }; 543 544 lsio_mu0: mailbox@5d1b0000 { 545 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 546 reg = <0x5d1b0000 0x10000>; 547 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 548 #mbox-cells = <2>; 549 status = "disabled"; 550 }; 551 552 lsio_mu1: mailbox@5d1c0000 { 553 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 554 reg = <0x5d1c0000 0x10000>; 555 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 556 #mbox-cells = <2>; 557 }; 558 559 lsio_mu2: mailbox@5d1d0000 { 560 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 561 reg = <0x5d1d0000 0x10000>; 562 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 563 #mbox-cells = <2>; 564 status = "disabled"; 565 }; 566 567 lsio_mu3: mailbox@5d1e0000 { 568 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 569 reg = <0x5d1e0000 0x10000>; 570 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 571 #mbox-cells = <2>; 572 status = "disabled"; 573 }; 574 575 lsio_mu4: mailbox@5d1f0000 { 576 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 577 reg = <0x5d1f0000 0x10000>; 578 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 579 #mbox-cells = <2>; 580 status = "disabled"; 581 }; 582 583 lsio_mu13: mailbox@5d280000 { 584 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 585 reg = <0x5d280000 0x10000>; 586 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 587 #mbox-cells = <2>; 588 power-domains = <&pd IMX_SC_R_MU_13A>; 589 }; 590 591 lsio_lpcg: clock-controller@5d400000 { 592 compatible = "fsl,imx8qxp-lpcg-lsio"; 593 reg = <0x5d400000 0x400000>; 594 #clock-cells = <1>; 595 }; 596 }; 597 598 thermal_zones: thermal-zones { 599 cpu-thermal0 { 600 polling-delay-passive = <250>; 601 polling-delay = <2000>; 602 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 603 604 trips { 605 cpu_alert0: trip0 { 606 temperature = <107000>; 607 hysteresis = <2000>; 608 type = "passive"; 609 }; 610 611 cpu_crit0: trip1 { 612 temperature = <127000>; 613 hysteresis = <2000>; 614 type = "critical"; 615 }; 616 }; 617 618 cooling-maps { 619 map0 { 620 trip = <&cpu_alert0>; 621 cooling-device = 622 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 623 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 624 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 625 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 626 }; 627 }; 628 }; 629 }; 630}; 631