1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/pinctrl/pads-imx8qxp.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &lsio_gpio0; 23 gpio1 = &lsio_gpio1; 24 gpio2 = &lsio_gpio2; 25 gpio3 = &lsio_gpio3; 26 gpio4 = &lsio_gpio4; 27 gpio5 = &lsio_gpio5; 28 gpio6 = &lsio_gpio6; 29 gpio7 = &lsio_gpio7; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc3; 33 mu0 = &lsio_mu0; 34 mu1 = &lsio_mu1; 35 mu2 = &lsio_mu2; 36 mu3 = &lsio_mu3; 37 mu4 = &lsio_mu4; 38 serial0 = &adma_lpuart0; 39 serial1 = &adma_lpuart1; 40 serial2 = &adma_lpuart2; 41 serial3 = &adma_lpuart3; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 /* We have 1 clusters with 4 Cortex-A35 cores */ 49 A35_0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a35"; 52 reg = <0x0 0x0>; 53 enable-method = "psci"; 54 next-level-cache = <&A35_L2>; 55 clocks = <&clk IMX_A35_CLK>; 56 operating-points-v2 = <&a35_opp_table>; 57 #cooling-cells = <2>; 58 }; 59 60 A35_1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a35"; 63 reg = <0x0 0x1>; 64 enable-method = "psci"; 65 next-level-cache = <&A35_L2>; 66 clocks = <&clk IMX_A35_CLK>; 67 operating-points-v2 = <&a35_opp_table>; 68 #cooling-cells = <2>; 69 }; 70 71 A35_2: cpu@2 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a35"; 74 reg = <0x0 0x2>; 75 enable-method = "psci"; 76 next-level-cache = <&A35_L2>; 77 clocks = <&clk IMX_A35_CLK>; 78 operating-points-v2 = <&a35_opp_table>; 79 #cooling-cells = <2>; 80 }; 81 82 A35_3: cpu@3 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a35"; 85 reg = <0x0 0x3>; 86 enable-method = "psci"; 87 next-level-cache = <&A35_L2>; 88 clocks = <&clk IMX_A35_CLK>; 89 operating-points-v2 = <&a35_opp_table>; 90 #cooling-cells = <2>; 91 }; 92 93 A35_L2: l2-cache0 { 94 compatible = "cache"; 95 }; 96 }; 97 98 a35_opp_table: opp-table { 99 compatible = "operating-points-v2"; 100 opp-shared; 101 102 opp-900000000 { 103 opp-hz = /bits/ 64 <900000000>; 104 opp-microvolt = <1000000>; 105 clock-latency-ns = <150000>; 106 }; 107 108 opp-1200000000 { 109 opp-hz = /bits/ 64 <1200000000>; 110 opp-microvolt = <1100000>; 111 clock-latency-ns = <150000>; 112 opp-suspend; 113 }; 114 }; 115 116 gic: interrupt-controller@51a00000 { 117 compatible = "arm,gic-v3"; 118 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 119 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 120 #interrupt-cells = <3>; 121 interrupt-controller; 122 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 123 }; 124 125 reserved-memory { 126 #address-cells = <2>; 127 #size-cells = <2>; 128 ranges; 129 130 dsp_reserved: dsp@92400000 { 131 reg = <0 0x92400000 0 0x2000000>; 132 no-map; 133 }; 134 }; 135 136 pmu { 137 compatible = "arm,armv8-pmuv3"; 138 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 139 }; 140 141 psci { 142 compatible = "arm,psci-1.0"; 143 method = "smc"; 144 }; 145 146 scu { 147 compatible = "fsl,imx-scu"; 148 mbox-names = "tx0", 149 "rx0", 150 "gip3"; 151 mboxes = <&lsio_mu1 0 0 152 &lsio_mu1 1 0 153 &lsio_mu1 3 3>; 154 155 clk: clock-controller { 156 compatible = "fsl,imx8qxp-clk"; 157 #clock-cells = <1>; 158 clocks = <&xtal32k &xtal24m>; 159 clock-names = "xtal_32KHz", "xtal_24Mhz"; 160 }; 161 162 iomuxc: pinctrl { 163 compatible = "fsl,imx8qxp-iomuxc"; 164 }; 165 166 ocotp: imx8qx-ocotp { 167 compatible = "fsl,imx8qxp-scu-ocotp"; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 }; 171 172 pd: imx8qx-pd { 173 compatible = "fsl,imx8qxp-scu-pd"; 174 #power-domain-cells = <1>; 175 }; 176 177 scu_key: scu-key { 178 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 179 linux,keycodes = <KEY_POWER>; 180 status = "disabled"; 181 }; 182 183 rtc: rtc { 184 compatible = "fsl,imx8qxp-sc-rtc"; 185 }; 186 187 watchdog { 188 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 189 timeout-sec = <60>; 190 }; 191 192 tsens: thermal-sensor { 193 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 194 #thermal-sensor-cells = <1>; 195 }; 196 }; 197 198 timer { 199 compatible = "arm,armv8-timer"; 200 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 201 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 202 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 203 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 204 }; 205 206 xtal32k: clock-xtal32k { 207 compatible = "fixed-clock"; 208 #clock-cells = <0>; 209 clock-frequency = <32768>; 210 clock-output-names = "xtal_32KHz"; 211 }; 212 213 xtal24m: clock-xtal24m { 214 compatible = "fixed-clock"; 215 #clock-cells = <0>; 216 clock-frequency = <24000000>; 217 clock-output-names = "xtal_24MHz"; 218 }; 219 220 adma_subsys: bus@59000000 { 221 compatible = "simple-bus"; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 225 226 adma_lpcg: clock-controller@59000000 { 227 compatible = "fsl,imx8qxp-lpcg-adma"; 228 reg = <0x59000000 0x2000000>; 229 #clock-cells = <1>; 230 }; 231 232 adma_dsp: dsp@596e8000 { 233 compatible = "fsl,imx8qxp-dsp"; 234 reg = <0x596e8000 0x88000>; 235 clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, 236 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, 237 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; 238 clock-names = "ipg", "ocram", "core"; 239 power-domains = <&pd IMX_SC_R_MU_13A>, 240 <&pd IMX_SC_R_MU_13B>, 241 <&pd IMX_SC_R_DSP>, 242 <&pd IMX_SC_R_DSP_RAM>; 243 mbox-names = "txdb0", "txdb1", 244 "rxdb0", "rxdb1"; 245 mboxes = <&lsio_mu13 2 0>, 246 <&lsio_mu13 2 1>, 247 <&lsio_mu13 3 0>, 248 <&lsio_mu13 3 1>; 249 memory-region = <&dsp_reserved>; 250 status = "disabled"; 251 }; 252 253 adma_lpuart0: serial@5a060000 { 254 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 255 reg = <0x5a060000 0x1000>; 256 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, 258 <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 259 clock-names = "ipg", "baud"; 260 power-domains = <&pd IMX_SC_R_UART_0>; 261 status = "disabled"; 262 }; 263 264 adma_lpuart1: serial@5a070000 { 265 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 266 reg = <0x5a070000 0x1000>; 267 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, 269 <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 270 clock-names = "ipg", "baud"; 271 power-domains = <&pd IMX_SC_R_UART_1>; 272 status = "disabled"; 273 }; 274 275 adma_lpuart2: serial@5a080000 { 276 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 277 reg = <0x5a080000 0x1000>; 278 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, 280 <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 281 clock-names = "ipg", "baud"; 282 power-domains = <&pd IMX_SC_R_UART_2>; 283 status = "disabled"; 284 }; 285 286 adma_lpuart3: serial@5a090000 { 287 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 288 reg = <0x5a090000 0x1000>; 289 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, 291 <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 292 clock-names = "ipg", "baud"; 293 power-domains = <&pd IMX_SC_R_UART_3>; 294 status = "disabled"; 295 }; 296 297 adma_i2c0: i2c@5a800000 { 298 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 299 reg = <0x5a800000 0x4000>; 300 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 302 clock-names = "per"; 303 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 304 assigned-clock-rates = <24000000>; 305 power-domains = <&pd IMX_SC_R_I2C_0>; 306 status = "disabled"; 307 }; 308 309 adma_i2c1: i2c@5a810000 { 310 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 311 reg = <0x5a810000 0x4000>; 312 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 314 clock-names = "per"; 315 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 316 assigned-clock-rates = <24000000>; 317 power-domains = <&pd IMX_SC_R_I2C_1>; 318 status = "disabled"; 319 }; 320 321 adma_i2c2: i2c@5a820000 { 322 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 323 reg = <0x5a820000 0x4000>; 324 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 326 clock-names = "per"; 327 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 328 assigned-clock-rates = <24000000>; 329 power-domains = <&pd IMX_SC_R_I2C_2>; 330 status = "disabled"; 331 }; 332 333 adma_i2c3: i2c@5a830000 { 334 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 335 reg = <0x5a830000 0x4000>; 336 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 338 clock-names = "per"; 339 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 340 assigned-clock-rates = <24000000>; 341 power-domains = <&pd IMX_SC_R_I2C_3>; 342 status = "disabled"; 343 }; 344 }; 345 346 conn_subsys: bus@5b000000 { 347 compatible = "simple-bus"; 348 #address-cells = <1>; 349 #size-cells = <1>; 350 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 351 352 conn_lpcg: clock-controller@5b200000 { 353 compatible = "fsl,imx8qxp-lpcg-conn"; 354 reg = <0x5b200000 0xb0000>; 355 #clock-cells = <1>; 356 }; 357 358 usdhc1: mmc@5b010000 { 359 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 360 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 361 reg = <0x5b010000 0x10000>; 362 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 363 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 364 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 365 clock-names = "ipg", "per", "ahb"; 366 power-domains = <&pd IMX_SC_R_SDHC_0>; 367 status = "disabled"; 368 }; 369 370 usdhc2: mmc@5b020000 { 371 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 372 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 373 reg = <0x5b020000 0x10000>; 374 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 375 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 376 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 377 clock-names = "ipg", "per", "ahb"; 378 power-domains = <&pd IMX_SC_R_SDHC_1>; 379 fsl,tuning-start-tap = <20>; 380 fsl,tuning-step= <2>; 381 status = "disabled"; 382 }; 383 384 usdhc3: mmc@5b030000 { 385 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 386 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 387 reg = <0x5b030000 0x10000>; 388 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 389 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 390 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 391 clock-names = "ipg", "per", "ahb"; 392 power-domains = <&pd IMX_SC_R_SDHC_2>; 393 status = "disabled"; 394 }; 395 396 fec1: ethernet@5b040000 { 397 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 398 reg = <0x5b040000 0x10000>; 399 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 404 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 405 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 406 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 407 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 408 fsl,num-tx-queues=<3>; 409 fsl,num-rx-queues=<3>; 410 power-domains = <&pd IMX_SC_R_ENET_0>; 411 status = "disabled"; 412 }; 413 414 fec2: ethernet@5b050000 { 415 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 416 reg = <0x5b050000 0x10000>; 417 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 422 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 423 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 424 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 425 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 426 fsl,num-tx-queues=<3>; 427 fsl,num-rx-queues=<3>; 428 power-domains = <&pd IMX_SC_R_ENET_1>; 429 status = "disabled"; 430 }; 431 }; 432 433 ddr_subsyss: bus@5c000000 { 434 compatible = "simple-bus"; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; 438 439 ddr-pmu@5c020000 { 440 compatible = "fsl,imx8-ddr-pmu"; 441 reg = <0x5c020000 0x10000>; 442 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 443 }; 444 }; 445 446 lsio_subsys: bus@5d000000 { 447 compatible = "simple-bus"; 448 #address-cells = <1>; 449 #size-cells = <1>; 450 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 451 452 lsio_gpio0: gpio@5d080000 { 453 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 454 reg = <0x5d080000 0x10000>; 455 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 456 gpio-controller; 457 #gpio-cells = <2>; 458 interrupt-controller; 459 #interrupt-cells = <2>; 460 power-domains = <&pd IMX_SC_R_GPIO_0>; 461 }; 462 463 lsio_gpio1: gpio@5d090000 { 464 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 465 reg = <0x5d090000 0x10000>; 466 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 power-domains = <&pd IMX_SC_R_GPIO_1>; 472 }; 473 474 lsio_gpio2: gpio@5d0a0000 { 475 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 476 reg = <0x5d0a0000 0x10000>; 477 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 478 gpio-controller; 479 #gpio-cells = <2>; 480 interrupt-controller; 481 #interrupt-cells = <2>; 482 power-domains = <&pd IMX_SC_R_GPIO_2>; 483 }; 484 485 lsio_gpio3: gpio@5d0b0000 { 486 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 487 reg = <0x5d0b0000 0x10000>; 488 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 489 gpio-controller; 490 #gpio-cells = <2>; 491 interrupt-controller; 492 #interrupt-cells = <2>; 493 power-domains = <&pd IMX_SC_R_GPIO_3>; 494 }; 495 496 lsio_gpio4: gpio@5d0c0000 { 497 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 498 reg = <0x5d0c0000 0x10000>; 499 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 500 gpio-controller; 501 #gpio-cells = <2>; 502 interrupt-controller; 503 #interrupt-cells = <2>; 504 power-domains = <&pd IMX_SC_R_GPIO_4>; 505 }; 506 507 lsio_gpio5: gpio@5d0d0000 { 508 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 509 reg = <0x5d0d0000 0x10000>; 510 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 511 gpio-controller; 512 #gpio-cells = <2>; 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 power-domains = <&pd IMX_SC_R_GPIO_5>; 516 }; 517 518 lsio_gpio6: gpio@5d0e0000 { 519 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 520 reg = <0x5d0e0000 0x10000>; 521 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 522 gpio-controller; 523 #gpio-cells = <2>; 524 interrupt-controller; 525 #interrupt-cells = <2>; 526 power-domains = <&pd IMX_SC_R_GPIO_6>; 527 }; 528 529 lsio_gpio7: gpio@5d0f0000 { 530 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 531 reg = <0x5d0f0000 0x10000>; 532 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 533 gpio-controller; 534 #gpio-cells = <2>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 power-domains = <&pd IMX_SC_R_GPIO_7>; 538 }; 539 540 lsio_mu0: mailbox@5d1b0000 { 541 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 542 reg = <0x5d1b0000 0x10000>; 543 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 544 #mbox-cells = <2>; 545 status = "disabled"; 546 }; 547 548 lsio_mu1: mailbox@5d1c0000 { 549 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 550 reg = <0x5d1c0000 0x10000>; 551 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 552 #mbox-cells = <2>; 553 }; 554 555 lsio_mu2: mailbox@5d1d0000 { 556 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 557 reg = <0x5d1d0000 0x10000>; 558 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 559 #mbox-cells = <2>; 560 status = "disabled"; 561 }; 562 563 lsio_mu3: mailbox@5d1e0000 { 564 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 565 reg = <0x5d1e0000 0x10000>; 566 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 567 #mbox-cells = <2>; 568 status = "disabled"; 569 }; 570 571 lsio_mu4: mailbox@5d1f0000 { 572 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 573 reg = <0x5d1f0000 0x10000>; 574 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 575 #mbox-cells = <2>; 576 status = "disabled"; 577 }; 578 579 lsio_mu13: mailbox@5d280000 { 580 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 581 reg = <0x5d280000 0x10000>; 582 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 583 #mbox-cells = <2>; 584 power-domains = <&pd IMX_SC_R_MU_13A>; 585 }; 586 587 lsio_lpcg: clock-controller@5d400000 { 588 compatible = "fsl,imx8qxp-lpcg-lsio"; 589 reg = <0x5d400000 0x400000>; 590 #clock-cells = <1>; 591 }; 592 }; 593 594 thermal_zones: thermal-zones { 595 cpu-thermal0 { 596 polling-delay-passive = <250>; 597 polling-delay = <2000>; 598 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 599 600 trips { 601 cpu_alert0: trip0 { 602 temperature = <107000>; 603 hysteresis = <2000>; 604 type = "passive"; 605 }; 606 607 cpu_crit0: trip1 { 608 temperature = <127000>; 609 hysteresis = <2000>; 610 type = "critical"; 611 }; 612 }; 613 614 cooling-maps { 615 map0 { 616 trip = <&cpu_alert0>; 617 cooling-device = 618 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 619 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 620 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 621 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 622 }; 623 }; 624 }; 625 }; 626}; 627