1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/pinctrl/pads-imx8qxp.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 ethernet1 = &fec2; 24 gpio0 = &lsio_gpio0; 25 gpio1 = &lsio_gpio1; 26 gpio2 = &lsio_gpio2; 27 gpio3 = &lsio_gpio3; 28 gpio4 = &lsio_gpio4; 29 gpio5 = &lsio_gpio5; 30 gpio6 = &lsio_gpio6; 31 gpio7 = &lsio_gpio7; 32 i2c0 = &adma_i2c0; 33 i2c1 = &adma_i2c1; 34 i2c2 = &adma_i2c2; 35 i2c3 = &adma_i2c3; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 mu0 = &lsio_mu0; 40 mu1 = &lsio_mu1; 41 mu2 = &lsio_mu2; 42 mu3 = &lsio_mu3; 43 mu4 = &lsio_mu4; 44 serial0 = &adma_lpuart0; 45 serial1 = &adma_lpuart1; 46 serial2 = &adma_lpuart2; 47 serial3 = &adma_lpuart3; 48 }; 49 50 cpus { 51 #address-cells = <2>; 52 #size-cells = <0>; 53 54 /* We have 1 clusters with 4 Cortex-A35 cores */ 55 A35_0: cpu@0 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35"; 58 reg = <0x0 0x0>; 59 enable-method = "psci"; 60 next-level-cache = <&A35_L2>; 61 clocks = <&clk IMX_A35_CLK>; 62 operating-points-v2 = <&a35_opp_table>; 63 #cooling-cells = <2>; 64 }; 65 66 A35_1: cpu@1 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x1>; 70 enable-method = "psci"; 71 next-level-cache = <&A35_L2>; 72 clocks = <&clk IMX_A35_CLK>; 73 operating-points-v2 = <&a35_opp_table>; 74 #cooling-cells = <2>; 75 }; 76 77 A35_2: cpu@2 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a35"; 80 reg = <0x0 0x2>; 81 enable-method = "psci"; 82 next-level-cache = <&A35_L2>; 83 clocks = <&clk IMX_A35_CLK>; 84 operating-points-v2 = <&a35_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A35_3: cpu@3 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a35"; 91 reg = <0x0 0x3>; 92 enable-method = "psci"; 93 next-level-cache = <&A35_L2>; 94 clocks = <&clk IMX_A35_CLK>; 95 operating-points-v2 = <&a35_opp_table>; 96 #cooling-cells = <2>; 97 }; 98 99 A35_L2: l2-cache0 { 100 compatible = "cache"; 101 }; 102 }; 103 104 a35_opp_table: opp-table { 105 compatible = "operating-points-v2"; 106 opp-shared; 107 108 opp-900000000 { 109 opp-hz = /bits/ 64 <900000000>; 110 opp-microvolt = <1000000>; 111 clock-latency-ns = <150000>; 112 }; 113 114 opp-1200000000 { 115 opp-hz = /bits/ 64 <1200000000>; 116 opp-microvolt = <1100000>; 117 clock-latency-ns = <150000>; 118 opp-suspend; 119 }; 120 }; 121 122 gic: interrupt-controller@51a00000 { 123 compatible = "arm,gic-v3"; 124 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 125 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 126 #interrupt-cells = <3>; 127 interrupt-controller; 128 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 129 }; 130 131 reserved-memory { 132 #address-cells = <2>; 133 #size-cells = <2>; 134 ranges; 135 136 dsp_reserved: dsp@92400000 { 137 reg = <0 0x92400000 0 0x2000000>; 138 no-map; 139 }; 140 }; 141 142 pmu { 143 compatible = "arm,armv8-pmuv3"; 144 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 145 }; 146 147 psci { 148 compatible = "arm,psci-1.0"; 149 method = "smc"; 150 }; 151 152 scu { 153 compatible = "fsl,imx-scu"; 154 mbox-names = "tx0", 155 "rx0", 156 "gip3"; 157 mboxes = <&lsio_mu1 0 0 158 &lsio_mu1 1 0 159 &lsio_mu1 3 3>; 160 161 clk: clock-controller { 162 compatible = "fsl,imx8qxp-clk"; 163 #clock-cells = <1>; 164 clocks = <&xtal32k &xtal24m>; 165 clock-names = "xtal_32KHz", "xtal_24Mhz"; 166 }; 167 168 iomuxc: pinctrl { 169 compatible = "fsl,imx8qxp-iomuxc"; 170 }; 171 172 ocotp: imx8qx-ocotp { 173 compatible = "fsl,imx8qxp-scu-ocotp"; 174 #address-cells = <1>; 175 #size-cells = <1>; 176 }; 177 178 pd: imx8qx-pd { 179 compatible = "fsl,imx8qxp-scu-pd"; 180 #power-domain-cells = <1>; 181 }; 182 183 scu_key: scu-key { 184 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 185 linux,keycodes = <KEY_POWER>; 186 status = "disabled"; 187 }; 188 189 rtc: rtc { 190 compatible = "fsl,imx8qxp-sc-rtc"; 191 }; 192 193 watchdog { 194 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 195 timeout-sec = <60>; 196 }; 197 198 tsens: thermal-sensor { 199 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 200 #thermal-sensor-cells = <1>; 201 }; 202 }; 203 204 timer { 205 compatible = "arm,armv8-timer"; 206 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 207 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 208 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 209 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 210 }; 211 212 xtal32k: clock-xtal32k { 213 compatible = "fixed-clock"; 214 #clock-cells = <0>; 215 clock-frequency = <32768>; 216 clock-output-names = "xtal_32KHz"; 217 }; 218 219 xtal24m: clock-xtal24m { 220 compatible = "fixed-clock"; 221 #clock-cells = <0>; 222 clock-frequency = <24000000>; 223 clock-output-names = "xtal_24MHz"; 224 }; 225 226 adma_subsys: bus@59000000 { 227 compatible = "simple-bus"; 228 #address-cells = <1>; 229 #size-cells = <1>; 230 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 231 232 adma_lpcg: clock-controller@59000000 { 233 compatible = "fsl,imx8qxp-lpcg-adma"; 234 reg = <0x59000000 0x2000000>; 235 #clock-cells = <1>; 236 }; 237 238 adma_dsp: dsp@596e8000 { 239 compatible = "fsl,imx8qxp-dsp"; 240 reg = <0x596e8000 0x88000>; 241 clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, 242 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, 243 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; 244 clock-names = "ipg", "ocram", "core"; 245 power-domains = <&pd IMX_SC_R_MU_13A>, 246 <&pd IMX_SC_R_MU_13B>, 247 <&pd IMX_SC_R_DSP>, 248 <&pd IMX_SC_R_DSP_RAM>; 249 mbox-names = "txdb0", "txdb1", 250 "rxdb0", "rxdb1"; 251 mboxes = <&lsio_mu13 2 0>, 252 <&lsio_mu13 2 1>, 253 <&lsio_mu13 3 0>, 254 <&lsio_mu13 3 1>; 255 memory-region = <&dsp_reserved>; 256 status = "disabled"; 257 }; 258 259 adma_lpuart0: serial@5a060000 { 260 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 261 reg = <0x5a060000 0x1000>; 262 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, 264 <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 265 clock-names = "ipg", "baud"; 266 power-domains = <&pd IMX_SC_R_UART_0>; 267 status = "disabled"; 268 }; 269 270 adma_lpuart1: serial@5a070000 { 271 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 272 reg = <0x5a070000 0x1000>; 273 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, 275 <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 276 clock-names = "ipg", "baud"; 277 power-domains = <&pd IMX_SC_R_UART_1>; 278 status = "disabled"; 279 }; 280 281 adma_lpuart2: serial@5a080000 { 282 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 283 reg = <0x5a080000 0x1000>; 284 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, 286 <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 287 clock-names = "ipg", "baud"; 288 power-domains = <&pd IMX_SC_R_UART_2>; 289 status = "disabled"; 290 }; 291 292 adma_lpuart3: serial@5a090000 { 293 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 294 reg = <0x5a090000 0x1000>; 295 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, 297 <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 298 clock-names = "ipg", "baud"; 299 power-domains = <&pd IMX_SC_R_UART_3>; 300 status = "disabled"; 301 }; 302 303 adma_i2c0: i2c@5a800000 { 304 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 305 reg = <0x5a800000 0x4000>; 306 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 308 clock-names = "per"; 309 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 310 assigned-clock-rates = <24000000>; 311 power-domains = <&pd IMX_SC_R_I2C_0>; 312 status = "disabled"; 313 }; 314 315 adma_i2c1: i2c@5a810000 { 316 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 317 reg = <0x5a810000 0x4000>; 318 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 320 clock-names = "per"; 321 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 322 assigned-clock-rates = <24000000>; 323 power-domains = <&pd IMX_SC_R_I2C_1>; 324 status = "disabled"; 325 }; 326 327 adma_i2c2: i2c@5a820000 { 328 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 329 reg = <0x5a820000 0x4000>; 330 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 332 clock-names = "per"; 333 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 334 assigned-clock-rates = <24000000>; 335 power-domains = <&pd IMX_SC_R_I2C_2>; 336 status = "disabled"; 337 }; 338 339 adma_i2c3: i2c@5a830000 { 340 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 341 reg = <0x5a830000 0x4000>; 342 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 344 clock-names = "per"; 345 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 346 assigned-clock-rates = <24000000>; 347 power-domains = <&pd IMX_SC_R_I2C_3>; 348 status = "disabled"; 349 }; 350 }; 351 352 conn_subsys: bus@5b000000 { 353 compatible = "simple-bus"; 354 #address-cells = <1>; 355 #size-cells = <1>; 356 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 357 358 conn_lpcg: clock-controller@5b200000 { 359 compatible = "fsl,imx8qxp-lpcg-conn"; 360 reg = <0x5b200000 0xb0000>; 361 #clock-cells = <1>; 362 }; 363 364 usdhc1: mmc@5b010000 { 365 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 366 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 367 reg = <0x5b010000 0x10000>; 368 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 369 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 370 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 371 clock-names = "ipg", "per", "ahb"; 372 power-domains = <&pd IMX_SC_R_SDHC_0>; 373 status = "disabled"; 374 }; 375 376 usdhc2: mmc@5b020000 { 377 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 378 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 379 reg = <0x5b020000 0x10000>; 380 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 381 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 382 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 383 clock-names = "ipg", "per", "ahb"; 384 power-domains = <&pd IMX_SC_R_SDHC_1>; 385 fsl,tuning-start-tap = <20>; 386 fsl,tuning-step= <2>; 387 status = "disabled"; 388 }; 389 390 usdhc3: mmc@5b030000 { 391 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 392 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 393 reg = <0x5b030000 0x10000>; 394 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 395 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 396 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 397 clock-names = "ipg", "per", "ahb"; 398 power-domains = <&pd IMX_SC_R_SDHC_2>; 399 status = "disabled"; 400 }; 401 402 fec1: ethernet@5b040000 { 403 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 404 reg = <0x5b040000 0x10000>; 405 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 410 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 411 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 412 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 413 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 414 fsl,num-tx-queues=<3>; 415 fsl,num-rx-queues=<3>; 416 power-domains = <&pd IMX_SC_R_ENET_0>; 417 status = "disabled"; 418 }; 419 420 fec2: ethernet@5b050000 { 421 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 422 reg = <0x5b050000 0x10000>; 423 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 428 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 429 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 430 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 431 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 432 fsl,num-tx-queues=<3>; 433 fsl,num-rx-queues=<3>; 434 power-domains = <&pd IMX_SC_R_ENET_1>; 435 status = "disabled"; 436 }; 437 }; 438 439 ddr_subsyss: bus@5c000000 { 440 compatible = "simple-bus"; 441 #address-cells = <1>; 442 #size-cells = <1>; 443 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; 444 445 ddr-pmu@5c020000 { 446 compatible = "fsl,imx8-ddr-pmu"; 447 reg = <0x5c020000 0x10000>; 448 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 449 }; 450 }; 451 452 lsio_subsys: bus@5d000000 { 453 compatible = "simple-bus"; 454 #address-cells = <1>; 455 #size-cells = <1>; 456 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 457 458 lsio_gpio0: gpio@5d080000 { 459 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 460 reg = <0x5d080000 0x10000>; 461 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 462 gpio-controller; 463 #gpio-cells = <2>; 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 power-domains = <&pd IMX_SC_R_GPIO_0>; 467 }; 468 469 lsio_gpio1: gpio@5d090000 { 470 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 471 reg = <0x5d090000 0x10000>; 472 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 473 gpio-controller; 474 #gpio-cells = <2>; 475 interrupt-controller; 476 #interrupt-cells = <2>; 477 power-domains = <&pd IMX_SC_R_GPIO_1>; 478 }; 479 480 lsio_gpio2: gpio@5d0a0000 { 481 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 482 reg = <0x5d0a0000 0x10000>; 483 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 484 gpio-controller; 485 #gpio-cells = <2>; 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 power-domains = <&pd IMX_SC_R_GPIO_2>; 489 }; 490 491 lsio_gpio3: gpio@5d0b0000 { 492 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 493 reg = <0x5d0b0000 0x10000>; 494 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 495 gpio-controller; 496 #gpio-cells = <2>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 power-domains = <&pd IMX_SC_R_GPIO_3>; 500 }; 501 502 lsio_gpio4: gpio@5d0c0000 { 503 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 504 reg = <0x5d0c0000 0x10000>; 505 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 506 gpio-controller; 507 #gpio-cells = <2>; 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 power-domains = <&pd IMX_SC_R_GPIO_4>; 511 }; 512 513 lsio_gpio5: gpio@5d0d0000 { 514 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 515 reg = <0x5d0d0000 0x10000>; 516 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 517 gpio-controller; 518 #gpio-cells = <2>; 519 interrupt-controller; 520 #interrupt-cells = <2>; 521 power-domains = <&pd IMX_SC_R_GPIO_5>; 522 }; 523 524 lsio_gpio6: gpio@5d0e0000 { 525 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 526 reg = <0x5d0e0000 0x10000>; 527 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 528 gpio-controller; 529 #gpio-cells = <2>; 530 interrupt-controller; 531 #interrupt-cells = <2>; 532 power-domains = <&pd IMX_SC_R_GPIO_6>; 533 }; 534 535 lsio_gpio7: gpio@5d0f0000 { 536 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 537 reg = <0x5d0f0000 0x10000>; 538 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 539 gpio-controller; 540 #gpio-cells = <2>; 541 interrupt-controller; 542 #interrupt-cells = <2>; 543 power-domains = <&pd IMX_SC_R_GPIO_7>; 544 }; 545 546 lsio_mu0: mailbox@5d1b0000 { 547 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 548 reg = <0x5d1b0000 0x10000>; 549 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 550 #mbox-cells = <2>; 551 status = "disabled"; 552 }; 553 554 lsio_mu1: mailbox@5d1c0000 { 555 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 556 reg = <0x5d1c0000 0x10000>; 557 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 558 #mbox-cells = <2>; 559 }; 560 561 lsio_mu2: mailbox@5d1d0000 { 562 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 563 reg = <0x5d1d0000 0x10000>; 564 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 565 #mbox-cells = <2>; 566 status = "disabled"; 567 }; 568 569 lsio_mu3: mailbox@5d1e0000 { 570 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 571 reg = <0x5d1e0000 0x10000>; 572 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 573 #mbox-cells = <2>; 574 status = "disabled"; 575 }; 576 577 lsio_mu4: mailbox@5d1f0000 { 578 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 579 reg = <0x5d1f0000 0x10000>; 580 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 581 #mbox-cells = <2>; 582 status = "disabled"; 583 }; 584 585 lsio_mu13: mailbox@5d280000 { 586 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 587 reg = <0x5d280000 0x10000>; 588 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 589 #mbox-cells = <2>; 590 power-domains = <&pd IMX_SC_R_MU_13A>; 591 }; 592 593 lsio_lpcg: clock-controller@5d400000 { 594 compatible = "fsl,imx8qxp-lpcg-lsio"; 595 reg = <0x5d400000 0x400000>; 596 #clock-cells = <1>; 597 }; 598 }; 599 600 thermal_zones: thermal-zones { 601 cpu-thermal0 { 602 polling-delay-passive = <250>; 603 polling-delay = <2000>; 604 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 605 606 trips { 607 cpu_alert0: trip0 { 608 temperature = <107000>; 609 hysteresis = <2000>; 610 type = "passive"; 611 }; 612 613 cpu_crit0: trip1 { 614 temperature = <127000>; 615 hysteresis = <2000>; 616 type = "critical"; 617 }; 618 }; 619 620 cooling-maps { 621 map0 { 622 trip = <&cpu_alert0>; 623 cooling-device = 624 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 625 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 626 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 627 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 628 }; 629 }; 630 }; 631 }; 632}; 633