1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2020 NXP
5 *	Dong Aisheng <aisheng.dong@nxp.com>
6 */
7
8#include <dt-bindings/clock/imx8-clock.h>
9#include <dt-bindings/clock/imx8-lpcg.h>
10#include <dt-bindings/firmware/imx/rsrc.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/pinctrl/pads-imx8qxp.h>
15#include <dt-bindings/thermal/thermal.h>
16
17/ {
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		ethernet0 = &fec1;
24		ethernet1 = &fec2;
25		gpio0 = &lsio_gpio0;
26		gpio1 = &lsio_gpio1;
27		gpio2 = &lsio_gpio2;
28		gpio3 = &lsio_gpio3;
29		gpio4 = &lsio_gpio4;
30		gpio5 = &lsio_gpio5;
31		gpio6 = &lsio_gpio6;
32		gpio7 = &lsio_gpio7;
33		i2c0 = &i2c0;
34		i2c1 = &i2c1;
35		i2c2 = &i2c2;
36		i2c3 = &i2c3;
37		mmc0 = &usdhc1;
38		mmc1 = &usdhc2;
39		mmc2 = &usdhc3;
40		mu0 = &lsio_mu0;
41		mu1 = &lsio_mu1;
42		mu2 = &lsio_mu2;
43		mu3 = &lsio_mu3;
44		mu4 = &lsio_mu4;
45		serial0 = &lpuart0;
46		serial1 = &lpuart1;
47		serial2 = &lpuart2;
48		serial3 = &lpuart3;
49		vpu-core0 = &vpu_core0;
50		vpu-core1 = &vpu_core1;
51	};
52
53	cpus {
54		#address-cells = <2>;
55		#size-cells = <0>;
56
57		/* We have 1 clusters with 4 Cortex-A35 cores */
58		A35_0: cpu@0 {
59			device_type = "cpu";
60			compatible = "arm,cortex-a35";
61			reg = <0x0 0x0>;
62			enable-method = "psci";
63			i-cache-size = <0x8000>;
64			i-cache-line-size = <64>;
65			i-cache-sets = <256>;
66			d-cache-size = <0x8000>;
67			d-cache-line-size = <64>;
68			d-cache-sets = <128>;
69			next-level-cache = <&A35_L2>;
70			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
71			operating-points-v2 = <&a35_opp_table>;
72			#cooling-cells = <2>;
73		};
74
75		A35_1: cpu@1 {
76			device_type = "cpu";
77			compatible = "arm,cortex-a35";
78			reg = <0x0 0x1>;
79			enable-method = "psci";
80			i-cache-size = <0x8000>;
81			i-cache-line-size = <64>;
82			i-cache-sets = <256>;
83			d-cache-size = <0x8000>;
84			d-cache-line-size = <64>;
85			d-cache-sets = <128>;
86			next-level-cache = <&A35_L2>;
87			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
88			operating-points-v2 = <&a35_opp_table>;
89			#cooling-cells = <2>;
90		};
91
92		A35_2: cpu@2 {
93			device_type = "cpu";
94			compatible = "arm,cortex-a35";
95			reg = <0x0 0x2>;
96			enable-method = "psci";
97			i-cache-size = <0x8000>;
98			i-cache-line-size = <64>;
99			i-cache-sets = <256>;
100			d-cache-size = <0x8000>;
101			d-cache-line-size = <64>;
102			d-cache-sets = <128>;
103			next-level-cache = <&A35_L2>;
104			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
105			operating-points-v2 = <&a35_opp_table>;
106			#cooling-cells = <2>;
107		};
108
109		A35_3: cpu@3 {
110			device_type = "cpu";
111			compatible = "arm,cortex-a35";
112			reg = <0x0 0x3>;
113			enable-method = "psci";
114			i-cache-size = <0x8000>;
115			i-cache-line-size = <64>;
116			i-cache-sets = <256>;
117			d-cache-size = <0x8000>;
118			d-cache-line-size = <64>;
119			d-cache-sets = <128>;
120			next-level-cache = <&A35_L2>;
121			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
122			operating-points-v2 = <&a35_opp_table>;
123			#cooling-cells = <2>;
124		};
125
126		A35_L2: l2-cache0 {
127			compatible = "cache";
128			cache-level = <2>;
129			cache-unified;
130			cache-size = <0x80000>;
131			cache-line-size = <64>;
132			cache-sets = <1024>;
133		};
134	};
135
136	a35_opp_table: opp-table {
137		compatible = "operating-points-v2";
138		opp-shared;
139
140		opp-900000000 {
141			opp-hz = /bits/ 64 <900000000>;
142			opp-microvolt = <1000000>;
143			clock-latency-ns = <150000>;
144		};
145
146		opp-1200000000 {
147			opp-hz = /bits/ 64 <1200000000>;
148			opp-microvolt = <1100000>;
149			clock-latency-ns = <150000>;
150			opp-suspend;
151		};
152	};
153
154	gic: interrupt-controller@51a00000 {
155		compatible = "arm,gic-v3";
156		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
157		      <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
158		#interrupt-cells = <3>;
159		interrupt-controller;
160		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
161	};
162
163	reserved-memory {
164		#address-cells = <2>;
165		#size-cells = <2>;
166		ranges;
167
168		decoder_boot: decoder-boot@84000000 {
169			reg = <0 0x84000000 0 0x2000000>;
170			no-map;
171		};
172
173		encoder_boot: encoder-boot@86000000 {
174			reg = <0 0x86000000 0 0x200000>;
175			no-map;
176		};
177
178		decoder_rpc: decoder-rpc@92000000 {
179			reg = <0 0x92000000 0 0x100000>;
180			no-map;
181		};
182
183		dsp_reserved: dsp@92400000 {
184			reg = <0 0x92400000 0 0x2000000>;
185			no-map;
186		};
187
188		encoder_rpc: encoder-rpc@94400000 {
189			reg = <0 0x94400000 0 0x700000>;
190			no-map;
191		};
192	};
193
194	pmu {
195		compatible = "arm,cortex-a35-pmu";
196		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
197	};
198
199	psci {
200		compatible = "arm,psci-1.0";
201		method = "smc";
202	};
203
204	system-controller {
205		compatible = "fsl,imx-scu";
206		mbox-names = "tx0",
207			     "rx0",
208			     "gip3";
209		mboxes = <&lsio_mu1 0 0
210			  &lsio_mu1 1 0
211			  &lsio_mu1 3 3>;
212
213		pd: power-controller {
214			compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
215			#power-domain-cells = <1>;
216		};
217
218		clk: clock-controller {
219			compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
220			#clock-cells = <2>;
221		};
222
223		iomuxc: pinctrl {
224			compatible = "fsl,imx8qxp-iomuxc";
225		};
226
227		ocotp: ocotp {
228			compatible = "fsl,imx8qxp-scu-ocotp";
229			#address-cells = <1>;
230			#size-cells = <1>;
231		};
232
233		scu_key: keys {
234			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
235			linux,keycodes = <KEY_POWER>;
236			status = "disabled";
237		};
238
239		rtc: rtc {
240			compatible = "fsl,imx8qxp-sc-rtc";
241		};
242
243		watchdog {
244			compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
245			timeout-sec = <60>;
246		};
247
248		tsens: thermal-sensor {
249			compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
250			#thermal-sensor-cells = <1>;
251		};
252	};
253
254	timer {
255		compatible = "arm,armv8-timer";
256		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
257			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
258			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
259			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
260	};
261
262	xtal32k: clock-xtal32k {
263		compatible = "fixed-clock";
264		#clock-cells = <0>;
265		clock-frequency = <32768>;
266		clock-output-names = "xtal_32KHz";
267	};
268
269	xtal24m: clock-xtal24m {
270		compatible = "fixed-clock";
271		#clock-cells = <0>;
272		clock-frequency = <24000000>;
273		clock-output-names = "xtal_24MHz";
274	};
275
276	thermal_zones: thermal-zones {
277		cpu0-thermal {
278			polling-delay-passive = <250>;
279			polling-delay = <2000>;
280			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
281
282			trips {
283				cpu_alert0: trip0 {
284					temperature = <107000>;
285					hysteresis = <2000>;
286					type = "passive";
287				};
288
289				cpu_crit0: trip1 {
290					temperature = <127000>;
291					hysteresis = <2000>;
292					type = "critical";
293				};
294			};
295
296			cooling-maps {
297				map0 {
298					trip = <&cpu_alert0>;
299					cooling-device =
300						<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
301						<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
302						<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
303						<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
304				};
305			};
306		};
307	};
308
309	/* sorted in register address */
310	#include "imx8-ss-img.dtsi"
311	#include "imx8-ss-vpu.dtsi"
312	#include "imx8-ss-adma.dtsi"
313	#include "imx8-ss-conn.dtsi"
314	#include "imx8-ss-ddr.dtsi"
315	#include "imx8-ss-lsio.dtsi"
316};
317
318#include "imx8qxp-ss-img.dtsi"
319#include "imx8qxp-ss-vpu.dtsi"
320#include "imx8qxp-ss-adma.dtsi"
321#include "imx8qxp-ss-conn.dtsi"
322#include "imx8qxp-ss-lsio.dtsi"
323