1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
7  */
8 
9 #ifndef __ADRENO_GPU_H__
10 #define __ADRENO_GPU_H__
11 
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
14 
15 #include "msm_gpu.h"
16 
17 #include "adreno_common.xml.h"
18 #include "adreno_pm4.xml.h"
19 
20 extern bool snapshot_debugbus;
21 extern bool allow_vram_carveout;
22 
23 enum {
24 	ADRENO_FW_PM4 = 0,
25 	ADRENO_FW_SQE = 0, /* a6xx */
26 	ADRENO_FW_PFP = 1,
27 	ADRENO_FW_GMU = 1, /* a6xx */
28 	ADRENO_FW_GPMU = 2,
29 	ADRENO_FW_MAX,
30 };
31 
32 #define ADRENO_QUIRK_TWO_PASS_USE_WFI		BIT(0)
33 #define ADRENO_QUIRK_FAULT_DETECT_MASK		BIT(1)
34 #define ADRENO_QUIRK_LMLOADKILL_DISABLE		BIT(2)
35 
36 struct adreno_rev {
37 	uint8_t  core;
38 	uint8_t  major;
39 	uint8_t  minor;
40 	uint8_t  patchid;
41 };
42 
43 #define ANY_ID 0xff
44 
45 #define ADRENO_REV(core, major, minor, patchid) \
46 	((struct adreno_rev){ core, major, minor, patchid })
47 
48 struct adreno_gpu_funcs {
49 	struct msm_gpu_funcs base;
50 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
51 };
52 
53 struct adreno_reglist {
54 	u32 offset;
55 	u32 value;
56 };
57 
58 extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[];
59 extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
60 
61 struct adreno_info {
62 	struct adreno_rev rev;
63 	uint32_t revn;
64 	const char *fw[ADRENO_FW_MAX];
65 	uint32_t gmem;
66 	u64 quirks;
67 	struct msm_gpu *(*init)(struct drm_device *dev);
68 	const char *zapfw;
69 	u32 inactive_period;
70 	const struct adreno_reglist *hwcg;
71 	u64 address_space_size;
72 };
73 
74 const struct adreno_info *adreno_info(struct adreno_rev rev);
75 
76 struct adreno_gpu {
77 	struct msm_gpu base;
78 	struct adreno_rev rev;
79 	const struct adreno_info *info;
80 	uint32_t revn;  /* numeric revision name */
81 	uint16_t speedbin;
82 	const struct adreno_gpu_funcs *funcs;
83 
84 	/* interesting register offsets to dump: */
85 	const unsigned int *registers;
86 
87 	/*
88 	 * Are we loading fw from legacy path?  Prior to addition
89 	 * of gpu firmware to linux-firmware, the fw files were
90 	 * placed in toplevel firmware directory, following qcom's
91 	 * android kernel.  But linux-firmware preferred they be
92 	 * placed in a 'qcom' subdirectory.
93 	 *
94 	 * For backwards compatibility, we try first to load from
95 	 * the new path, using request_firmware_direct() to avoid
96 	 * any potential timeout waiting for usermode helper, then
97 	 * fall back to the old path (with direct load).  And
98 	 * finally fall back to request_firmware() with the new
99 	 * path to allow the usermode helper.
100 	 */
101 	enum {
102 		FW_LOCATION_UNKNOWN = 0,
103 		FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
104 		FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
105 		FW_LOCATION_HELPER,
106 	} fwloc;
107 
108 	/* firmware: */
109 	const struct firmware *fw[ADRENO_FW_MAX];
110 
111 	/*
112 	 * Register offsets are different between some GPUs.
113 	 * GPU specific offsets will be exported by GPU specific
114 	 * code (a3xx_gpu.c) and stored in this common location.
115 	 */
116 	const unsigned int *reg_offsets;
117 	bool gmu_is_wrapper;
118 };
119 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
120 
121 struct adreno_ocmem {
122 	struct ocmem *ocmem;
123 	unsigned long base;
124 	void *hdl;
125 };
126 
127 /* platform config data (ie. from DT, or pdata) */
128 struct adreno_platform_config {
129 	struct adreno_rev rev;
130 };
131 
132 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
133 
134 #define spin_until(X) ({                                   \
135 	int __ret = -ETIMEDOUT;                            \
136 	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
137 	do {                                               \
138 		if (X) {                                   \
139 			__ret = 0;                         \
140 			break;                             \
141 		}                                          \
142 	} while (time_before(jiffies, __t));               \
143 	__ret;                                             \
144 })
145 
146 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
147 
148 static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
149 {
150 	/* revn can be zero, but if not is set at same time as info */
151 	WARN_ON_ONCE(!gpu->info);
152 
153 	return gpu->revn == revn;
154 }
155 
156 static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
157 {
158 	return gpu->gmu_is_wrapper;
159 }
160 
161 static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
162 {
163 	/* revn can be zero, but if not is set at same time as info */
164 	WARN_ON_ONCE(!gpu->info);
165 
166 	return (gpu->revn < 300);
167 }
168 
169 static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
170 {
171 	/* revn can be zero, but if not is set at same time as info */
172 	WARN_ON_ONCE(!gpu->info);
173 
174 	return (gpu->revn < 210);
175 }
176 
177 static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
178 {
179 	return adreno_is_revn(gpu, 225);
180 }
181 
182 static inline bool adreno_is_a305(const struct adreno_gpu *gpu)
183 {
184 	return adreno_is_revn(gpu, 305);
185 }
186 
187 static inline bool adreno_is_a306(const struct adreno_gpu *gpu)
188 {
189 	/* yes, 307, because a305c is 306 */
190 	return adreno_is_revn(gpu, 307);
191 }
192 
193 static inline bool adreno_is_a320(const struct adreno_gpu *gpu)
194 {
195 	return adreno_is_revn(gpu, 320);
196 }
197 
198 static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
199 {
200 	return adreno_is_revn(gpu, 330);
201 }
202 
203 static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
204 {
205 	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
206 }
207 
208 static inline int adreno_is_a405(const struct adreno_gpu *gpu)
209 {
210 	return adreno_is_revn(gpu, 405);
211 }
212 
213 static inline int adreno_is_a420(const struct adreno_gpu *gpu)
214 {
215 	return adreno_is_revn(gpu, 420);
216 }
217 
218 static inline int adreno_is_a430(const struct adreno_gpu *gpu)
219 {
220 	return adreno_is_revn(gpu, 430);
221 }
222 
223 static inline int adreno_is_a506(const struct adreno_gpu *gpu)
224 {
225 	return adreno_is_revn(gpu, 506);
226 }
227 
228 static inline int adreno_is_a508(const struct adreno_gpu *gpu)
229 {
230 	return adreno_is_revn(gpu, 508);
231 }
232 
233 static inline int adreno_is_a509(const struct adreno_gpu *gpu)
234 {
235 	return adreno_is_revn(gpu, 509);
236 }
237 
238 static inline int adreno_is_a510(const struct adreno_gpu *gpu)
239 {
240 	return adreno_is_revn(gpu, 510);
241 }
242 
243 static inline int adreno_is_a512(const struct adreno_gpu *gpu)
244 {
245 	return adreno_is_revn(gpu, 512);
246 }
247 
248 static inline int adreno_is_a530(const struct adreno_gpu *gpu)
249 {
250 	return adreno_is_revn(gpu, 530);
251 }
252 
253 static inline int adreno_is_a540(const struct adreno_gpu *gpu)
254 {
255 	return adreno_is_revn(gpu, 540);
256 }
257 
258 static inline int adreno_is_a610(const struct adreno_gpu *gpu)
259 {
260 	return adreno_is_revn(gpu, 610);
261 }
262 
263 static inline int adreno_is_a618(const struct adreno_gpu *gpu)
264 {
265 	return adreno_is_revn(gpu, 618);
266 }
267 
268 static inline int adreno_is_a619(const struct adreno_gpu *gpu)
269 {
270 	return adreno_is_revn(gpu, 619);
271 }
272 
273 static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu)
274 {
275 	return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu);
276 }
277 
278 static inline int adreno_is_a630(const struct adreno_gpu *gpu)
279 {
280 	return adreno_is_revn(gpu, 630);
281 }
282 
283 static inline int adreno_is_a640(const struct adreno_gpu *gpu)
284 {
285 	return adreno_is_revn(gpu, 640);
286 }
287 
288 static inline int adreno_is_a650(const struct adreno_gpu *gpu)
289 {
290 	return adreno_is_revn(gpu, 650);
291 }
292 
293 static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
294 {
295 	/* The order of args is important here to handle ANY_ID correctly */
296 	return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
297 }
298 
299 static inline int adreno_is_a660(const struct adreno_gpu *gpu)
300 {
301 	return adreno_is_revn(gpu, 660);
302 }
303 
304 static inline int adreno_is_a680(const struct adreno_gpu *gpu)
305 {
306 	return adreno_is_revn(gpu, 680);
307 }
308 
309 static inline int adreno_is_a690(const struct adreno_gpu *gpu)
310 {
311 	/* The order of args is important here to handle ANY_ID correctly */
312 	return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
313 };
314 
315 /* check for a615, a616, a618, a619 or any derivatives */
316 static inline int adreno_is_a615_family(const struct adreno_gpu *gpu)
317 {
318 	return adreno_is_revn(gpu, 615) ||
319 		adreno_is_revn(gpu, 616) ||
320 		adreno_is_revn(gpu, 618) ||
321 		adreno_is_revn(gpu, 619);
322 }
323 
324 static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
325 {
326 	return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
327 }
328 
329 /* check for a650, a660, or any derivatives */
330 static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
331 {
332 	return adreno_is_revn(gpu, 650) ||
333 		adreno_is_revn(gpu, 620) ||
334 		adreno_is_a660_family(gpu);
335 }
336 
337 static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
338 {
339 	return adreno_is_a640(gpu) || adreno_is_a680(gpu);
340 }
341 
342 u64 adreno_private_address_space_size(struct msm_gpu *gpu);
343 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
344 		     uint32_t param, uint64_t *value, uint32_t *len);
345 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
346 		     uint32_t param, uint64_t value, uint32_t len);
347 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
348 		const char *fwname);
349 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
350 		const struct firmware *fw, u64 *iova);
351 int adreno_hw_init(struct msm_gpu *gpu);
352 void adreno_recover(struct msm_gpu *gpu);
353 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
354 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
355 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
356 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
357 		struct drm_printer *p);
358 #endif
359 void adreno_dump_info(struct msm_gpu *gpu);
360 void adreno_dump(struct msm_gpu *gpu);
361 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
362 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
363 
364 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
365 			  struct adreno_ocmem *ocmem);
366 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
367 
368 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
369 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
370 		int nr_rings);
371 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
372 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
373 
374 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
375 
376 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
377 int adreno_gpu_state_put(struct msm_gpu_state *state);
378 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
379 		bool *encoded);
380 
381 /*
382  * Common helper function to initialize the default address space for arm-smmu
383  * attached targets
384  */
385 struct msm_gem_address_space *
386 adreno_create_address_space(struct msm_gpu *gpu,
387 			    struct platform_device *pdev);
388 
389 struct msm_gem_address_space *
390 adreno_iommu_create_address_space(struct msm_gpu *gpu,
391 				  struct platform_device *pdev,
392 				  unsigned long quirks);
393 
394 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
395 			 struct adreno_smmu_fault_info *info, const char *block,
396 			 u32 scratch[4]);
397 
398 int adreno_read_speedbin(struct device *dev, u32 *speedbin);
399 
400 /*
401  * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
402  * out of secure mode
403  */
404 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
405 
406 /* ringbuffer helpers (the parts that are adreno specific) */
407 
408 static inline void
409 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
410 {
411 	adreno_wait_ring(ring, cnt+1);
412 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
413 }
414 
415 /* no-op packet: */
416 static inline void
417 OUT_PKT2(struct msm_ringbuffer *ring)
418 {
419 	adreno_wait_ring(ring, 1);
420 	OUT_RING(ring, CP_TYPE2_PKT);
421 }
422 
423 static inline void
424 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
425 {
426 	adreno_wait_ring(ring, cnt+1);
427 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
428 }
429 
430 static inline u32 PM4_PARITY(u32 val)
431 {
432 	return (0x9669 >> (0xF & (val ^
433 		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
434 		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
435 		(val >> 28)))) & 1;
436 }
437 
438 /* Maximum number of values that can be executed for one opcode */
439 #define TYPE4_MAX_PAYLOAD 127
440 
441 #define PKT4(_reg, _cnt) \
442 	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
443 	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
444 
445 static inline void
446 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
447 {
448 	adreno_wait_ring(ring, cnt + 1);
449 	OUT_RING(ring, PKT4(regindx, cnt));
450 }
451 
452 static inline void
453 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
454 {
455 	adreno_wait_ring(ring, cnt + 1);
456 	OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
457 		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
458 }
459 
460 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
461 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
462 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
463 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
464 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
465 
466 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
467 {
468 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
469 }
470 
471 /*
472  * Given a register and a count, return a value to program into
473  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
474  * registers starting at _reg.
475  *
476  * The register base needs to be a multiple of the length. If it is not, the
477  * hardware will quietly mask off the bits for you and shift the size. For
478  * example, if you intend the protection to start at 0x07 for a length of 4
479  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
480  * expose registers you intended to protect!
481  */
482 #define ADRENO_PROTECT_RW(_reg, _len) \
483 	((1 << 30) | (1 << 29) | \
484 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
485 
486 /*
487  * Same as above, but allow reads over the range. For areas of mixed use (such
488  * as performance counters) this allows us to protect a much larger range with a
489  * single register
490  */
491 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
492 	((1 << 29) \
493 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
494 
495 
496 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
497 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
498 		interval, timeout)
499 
500 #endif /* __ADRENO_GPU_H__ */
501