1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved. 7 */ 8 9 #ifndef __ADRENO_GPU_H__ 10 #define __ADRENO_GPU_H__ 11 12 #include <linux/firmware.h> 13 #include <linux/iopoll.h> 14 15 #include "msm_gpu.h" 16 17 #include "adreno_common.xml.h" 18 #include "adreno_pm4.xml.h" 19 20 extern bool snapshot_debugbus; 21 extern bool allow_vram_carveout; 22 23 enum { 24 ADRENO_FW_PM4 = 0, 25 ADRENO_FW_SQE = 0, /* a6xx */ 26 ADRENO_FW_PFP = 1, 27 ADRENO_FW_GMU = 1, /* a6xx */ 28 ADRENO_FW_GPMU = 2, 29 ADRENO_FW_MAX, 30 }; 31 32 #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) 33 #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) 34 #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) 35 36 struct adreno_rev { 37 uint8_t core; 38 uint8_t major; 39 uint8_t minor; 40 uint8_t patchid; 41 }; 42 43 #define ANY_ID 0xff 44 45 #define ADRENO_REV(core, major, minor, patchid) \ 46 ((struct adreno_rev){ core, major, minor, patchid }) 47 48 struct adreno_gpu_funcs { 49 struct msm_gpu_funcs base; 50 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); 51 }; 52 53 struct adreno_reglist { 54 u32 offset; 55 u32 value; 56 }; 57 58 extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[]; 59 extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; 60 61 struct adreno_info { 62 struct adreno_rev rev; 63 uint32_t revn; 64 const char *name; 65 const char *fw[ADRENO_FW_MAX]; 66 uint32_t gmem; 67 u64 quirks; 68 struct msm_gpu *(*init)(struct drm_device *dev); 69 const char *zapfw; 70 u32 inactive_period; 71 const struct adreno_reglist *hwcg; 72 u64 address_space_size; 73 }; 74 75 const struct adreno_info *adreno_info(struct adreno_rev rev); 76 77 struct adreno_gpu { 78 struct msm_gpu base; 79 struct adreno_rev rev; 80 const struct adreno_info *info; 81 uint32_t gmem; /* actual gmem size */ 82 uint32_t revn; /* numeric revision name */ 83 uint16_t speedbin; 84 const struct adreno_gpu_funcs *funcs; 85 86 /* interesting register offsets to dump: */ 87 const unsigned int *registers; 88 89 /* 90 * Are we loading fw from legacy path? Prior to addition 91 * of gpu firmware to linux-firmware, the fw files were 92 * placed in toplevel firmware directory, following qcom's 93 * android kernel. But linux-firmware preferred they be 94 * placed in a 'qcom' subdirectory. 95 * 96 * For backwards compatibility, we try first to load from 97 * the new path, using request_firmware_direct() to avoid 98 * any potential timeout waiting for usermode helper, then 99 * fall back to the old path (with direct load). And 100 * finally fall back to request_firmware() with the new 101 * path to allow the usermode helper. 102 */ 103 enum { 104 FW_LOCATION_UNKNOWN = 0, 105 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */ 106 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */ 107 FW_LOCATION_HELPER, 108 } fwloc; 109 110 /* firmware: */ 111 const struct firmware *fw[ADRENO_FW_MAX]; 112 113 /* 114 * Register offsets are different between some GPUs. 115 * GPU specific offsets will be exported by GPU specific 116 * code (a3xx_gpu.c) and stored in this common location. 117 */ 118 const unsigned int *reg_offsets; 119 bool gmu_is_wrapper; 120 }; 121 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) 122 123 struct adreno_ocmem { 124 struct ocmem *ocmem; 125 unsigned long base; 126 void *hdl; 127 }; 128 129 /* platform config data (ie. from DT, or pdata) */ 130 struct adreno_platform_config { 131 struct adreno_rev rev; 132 }; 133 134 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) 135 136 #define spin_until(X) ({ \ 137 int __ret = -ETIMEDOUT; \ 138 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \ 139 do { \ 140 if (X) { \ 141 __ret = 0; \ 142 break; \ 143 } \ 144 } while (time_before(jiffies, __t)); \ 145 __ret; \ 146 }) 147 148 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); 149 150 static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) 151 { 152 WARN_ON_ONCE(!gpu->revn); 153 154 return gpu->revn == revn; 155 } 156 157 static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) 158 { 159 return gpu->gmu_is_wrapper; 160 } 161 162 static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) 163 { 164 WARN_ON_ONCE(!gpu->revn); 165 166 return (gpu->revn < 300); 167 } 168 169 static inline bool adreno_is_a20x(const struct adreno_gpu *gpu) 170 { 171 WARN_ON_ONCE(!gpu->revn); 172 173 return (gpu->revn < 210); 174 } 175 176 static inline bool adreno_is_a225(const struct adreno_gpu *gpu) 177 { 178 return adreno_is_revn(gpu, 225); 179 } 180 181 static inline bool adreno_is_a305(const struct adreno_gpu *gpu) 182 { 183 return adreno_is_revn(gpu, 305); 184 } 185 186 static inline bool adreno_is_a306(const struct adreno_gpu *gpu) 187 { 188 /* yes, 307, because a305c is 306 */ 189 return adreno_is_revn(gpu, 307); 190 } 191 192 static inline bool adreno_is_a320(const struct adreno_gpu *gpu) 193 { 194 return adreno_is_revn(gpu, 320); 195 } 196 197 static inline bool adreno_is_a330(const struct adreno_gpu *gpu) 198 { 199 return adreno_is_revn(gpu, 330); 200 } 201 202 static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu) 203 { 204 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0); 205 } 206 207 static inline int adreno_is_a405(const struct adreno_gpu *gpu) 208 { 209 return adreno_is_revn(gpu, 405); 210 } 211 212 static inline int adreno_is_a420(const struct adreno_gpu *gpu) 213 { 214 return adreno_is_revn(gpu, 420); 215 } 216 217 static inline int adreno_is_a430(const struct adreno_gpu *gpu) 218 { 219 return adreno_is_revn(gpu, 430); 220 } 221 222 static inline int adreno_is_a506(const struct adreno_gpu *gpu) 223 { 224 return adreno_is_revn(gpu, 506); 225 } 226 227 static inline int adreno_is_a508(const struct adreno_gpu *gpu) 228 { 229 return adreno_is_revn(gpu, 508); 230 } 231 232 static inline int adreno_is_a509(const struct adreno_gpu *gpu) 233 { 234 return adreno_is_revn(gpu, 509); 235 } 236 237 static inline int adreno_is_a510(const struct adreno_gpu *gpu) 238 { 239 return adreno_is_revn(gpu, 510); 240 } 241 242 static inline int adreno_is_a512(const struct adreno_gpu *gpu) 243 { 244 return adreno_is_revn(gpu, 512); 245 } 246 247 static inline int adreno_is_a530(const struct adreno_gpu *gpu) 248 { 249 return adreno_is_revn(gpu, 530); 250 } 251 252 static inline int adreno_is_a540(const struct adreno_gpu *gpu) 253 { 254 return adreno_is_revn(gpu, 540); 255 } 256 257 static inline int adreno_is_a610(const struct adreno_gpu *gpu) 258 { 259 return adreno_is_revn(gpu, 610); 260 } 261 262 static inline int adreno_is_a618(const struct adreno_gpu *gpu) 263 { 264 return adreno_is_revn(gpu, 618); 265 } 266 267 static inline int adreno_is_a619(const struct adreno_gpu *gpu) 268 { 269 return adreno_is_revn(gpu, 619); 270 } 271 272 static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu) 273 { 274 return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu); 275 } 276 277 static inline int adreno_is_a630(const struct adreno_gpu *gpu) 278 { 279 return adreno_is_revn(gpu, 630); 280 } 281 282 static inline int adreno_is_a640_family(const struct adreno_gpu *gpu) 283 { 284 return adreno_is_revn(gpu, 640) || 285 adreno_is_revn(gpu, 680); 286 } 287 288 static inline int adreno_is_a650(const struct adreno_gpu *gpu) 289 { 290 return adreno_is_revn(gpu, 650); 291 } 292 293 static inline int adreno_is_7c3(const struct adreno_gpu *gpu) 294 { 295 /* The order of args is important here to handle ANY_ID correctly */ 296 return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev); 297 } 298 299 static inline int adreno_is_a660(const struct adreno_gpu *gpu) 300 { 301 return adreno_is_revn(gpu, 660); 302 } 303 304 static inline int adreno_is_a690(const struct adreno_gpu *gpu) 305 { 306 return adreno_is_revn(gpu, 690); 307 }; 308 309 /* check for a615, a616, a618, a619 or any derivatives */ 310 static inline int adreno_is_a615_family(const struct adreno_gpu *gpu) 311 { 312 return adreno_is_revn(gpu, 615) || 313 adreno_is_revn(gpu, 616) || 314 adreno_is_revn(gpu, 618) || 315 adreno_is_revn(gpu, 619); 316 } 317 318 static inline int adreno_is_a660_family(const struct adreno_gpu *gpu) 319 { 320 return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu); 321 } 322 323 /* check for a650, a660, or any derivatives */ 324 static inline int adreno_is_a650_family(const struct adreno_gpu *gpu) 325 { 326 return adreno_is_revn(gpu, 650) || 327 adreno_is_revn(gpu, 620) || 328 adreno_is_a660_family(gpu); 329 } 330 331 u64 adreno_private_address_space_size(struct msm_gpu *gpu); 332 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, 333 uint32_t param, uint64_t *value, uint32_t *len); 334 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx, 335 uint32_t param, uint64_t value, uint32_t len); 336 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu, 337 const char *fwname); 338 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 339 const struct firmware *fw, u64 *iova); 340 int adreno_hw_init(struct msm_gpu *gpu); 341 void adreno_recover(struct msm_gpu *gpu); 342 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg); 343 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 344 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 345 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 346 struct drm_printer *p); 347 #endif 348 void adreno_dump_info(struct msm_gpu *gpu); 349 void adreno_dump(struct msm_gpu *gpu); 350 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords); 351 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu); 352 353 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, 354 struct adreno_ocmem *ocmem); 355 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem); 356 357 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 358 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, 359 int nr_rings); 360 void adreno_gpu_cleanup(struct adreno_gpu *gpu); 361 int adreno_load_fw(struct adreno_gpu *adreno_gpu); 362 363 void adreno_gpu_state_destroy(struct msm_gpu_state *state); 364 365 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state); 366 int adreno_gpu_state_put(struct msm_gpu_state *state); 367 void adreno_show_object(struct drm_printer *p, void **ptr, int len, 368 bool *encoded); 369 370 /* 371 * Common helper function to initialize the default address space for arm-smmu 372 * attached targets 373 */ 374 struct msm_gem_address_space * 375 adreno_create_address_space(struct msm_gpu *gpu, 376 struct platform_device *pdev); 377 378 struct msm_gem_address_space * 379 adreno_iommu_create_address_space(struct msm_gpu *gpu, 380 struct platform_device *pdev, 381 unsigned long quirks); 382 383 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, 384 struct adreno_smmu_fault_info *info, const char *block, 385 u32 scratch[4]); 386 387 int adreno_read_speedbin(struct device *dev, u32 *speedbin); 388 389 /* 390 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU 391 * out of secure mode 392 */ 393 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid); 394 395 /* ringbuffer helpers (the parts that are adreno specific) */ 396 397 static inline void 398 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 399 { 400 adreno_wait_ring(ring, cnt+1); 401 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); 402 } 403 404 /* no-op packet: */ 405 static inline void 406 OUT_PKT2(struct msm_ringbuffer *ring) 407 { 408 adreno_wait_ring(ring, 1); 409 OUT_RING(ring, CP_TYPE2_PKT); 410 } 411 412 static inline void 413 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 414 { 415 adreno_wait_ring(ring, cnt+1); 416 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); 417 } 418 419 static inline u32 PM4_PARITY(u32 val) 420 { 421 return (0x9669 >> (0xF & (val ^ 422 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^ 423 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^ 424 (val >> 28)))) & 1; 425 } 426 427 /* Maximum number of values that can be executed for one opcode */ 428 #define TYPE4_MAX_PAYLOAD 127 429 430 #define PKT4(_reg, _cnt) \ 431 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \ 432 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27)) 433 434 static inline void 435 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 436 { 437 adreno_wait_ring(ring, cnt + 1); 438 OUT_RING(ring, PKT4(regindx, cnt)); 439 } 440 441 static inline void 442 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 443 { 444 adreno_wait_ring(ring, cnt + 1); 445 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | 446 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23)); 447 } 448 449 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev); 450 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); 451 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); 452 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev); 453 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev); 454 455 static inline uint32_t get_wptr(struct msm_ringbuffer *ring) 456 { 457 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2); 458 } 459 460 /* 461 * Given a register and a count, return a value to program into 462 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 463 * registers starting at _reg. 464 * 465 * The register base needs to be a multiple of the length. If it is not, the 466 * hardware will quietly mask off the bits for you and shift the size. For 467 * example, if you intend the protection to start at 0x07 for a length of 4 468 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might 469 * expose registers you intended to protect! 470 */ 471 #define ADRENO_PROTECT_RW(_reg, _len) \ 472 ((1 << 30) | (1 << 29) | \ 473 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 474 475 /* 476 * Same as above, but allow reads over the range. For areas of mixed use (such 477 * as performance counters) this allows us to protect a much larger range with a 478 * single register 479 */ 480 #define ADRENO_PROTECT_RDONLY(_reg, _len) \ 481 ((1 << 29) \ 482 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 483 484 485 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \ 486 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \ 487 interval, timeout) 488 489 #endif /* __ADRENO_GPU_H__ */ 490