1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
7  */
8 
9 #ifndef __ADRENO_GPU_H__
10 #define __ADRENO_GPU_H__
11 
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
14 
15 #include "msm_gpu.h"
16 
17 #include "adreno_common.xml.h"
18 #include "adreno_pm4.xml.h"
19 
20 extern bool snapshot_debugbus;
21 extern bool allow_vram_carveout;
22 
23 enum {
24 	ADRENO_FW_PM4 = 0,
25 	ADRENO_FW_SQE = 0, /* a6xx */
26 	ADRENO_FW_PFP = 1,
27 	ADRENO_FW_GMU = 1, /* a6xx */
28 	ADRENO_FW_GPMU = 2,
29 	ADRENO_FW_MAX,
30 };
31 
32 #define ADRENO_QUIRK_TWO_PASS_USE_WFI		BIT(0)
33 #define ADRENO_QUIRK_FAULT_DETECT_MASK		BIT(1)
34 #define ADRENO_QUIRK_LMLOADKILL_DISABLE		BIT(2)
35 
36 struct adreno_rev {
37 	uint8_t  core;
38 	uint8_t  major;
39 	uint8_t  minor;
40 	uint8_t  patchid;
41 };
42 
43 #define ANY_ID 0xff
44 
45 #define ADRENO_REV(core, major, minor, patchid) \
46 	((struct adreno_rev){ core, major, minor, patchid })
47 
48 struct adreno_gpu_funcs {
49 	struct msm_gpu_funcs base;
50 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
51 };
52 
53 struct adreno_reglist {
54 	u32 offset;
55 	u32 value;
56 };
57 
58 extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[], a690_hwcg[];
59 
60 struct adreno_info {
61 	struct adreno_rev rev;
62 	uint32_t revn;
63 	const char *name;
64 	const char *fw[ADRENO_FW_MAX];
65 	uint32_t gmem;
66 	u64 quirks;
67 	struct msm_gpu *(*init)(struct drm_device *dev);
68 	const char *zapfw;
69 	u32 inactive_period;
70 	const struct adreno_reglist *hwcg;
71 	u64 address_space_size;
72 };
73 
74 const struct adreno_info *adreno_info(struct adreno_rev rev);
75 
76 struct adreno_gpu {
77 	struct msm_gpu base;
78 	struct adreno_rev rev;
79 	const struct adreno_info *info;
80 	uint32_t gmem;  /* actual gmem size */
81 	uint32_t revn;  /* numeric revision name */
82 	uint16_t speedbin;
83 	const struct adreno_gpu_funcs *funcs;
84 
85 	/* interesting register offsets to dump: */
86 	const unsigned int *registers;
87 
88 	/*
89 	 * Are we loading fw from legacy path?  Prior to addition
90 	 * of gpu firmware to linux-firmware, the fw files were
91 	 * placed in toplevel firmware directory, following qcom's
92 	 * android kernel.  But linux-firmware preferred they be
93 	 * placed in a 'qcom' subdirectory.
94 	 *
95 	 * For backwards compatibility, we try first to load from
96 	 * the new path, using request_firmware_direct() to avoid
97 	 * any potential timeout waiting for usermode helper, then
98 	 * fall back to the old path (with direct load).  And
99 	 * finally fall back to request_firmware() with the new
100 	 * path to allow the usermode helper.
101 	 */
102 	enum {
103 		FW_LOCATION_UNKNOWN = 0,
104 		FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
105 		FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
106 		FW_LOCATION_HELPER,
107 	} fwloc;
108 
109 	/* firmware: */
110 	const struct firmware *fw[ADRENO_FW_MAX];
111 
112 	/*
113 	 * Register offsets are different between some GPUs.
114 	 * GPU specific offsets will be exported by GPU specific
115 	 * code (a3xx_gpu.c) and stored in this common location.
116 	 */
117 	const unsigned int *reg_offsets;
118 	bool gmu_is_wrapper;
119 };
120 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
121 
122 struct adreno_ocmem {
123 	struct ocmem *ocmem;
124 	unsigned long base;
125 	void *hdl;
126 };
127 
128 /* platform config data (ie. from DT, or pdata) */
129 struct adreno_platform_config {
130 	struct adreno_rev rev;
131 };
132 
133 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
134 
135 #define spin_until(X) ({                                   \
136 	int __ret = -ETIMEDOUT;                            \
137 	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
138 	do {                                               \
139 		if (X) {                                   \
140 			__ret = 0;                         \
141 			break;                             \
142 		}                                          \
143 	} while (time_before(jiffies, __t));               \
144 	__ret;                                             \
145 })
146 
147 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
148 
149 static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
150 {
151 	WARN_ON_ONCE(!gpu->revn);
152 
153 	return gpu->revn == revn;
154 }
155 
156 static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
157 {
158 	return gpu->gmu_is_wrapper;
159 }
160 
161 static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
162 {
163 	WARN_ON_ONCE(!gpu->revn);
164 
165 	return (gpu->revn < 300);
166 }
167 
168 static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
169 {
170 	WARN_ON_ONCE(!gpu->revn);
171 
172 	return (gpu->revn < 210);
173 }
174 
175 static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
176 {
177 	return adreno_is_revn(gpu, 225);
178 }
179 
180 static inline bool adreno_is_a305(const struct adreno_gpu *gpu)
181 {
182 	return adreno_is_revn(gpu, 305);
183 }
184 
185 static inline bool adreno_is_a306(const struct adreno_gpu *gpu)
186 {
187 	/* yes, 307, because a305c is 306 */
188 	return adreno_is_revn(gpu, 307);
189 }
190 
191 static inline bool adreno_is_a320(const struct adreno_gpu *gpu)
192 {
193 	return adreno_is_revn(gpu, 320);
194 }
195 
196 static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
197 {
198 	return adreno_is_revn(gpu, 330);
199 }
200 
201 static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
202 {
203 	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
204 }
205 
206 static inline int adreno_is_a405(const struct adreno_gpu *gpu)
207 {
208 	return adreno_is_revn(gpu, 405);
209 }
210 
211 static inline int adreno_is_a420(const struct adreno_gpu *gpu)
212 {
213 	return adreno_is_revn(gpu, 420);
214 }
215 
216 static inline int adreno_is_a430(const struct adreno_gpu *gpu)
217 {
218 	return adreno_is_revn(gpu, 430);
219 }
220 
221 static inline int adreno_is_a506(const struct adreno_gpu *gpu)
222 {
223 	return adreno_is_revn(gpu, 506);
224 }
225 
226 static inline int adreno_is_a508(const struct adreno_gpu *gpu)
227 {
228 	return adreno_is_revn(gpu, 508);
229 }
230 
231 static inline int adreno_is_a509(const struct adreno_gpu *gpu)
232 {
233 	return adreno_is_revn(gpu, 509);
234 }
235 
236 static inline int adreno_is_a510(const struct adreno_gpu *gpu)
237 {
238 	return adreno_is_revn(gpu, 510);
239 }
240 
241 static inline int adreno_is_a512(const struct adreno_gpu *gpu)
242 {
243 	return adreno_is_revn(gpu, 512);
244 }
245 
246 static inline int adreno_is_a530(const struct adreno_gpu *gpu)
247 {
248 	return adreno_is_revn(gpu, 530);
249 }
250 
251 static inline int adreno_is_a540(const struct adreno_gpu *gpu)
252 {
253 	return adreno_is_revn(gpu, 540);
254 }
255 
256 static inline int adreno_is_a618(const struct adreno_gpu *gpu)
257 {
258 	return adreno_is_revn(gpu, 618);
259 }
260 
261 static inline int adreno_is_a619(const struct adreno_gpu *gpu)
262 {
263 	return adreno_is_revn(gpu, 619);
264 }
265 
266 static inline int adreno_is_a630(const struct adreno_gpu *gpu)
267 {
268 	return adreno_is_revn(gpu, 630);
269 }
270 
271 static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
272 {
273 	return adreno_is_revn(gpu, 640) ||
274 		adreno_is_revn(gpu, 680);
275 }
276 
277 static inline int adreno_is_a650(const struct adreno_gpu *gpu)
278 {
279 	return adreno_is_revn(gpu, 650);
280 }
281 
282 static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
283 {
284 	/* The order of args is important here to handle ANY_ID correctly */
285 	return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
286 }
287 
288 static inline int adreno_is_a660(const struct adreno_gpu *gpu)
289 {
290 	return adreno_is_revn(gpu, 660);
291 }
292 
293 static inline int adreno_is_a690(const struct adreno_gpu *gpu)
294 {
295 	return adreno_is_revn(gpu, 690);
296 };
297 
298 /* check for a615, a616, a618, a619 or any derivatives */
299 static inline int adreno_is_a615_family(const struct adreno_gpu *gpu)
300 {
301 	return adreno_is_revn(gpu, 615) ||
302 		adreno_is_revn(gpu, 616) ||
303 		adreno_is_revn(gpu, 618) ||
304 		adreno_is_revn(gpu, 619);
305 }
306 
307 static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
308 {
309 	return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu);
310 }
311 
312 /* check for a650, a660, or any derivatives */
313 static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
314 {
315 	return adreno_is_revn(gpu, 650) ||
316 		adreno_is_revn(gpu, 620) ||
317 		adreno_is_a660_family(gpu);
318 }
319 
320 u64 adreno_private_address_space_size(struct msm_gpu *gpu);
321 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
322 		     uint32_t param, uint64_t *value, uint32_t *len);
323 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
324 		     uint32_t param, uint64_t value, uint32_t len);
325 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
326 		const char *fwname);
327 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
328 		const struct firmware *fw, u64 *iova);
329 int adreno_hw_init(struct msm_gpu *gpu);
330 void adreno_recover(struct msm_gpu *gpu);
331 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
332 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
333 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
334 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
335 		struct drm_printer *p);
336 #endif
337 void adreno_dump_info(struct msm_gpu *gpu);
338 void adreno_dump(struct msm_gpu *gpu);
339 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
340 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
341 
342 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
343 			  struct adreno_ocmem *ocmem);
344 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
345 
346 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
347 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
348 		int nr_rings);
349 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
350 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
351 
352 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
353 
354 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
355 int adreno_gpu_state_put(struct msm_gpu_state *state);
356 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
357 		bool *encoded);
358 
359 /*
360  * Common helper function to initialize the default address space for arm-smmu
361  * attached targets
362  */
363 struct msm_gem_address_space *
364 adreno_create_address_space(struct msm_gpu *gpu,
365 			    struct platform_device *pdev);
366 
367 struct msm_gem_address_space *
368 adreno_iommu_create_address_space(struct msm_gpu *gpu,
369 				  struct platform_device *pdev,
370 				  unsigned long quirks);
371 
372 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
373 			 struct adreno_smmu_fault_info *info, const char *block,
374 			 u32 scratch[4]);
375 
376 int adreno_read_speedbin(struct device *dev, u32 *speedbin);
377 
378 /*
379  * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
380  * out of secure mode
381  */
382 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
383 
384 /* ringbuffer helpers (the parts that are adreno specific) */
385 
386 static inline void
387 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
388 {
389 	adreno_wait_ring(ring, cnt+1);
390 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
391 }
392 
393 /* no-op packet: */
394 static inline void
395 OUT_PKT2(struct msm_ringbuffer *ring)
396 {
397 	adreno_wait_ring(ring, 1);
398 	OUT_RING(ring, CP_TYPE2_PKT);
399 }
400 
401 static inline void
402 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
403 {
404 	adreno_wait_ring(ring, cnt+1);
405 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
406 }
407 
408 static inline u32 PM4_PARITY(u32 val)
409 {
410 	return (0x9669 >> (0xF & (val ^
411 		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
412 		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
413 		(val >> 28)))) & 1;
414 }
415 
416 /* Maximum number of values that can be executed for one opcode */
417 #define TYPE4_MAX_PAYLOAD 127
418 
419 #define PKT4(_reg, _cnt) \
420 	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
421 	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
422 
423 static inline void
424 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
425 {
426 	adreno_wait_ring(ring, cnt + 1);
427 	OUT_RING(ring, PKT4(regindx, cnt));
428 }
429 
430 static inline void
431 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
432 {
433 	adreno_wait_ring(ring, cnt + 1);
434 	OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
435 		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
436 }
437 
438 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
439 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
440 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
441 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
442 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
443 
444 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
445 {
446 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
447 }
448 
449 /*
450  * Given a register and a count, return a value to program into
451  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
452  * registers starting at _reg.
453  *
454  * The register base needs to be a multiple of the length. If it is not, the
455  * hardware will quietly mask off the bits for you and shift the size. For
456  * example, if you intend the protection to start at 0x07 for a length of 4
457  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
458  * expose registers you intended to protect!
459  */
460 #define ADRENO_PROTECT_RW(_reg, _len) \
461 	((1 << 30) | (1 << 29) | \
462 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
463 
464 /*
465  * Same as above, but allow reads over the range. For areas of mixed use (such
466  * as performance counters) this allows us to protect a much larger range with a
467  * single register
468  */
469 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
470 	((1 << 29) \
471 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
472 
473 
474 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
475 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
476 		interval, timeout)
477 
478 #endif /* __ADRENO_GPU_H__ */
479