1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
7  */
8 
9 #ifndef __ADRENO_GPU_H__
10 #define __ADRENO_GPU_H__
11 
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
14 
15 #include "msm_gpu.h"
16 
17 #include "adreno_common.xml.h"
18 #include "adreno_pm4.xml.h"
19 
20 extern bool snapshot_debugbus;
21 extern bool allow_vram_carveout;
22 
23 enum {
24 	ADRENO_FW_PM4 = 0,
25 	ADRENO_FW_SQE = 0, /* a6xx */
26 	ADRENO_FW_PFP = 1,
27 	ADRENO_FW_GMU = 1, /* a6xx */
28 	ADRENO_FW_GPMU = 2,
29 	ADRENO_FW_MAX,
30 };
31 
32 /**
33  * @enum adreno_family: identify generation and possibly sub-generation
34  *
35  * In some cases there are distinct sub-generations within a major revision
36  * so it helps to be able to group the GPU devices by generation and if
37  * necessary sub-generation.
38  */
39 enum adreno_family {
40 	ADRENO_2XX_GEN1,  /* a20x */
41 	ADRENO_2XX_GEN2,  /* a22x */
42 	ADRENO_3XX,
43 	ADRENO_4XX,
44 	ADRENO_5XX,
45 	ADRENO_6XX_GEN1,  /* a630 family */
46 	ADRENO_6XX_GEN2,  /* a640 family */
47 	ADRENO_6XX_GEN3,  /* a650 family */
48 	ADRENO_6XX_GEN4,  /* a660 family */
49 };
50 
51 #define ADRENO_QUIRK_TWO_PASS_USE_WFI		BIT(0)
52 #define ADRENO_QUIRK_FAULT_DETECT_MASK		BIT(1)
53 #define ADRENO_QUIRK_LMLOADKILL_DISABLE		BIT(2)
54 #define ADRENO_QUIRK_HAS_HW_APRIV		BIT(3)
55 #define ADRENO_QUIRK_HAS_CACHED_COHERENT	BIT(4)
56 
57 struct adreno_rev {
58 	uint8_t  core;
59 	uint8_t  major;
60 	uint8_t  minor;
61 	uint8_t  patchid;
62 };
63 
64 #define ANY_ID 0xff
65 
66 #define ADRENO_REV(core, major, minor, patchid) \
67 	((struct adreno_rev){ core, major, minor, patchid })
68 
69 /* Helper for formating the chip_id in the way that userspace tools like
70  * crashdec expect.
71  */
72 #define ADRENO_CHIPID_FMT "u.%u.%u.%u"
73 #define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid
74 
75 struct adreno_gpu_funcs {
76 	struct msm_gpu_funcs base;
77 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
78 };
79 
80 struct adreno_reglist {
81 	u32 offset;
82 	u32 value;
83 };
84 
85 extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[];
86 extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
87 
88 struct adreno_speedbin {
89 	uint16_t fuse;
90 	uint16_t speedbin;
91 };
92 
93 struct adreno_info {
94 	const char *machine;
95 	struct adreno_rev rev;
96 	enum adreno_family family;
97 	uint32_t revn;
98 	const char *fw[ADRENO_FW_MAX];
99 	uint32_t gmem;
100 	u64 quirks;
101 	struct msm_gpu *(*init)(struct drm_device *dev);
102 	const char *zapfw;
103 	u32 inactive_period;
104 	const struct adreno_reglist *hwcg;
105 	u64 address_space_size;
106 	/**
107 	 * @speedbins: Optional table of fuse to speedbin mappings
108 	 *
109 	 * Consists of pairs of fuse, index mappings, terminated with
110 	 * {SHRT_MAX, 0} sentinal.
111 	 */
112 	struct adreno_speedbin *speedbins;
113 };
114 
115 /*
116  * Helper to build a speedbin table, ie. the table:
117  *      fuse | speedbin
118  *      -----+---------
119  *        0  |   0
120  *       169 |   1
121  *       174 |   2
122  *
123  * would be declared as:
124  *
125  *     .speedbins = ADRENO_SPEEDBINS(
126  *                      { 0,   0 },
127  *                      { 169, 1 },
128  *                      { 174, 2 },
129  *     ),
130  */
131 #define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} }
132 
133 const struct adreno_info *adreno_info(struct adreno_rev rev);
134 
135 struct adreno_gpu {
136 	struct msm_gpu base;
137 	struct adreno_rev rev;
138 	const struct adreno_info *info;
139 	uint16_t speedbin;
140 	const struct adreno_gpu_funcs *funcs;
141 
142 	/* interesting register offsets to dump: */
143 	const unsigned int *registers;
144 
145 	/*
146 	 * Are we loading fw from legacy path?  Prior to addition
147 	 * of gpu firmware to linux-firmware, the fw files were
148 	 * placed in toplevel firmware directory, following qcom's
149 	 * android kernel.  But linux-firmware preferred they be
150 	 * placed in a 'qcom' subdirectory.
151 	 *
152 	 * For backwards compatibility, we try first to load from
153 	 * the new path, using request_firmware_direct() to avoid
154 	 * any potential timeout waiting for usermode helper, then
155 	 * fall back to the old path (with direct load).  And
156 	 * finally fall back to request_firmware() with the new
157 	 * path to allow the usermode helper.
158 	 */
159 	enum {
160 		FW_LOCATION_UNKNOWN = 0,
161 		FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
162 		FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
163 		FW_LOCATION_HELPER,
164 	} fwloc;
165 
166 	/* firmware: */
167 	const struct firmware *fw[ADRENO_FW_MAX];
168 
169 	/*
170 	 * Register offsets are different between some GPUs.
171 	 * GPU specific offsets will be exported by GPU specific
172 	 * code (a3xx_gpu.c) and stored in this common location.
173 	 */
174 	const unsigned int *reg_offsets;
175 	bool gmu_is_wrapper;
176 };
177 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
178 
179 struct adreno_ocmem {
180 	struct ocmem *ocmem;
181 	unsigned long base;
182 	void *hdl;
183 };
184 
185 /* platform config data (ie. from DT, or pdata) */
186 struct adreno_platform_config {
187 	struct adreno_rev rev;
188 };
189 
190 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
191 
192 #define spin_until(X) ({                                   \
193 	int __ret = -ETIMEDOUT;                            \
194 	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
195 	do {                                               \
196 		if (X) {                                   \
197 			__ret = 0;                         \
198 			break;                             \
199 		}                                          \
200 	} while (time_before(jiffies, __t));               \
201 	__ret;                                             \
202 })
203 
204 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
205 
206 static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn)
207 {
208 	if (WARN_ON_ONCE(!gpu->info))
209 		return false;
210 	return gpu->info->revn == revn;
211 }
212 
213 static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)
214 {
215 	return gpu->gmu_is_wrapper;
216 }
217 
218 static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu)
219 {
220 	if (WARN_ON_ONCE(!gpu->info))
221 		return false;
222 	return gpu->info->family <= ADRENO_2XX_GEN2;
223 }
224 
225 static inline bool adreno_is_a20x(const struct adreno_gpu *gpu)
226 {
227 	if (WARN_ON_ONCE(!gpu->info))
228 		return false;
229 	return gpu->info->family == ADRENO_2XX_GEN1;
230 }
231 
232 static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
233 {
234 	return adreno_is_revn(gpu, 225);
235 }
236 
237 static inline bool adreno_is_a305(const struct adreno_gpu *gpu)
238 {
239 	return adreno_is_revn(gpu, 305);
240 }
241 
242 static inline bool adreno_is_a306(const struct adreno_gpu *gpu)
243 {
244 	/* yes, 307, because a305c is 306 */
245 	return adreno_is_revn(gpu, 307);
246 }
247 
248 static inline bool adreno_is_a320(const struct adreno_gpu *gpu)
249 {
250 	return adreno_is_revn(gpu, 320);
251 }
252 
253 static inline bool adreno_is_a330(const struct adreno_gpu *gpu)
254 {
255 	return adreno_is_revn(gpu, 330);
256 }
257 
258 static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu)
259 {
260 	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
261 }
262 
263 static inline int adreno_is_a405(const struct adreno_gpu *gpu)
264 {
265 	return adreno_is_revn(gpu, 405);
266 }
267 
268 static inline int adreno_is_a420(const struct adreno_gpu *gpu)
269 {
270 	return adreno_is_revn(gpu, 420);
271 }
272 
273 static inline int adreno_is_a430(const struct adreno_gpu *gpu)
274 {
275 	return adreno_is_revn(gpu, 430);
276 }
277 
278 static inline int adreno_is_a506(const struct adreno_gpu *gpu)
279 {
280 	return adreno_is_revn(gpu, 506);
281 }
282 
283 static inline int adreno_is_a508(const struct adreno_gpu *gpu)
284 {
285 	return adreno_is_revn(gpu, 508);
286 }
287 
288 static inline int adreno_is_a509(const struct adreno_gpu *gpu)
289 {
290 	return adreno_is_revn(gpu, 509);
291 }
292 
293 static inline int adreno_is_a510(const struct adreno_gpu *gpu)
294 {
295 	return adreno_is_revn(gpu, 510);
296 }
297 
298 static inline int adreno_is_a512(const struct adreno_gpu *gpu)
299 {
300 	return adreno_is_revn(gpu, 512);
301 }
302 
303 static inline int adreno_is_a530(const struct adreno_gpu *gpu)
304 {
305 	return adreno_is_revn(gpu, 530);
306 }
307 
308 static inline int adreno_is_a540(const struct adreno_gpu *gpu)
309 {
310 	return adreno_is_revn(gpu, 540);
311 }
312 
313 static inline int adreno_is_a610(const struct adreno_gpu *gpu)
314 {
315 	return adreno_is_revn(gpu, 610);
316 }
317 
318 static inline int adreno_is_a618(const struct adreno_gpu *gpu)
319 {
320 	return adreno_is_revn(gpu, 618);
321 }
322 
323 static inline int adreno_is_a619(const struct adreno_gpu *gpu)
324 {
325 	return adreno_is_revn(gpu, 619);
326 }
327 
328 static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu)
329 {
330 	return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu);
331 }
332 
333 static inline int adreno_is_a630(const struct adreno_gpu *gpu)
334 {
335 	return adreno_is_revn(gpu, 630);
336 }
337 
338 static inline int adreno_is_a640(const struct adreno_gpu *gpu)
339 {
340 	return adreno_is_revn(gpu, 640);
341 }
342 
343 static inline int adreno_is_a650(const struct adreno_gpu *gpu)
344 {
345 	return adreno_is_revn(gpu, 650);
346 }
347 
348 static inline int adreno_is_7c3(const struct adreno_gpu *gpu)
349 {
350 	/* The order of args is important here to handle ANY_ID correctly */
351 	return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
352 }
353 
354 static inline int adreno_is_a660(const struct adreno_gpu *gpu)
355 {
356 	return adreno_is_revn(gpu, 660);
357 }
358 
359 static inline int adreno_is_a680(const struct adreno_gpu *gpu)
360 {
361 	return adreno_is_revn(gpu, 680);
362 }
363 
364 static inline int adreno_is_a690(const struct adreno_gpu *gpu)
365 {
366 	/* The order of args is important here to handle ANY_ID correctly */
367 	return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev);
368 }
369 
370 /* check for a615, a616, a618, a619 or any a630 derivatives */
371 static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
372 {
373 	if (WARN_ON_ONCE(!gpu->info))
374 		return false;
375 	return gpu->info->family == ADRENO_6XX_GEN1;
376 }
377 
378 static inline int adreno_is_a660_family(const struct adreno_gpu *gpu)
379 {
380 	if (WARN_ON_ONCE(!gpu->info))
381 		return false;
382 	return gpu->info->family == ADRENO_6XX_GEN4;
383 }
384 
385 /* check for a650, a660, or any derivatives */
386 static inline int adreno_is_a650_family(const struct adreno_gpu *gpu)
387 {
388 	if (WARN_ON_ONCE(!gpu->info))
389 		return false;
390 	return gpu->info->family >= ADRENO_6XX_GEN3;
391 }
392 
393 static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
394 {
395 	if (WARN_ON_ONCE(!gpu->info))
396 		return false;
397 	return gpu->info->family == ADRENO_6XX_GEN2;
398 }
399 
400 u64 adreno_private_address_space_size(struct msm_gpu *gpu);
401 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
402 		     uint32_t param, uint64_t *value, uint32_t *len);
403 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
404 		     uint32_t param, uint64_t value, uint32_t len);
405 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
406 		const char *fwname);
407 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
408 		const struct firmware *fw, u64 *iova);
409 int adreno_hw_init(struct msm_gpu *gpu);
410 void adreno_recover(struct msm_gpu *gpu);
411 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
412 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
413 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
414 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
415 		struct drm_printer *p);
416 #endif
417 void adreno_dump_info(struct msm_gpu *gpu);
418 void adreno_dump(struct msm_gpu *gpu);
419 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
420 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
421 
422 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
423 			  struct adreno_ocmem *ocmem);
424 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
425 
426 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
427 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
428 		int nr_rings);
429 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
430 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
431 
432 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
433 
434 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
435 int adreno_gpu_state_put(struct msm_gpu_state *state);
436 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
437 		bool *encoded);
438 
439 /*
440  * Common helper function to initialize the default address space for arm-smmu
441  * attached targets
442  */
443 struct msm_gem_address_space *
444 adreno_create_address_space(struct msm_gpu *gpu,
445 			    struct platform_device *pdev);
446 
447 struct msm_gem_address_space *
448 adreno_iommu_create_address_space(struct msm_gpu *gpu,
449 				  struct platform_device *pdev,
450 				  unsigned long quirks);
451 
452 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
453 			 struct adreno_smmu_fault_info *info, const char *block,
454 			 u32 scratch[4]);
455 
456 int adreno_read_speedbin(struct device *dev, u32 *speedbin);
457 
458 /*
459  * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
460  * out of secure mode
461  */
462 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
463 
464 /* ringbuffer helpers (the parts that are adreno specific) */
465 
466 static inline void
467 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
468 {
469 	adreno_wait_ring(ring, cnt+1);
470 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
471 }
472 
473 /* no-op packet: */
474 static inline void
475 OUT_PKT2(struct msm_ringbuffer *ring)
476 {
477 	adreno_wait_ring(ring, 1);
478 	OUT_RING(ring, CP_TYPE2_PKT);
479 }
480 
481 static inline void
482 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
483 {
484 	adreno_wait_ring(ring, cnt+1);
485 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
486 }
487 
488 static inline u32 PM4_PARITY(u32 val)
489 {
490 	return (0x9669 >> (0xF & (val ^
491 		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
492 		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
493 		(val >> 28)))) & 1;
494 }
495 
496 /* Maximum number of values that can be executed for one opcode */
497 #define TYPE4_MAX_PAYLOAD 127
498 
499 #define PKT4(_reg, _cnt) \
500 	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
501 	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
502 
503 static inline void
504 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
505 {
506 	adreno_wait_ring(ring, cnt + 1);
507 	OUT_RING(ring, PKT4(regindx, cnt));
508 }
509 
510 static inline void
511 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
512 {
513 	adreno_wait_ring(ring, cnt + 1);
514 	OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
515 		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
516 }
517 
518 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
519 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
520 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
521 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
522 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
523 
524 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
525 {
526 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
527 }
528 
529 /*
530  * Given a register and a count, return a value to program into
531  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
532  * registers starting at _reg.
533  *
534  * The register base needs to be a multiple of the length. If it is not, the
535  * hardware will quietly mask off the bits for you and shift the size. For
536  * example, if you intend the protection to start at 0x07 for a length of 4
537  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
538  * expose registers you intended to protect!
539  */
540 #define ADRENO_PROTECT_RW(_reg, _len) \
541 	((1 << 30) | (1 << 29) | \
542 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
543 
544 /*
545  * Same as above, but allow reads over the range. For areas of mixed use (such
546  * as performance counters) this allows us to protect a much larger range with a
547  * single register
548  */
549 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
550 	((1 << 29) \
551 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
552 
553 
554 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
555 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
556 		interval, timeout)
557 
558 #endif /* __ADRENO_GPU_H__ */
559