1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved. 7 */ 8 9 #ifndef __ADRENO_GPU_H__ 10 #define __ADRENO_GPU_H__ 11 12 #include <linux/firmware.h> 13 #include <linux/iopoll.h> 14 15 #include "msm_gpu.h" 16 17 #include "adreno_common.xml.h" 18 #include "adreno_pm4.xml.h" 19 20 extern bool snapshot_debugbus; 21 extern bool allow_vram_carveout; 22 23 enum { 24 ADRENO_FW_PM4 = 0, 25 ADRENO_FW_SQE = 0, /* a6xx */ 26 ADRENO_FW_PFP = 1, 27 ADRENO_FW_GMU = 1, /* a6xx */ 28 ADRENO_FW_GPMU = 2, 29 ADRENO_FW_MAX, 30 }; 31 32 #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) 33 #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) 34 #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) 35 36 struct adreno_rev { 37 uint8_t core; 38 uint8_t major; 39 uint8_t minor; 40 uint8_t patchid; 41 }; 42 43 #define ANY_ID 0xff 44 45 #define ADRENO_REV(core, major, minor, patchid) \ 46 ((struct adreno_rev){ core, major, minor, patchid }) 47 48 struct adreno_gpu_funcs { 49 struct msm_gpu_funcs base; 50 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); 51 }; 52 53 struct adreno_reglist { 54 u32 offset; 55 u32 value; 56 }; 57 58 extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[], a690_hwcg[]; 59 60 struct adreno_info { 61 struct adreno_rev rev; 62 uint32_t revn; 63 const char *name; 64 const char *fw[ADRENO_FW_MAX]; 65 uint32_t gmem; 66 u64 quirks; 67 struct msm_gpu *(*init)(struct drm_device *dev); 68 const char *zapfw; 69 u32 inactive_period; 70 const struct adreno_reglist *hwcg; 71 u64 address_space_size; 72 }; 73 74 const struct adreno_info *adreno_info(struct adreno_rev rev); 75 76 struct adreno_gpu { 77 struct msm_gpu base; 78 struct adreno_rev rev; 79 const struct adreno_info *info; 80 uint32_t gmem; /* actual gmem size */ 81 uint32_t revn; /* numeric revision name */ 82 uint16_t speedbin; 83 const struct adreno_gpu_funcs *funcs; 84 85 /* interesting register offsets to dump: */ 86 const unsigned int *registers; 87 88 /* 89 * Are we loading fw from legacy path? Prior to addition 90 * of gpu firmware to linux-firmware, the fw files were 91 * placed in toplevel firmware directory, following qcom's 92 * android kernel. But linux-firmware preferred they be 93 * placed in a 'qcom' subdirectory. 94 * 95 * For backwards compatibility, we try first to load from 96 * the new path, using request_firmware_direct() to avoid 97 * any potential timeout waiting for usermode helper, then 98 * fall back to the old path (with direct load). And 99 * finally fall back to request_firmware() with the new 100 * path to allow the usermode helper. 101 */ 102 enum { 103 FW_LOCATION_UNKNOWN = 0, 104 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */ 105 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */ 106 FW_LOCATION_HELPER, 107 } fwloc; 108 109 /* firmware: */ 110 const struct firmware *fw[ADRENO_FW_MAX]; 111 112 /* 113 * Register offsets are different between some GPUs. 114 * GPU specific offsets will be exported by GPU specific 115 * code (a3xx_gpu.c) and stored in this common location. 116 */ 117 const unsigned int *reg_offsets; 118 }; 119 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) 120 121 struct adreno_ocmem { 122 struct ocmem *ocmem; 123 unsigned long base; 124 void *hdl; 125 }; 126 127 /* platform config data (ie. from DT, or pdata) */ 128 struct adreno_platform_config { 129 struct adreno_rev rev; 130 }; 131 132 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) 133 134 #define spin_until(X) ({ \ 135 int __ret = -ETIMEDOUT; \ 136 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \ 137 do { \ 138 if (X) { \ 139 __ret = 0; \ 140 break; \ 141 } \ 142 } while (time_before(jiffies, __t)); \ 143 __ret; \ 144 }) 145 146 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); 147 148 static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) 149 { 150 WARN_ON_ONCE(!gpu->revn); 151 152 return gpu->revn == revn; 153 } 154 155 static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) 156 { 157 WARN_ON_ONCE(!gpu->revn); 158 159 return (gpu->revn < 300); 160 } 161 162 static inline bool adreno_is_a20x(const struct adreno_gpu *gpu) 163 { 164 WARN_ON_ONCE(!gpu->revn); 165 166 return (gpu->revn < 210); 167 } 168 169 static inline bool adreno_is_a225(const struct adreno_gpu *gpu) 170 { 171 return adreno_is_revn(gpu, 225); 172 } 173 174 static inline bool adreno_is_a305(const struct adreno_gpu *gpu) 175 { 176 return adreno_is_revn(gpu, 305); 177 } 178 179 static inline bool adreno_is_a306(const struct adreno_gpu *gpu) 180 { 181 /* yes, 307, because a305c is 306 */ 182 return adreno_is_revn(gpu, 307); 183 } 184 185 static inline bool adreno_is_a320(const struct adreno_gpu *gpu) 186 { 187 return adreno_is_revn(gpu, 320); 188 } 189 190 static inline bool adreno_is_a330(const struct adreno_gpu *gpu) 191 { 192 return adreno_is_revn(gpu, 330); 193 } 194 195 static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu) 196 { 197 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0); 198 } 199 200 static inline int adreno_is_a405(const struct adreno_gpu *gpu) 201 { 202 return adreno_is_revn(gpu, 405); 203 } 204 205 static inline int adreno_is_a420(const struct adreno_gpu *gpu) 206 { 207 return adreno_is_revn(gpu, 420); 208 } 209 210 static inline int adreno_is_a430(const struct adreno_gpu *gpu) 211 { 212 return adreno_is_revn(gpu, 430); 213 } 214 215 static inline int adreno_is_a506(const struct adreno_gpu *gpu) 216 { 217 return adreno_is_revn(gpu, 506); 218 } 219 220 static inline int adreno_is_a508(const struct adreno_gpu *gpu) 221 { 222 return adreno_is_revn(gpu, 508); 223 } 224 225 static inline int adreno_is_a509(const struct adreno_gpu *gpu) 226 { 227 return adreno_is_revn(gpu, 509); 228 } 229 230 static inline int adreno_is_a510(const struct adreno_gpu *gpu) 231 { 232 return adreno_is_revn(gpu, 510); 233 } 234 235 static inline int adreno_is_a512(const struct adreno_gpu *gpu) 236 { 237 return adreno_is_revn(gpu, 512); 238 } 239 240 static inline int adreno_is_a530(const struct adreno_gpu *gpu) 241 { 242 return adreno_is_revn(gpu, 530); 243 } 244 245 static inline int adreno_is_a540(const struct adreno_gpu *gpu) 246 { 247 return adreno_is_revn(gpu, 540); 248 } 249 250 static inline int adreno_is_a618(const struct adreno_gpu *gpu) 251 { 252 return adreno_is_revn(gpu, 618); 253 } 254 255 static inline int adreno_is_a619(const struct adreno_gpu *gpu) 256 { 257 return adreno_is_revn(gpu, 619); 258 } 259 260 static inline int adreno_is_a630(const struct adreno_gpu *gpu) 261 { 262 return adreno_is_revn(gpu, 630); 263 } 264 265 static inline int adreno_is_a640_family(const struct adreno_gpu *gpu) 266 { 267 return adreno_is_revn(gpu, 640) || 268 adreno_is_revn(gpu, 680); 269 } 270 271 static inline int adreno_is_a650(const struct adreno_gpu *gpu) 272 { 273 return adreno_is_revn(gpu, 650); 274 } 275 276 static inline int adreno_is_7c3(const struct adreno_gpu *gpu) 277 { 278 /* The order of args is important here to handle ANY_ID correctly */ 279 return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev); 280 } 281 282 static inline int adreno_is_a660(const struct adreno_gpu *gpu) 283 { 284 return adreno_is_revn(gpu, 660); 285 } 286 287 static inline int adreno_is_a690(struct adreno_gpu *gpu) 288 { 289 return gpu->revn == 690; 290 }; 291 292 /* check for a615, a616, a618, a619 or any derivatives */ 293 static inline int adreno_is_a615_family(const struct adreno_gpu *gpu) 294 { 295 return adreno_is_revn(gpu, 615) || 296 adreno_is_revn(gpu, 616) || 297 adreno_is_revn(gpu, 618) || 298 adreno_is_revn(gpu, 619); 299 } 300 301 static inline int adreno_is_a660_family(const struct adreno_gpu *gpu) 302 { 303 return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu); 304 } 305 306 /* check for a650, a660, or any derivatives */ 307 static inline int adreno_is_a650_family(const struct adreno_gpu *gpu) 308 { 309 return adreno_is_revn(gpu, 650) || 310 adreno_is_revn(gpu, 620) || 311 adreno_is_a660_family(gpu); 312 } 313 314 u64 adreno_private_address_space_size(struct msm_gpu *gpu); 315 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, 316 uint32_t param, uint64_t *value, uint32_t *len); 317 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx, 318 uint32_t param, uint64_t value, uint32_t len); 319 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu, 320 const char *fwname); 321 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 322 const struct firmware *fw, u64 *iova); 323 int adreno_hw_init(struct msm_gpu *gpu); 324 void adreno_recover(struct msm_gpu *gpu); 325 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg); 326 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 327 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 328 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 329 struct drm_printer *p); 330 #endif 331 void adreno_dump_info(struct msm_gpu *gpu); 332 void adreno_dump(struct msm_gpu *gpu); 333 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords); 334 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu); 335 336 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, 337 struct adreno_ocmem *ocmem); 338 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem); 339 340 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 341 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, 342 int nr_rings); 343 void adreno_gpu_cleanup(struct adreno_gpu *gpu); 344 int adreno_load_fw(struct adreno_gpu *adreno_gpu); 345 346 void adreno_gpu_state_destroy(struct msm_gpu_state *state); 347 348 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state); 349 int adreno_gpu_state_put(struct msm_gpu_state *state); 350 void adreno_show_object(struct drm_printer *p, void **ptr, int len, 351 bool *encoded); 352 353 /* 354 * Common helper function to initialize the default address space for arm-smmu 355 * attached targets 356 */ 357 struct msm_gem_address_space * 358 adreno_create_address_space(struct msm_gpu *gpu, 359 struct platform_device *pdev); 360 361 struct msm_gem_address_space * 362 adreno_iommu_create_address_space(struct msm_gpu *gpu, 363 struct platform_device *pdev, 364 unsigned long quirks); 365 366 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, 367 struct adreno_smmu_fault_info *info, const char *block, 368 u32 scratch[4]); 369 370 int adreno_read_speedbin(struct device *dev, u32 *speedbin); 371 372 /* 373 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU 374 * out of secure mode 375 */ 376 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid); 377 378 /* ringbuffer helpers (the parts that are adreno specific) */ 379 380 static inline void 381 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 382 { 383 adreno_wait_ring(ring, cnt+1); 384 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); 385 } 386 387 /* no-op packet: */ 388 static inline void 389 OUT_PKT2(struct msm_ringbuffer *ring) 390 { 391 adreno_wait_ring(ring, 1); 392 OUT_RING(ring, CP_TYPE2_PKT); 393 } 394 395 static inline void 396 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 397 { 398 adreno_wait_ring(ring, cnt+1); 399 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); 400 } 401 402 static inline u32 PM4_PARITY(u32 val) 403 { 404 return (0x9669 >> (0xF & (val ^ 405 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^ 406 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^ 407 (val >> 28)))) & 1; 408 } 409 410 /* Maximum number of values that can be executed for one opcode */ 411 #define TYPE4_MAX_PAYLOAD 127 412 413 #define PKT4(_reg, _cnt) \ 414 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \ 415 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27)) 416 417 static inline void 418 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 419 { 420 adreno_wait_ring(ring, cnt + 1); 421 OUT_RING(ring, PKT4(regindx, cnt)); 422 } 423 424 static inline void 425 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 426 { 427 adreno_wait_ring(ring, cnt + 1); 428 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | 429 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23)); 430 } 431 432 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev); 433 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); 434 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); 435 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev); 436 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev); 437 438 static inline uint32_t get_wptr(struct msm_ringbuffer *ring) 439 { 440 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2); 441 } 442 443 /* 444 * Given a register and a count, return a value to program into 445 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 446 * registers starting at _reg. 447 * 448 * The register base needs to be a multiple of the length. If it is not, the 449 * hardware will quietly mask off the bits for you and shift the size. For 450 * example, if you intend the protection to start at 0x07 for a length of 4 451 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might 452 * expose registers you intended to protect! 453 */ 454 #define ADRENO_PROTECT_RW(_reg, _len) \ 455 ((1 << 30) | (1 << 29) | \ 456 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 457 458 /* 459 * Same as above, but allow reads over the range. For areas of mixed use (such 460 * as performance counters) this allows us to protect a much larger range with a 461 * single register 462 */ 463 #define ADRENO_PROTECT_RDONLY(_reg, _len) \ 464 ((1 << 29) \ 465 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 466 467 468 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \ 469 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \ 470 interval, timeout) 471 472 #endif /* __ADRENO_GPU_H__ */ 473