3604b451 | 09-Apr-2016 |
Álvaro Fernández Rojas <noltari@gmail.com> |
MIPS: BMIPS: Add BCM6358 support
BCM6358 has a shared TLB which conflicts with current SMP support, so it must be disabled for now. BCM6358 uses >= 0xfffe0000 addresses for internal registers, which
MIPS: BMIPS: Add BCM6358 support
BCM6358 has a shared TLB which conflicts with current SMP support, so it must be disabled for now. BCM6358 uses >= 0xfffe0000 addresses for internal registers, which need to be remapped (by using a simplified version of BRCM63xx ioremap.h). However, 0xfff80000 is a better address, since it also covers BCM3368, leaving the possibility to add it in the future.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Cc: f.fainelli@gmail.com Cc: jogo@openwrt.org Cc: cernekee@gmail.com Cc: robh@kernel.org Cc: simon@fire.lp0.eu Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13040/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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554b7f56 | 27-Mar-2015 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: BMIPS: Flush the readahead cache after DMA.
BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer may cau
MIPS: BMIPS: Flush the readahead cache after DMA.
BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer may cause parts of the DMA buffer to be prefetched into the RAC. To avoid possible coherency problems, flush the RAC upon DMA completion.
Derived from Kevin Cernekee's https://patchwork.linux-mips.org/patch/9602/.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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