Home
last modified time | relevance | path

Searched refs:active_fpu (Results 1 – 15 of 15) sorted by relevance

/openbmc/qemu/target/mips/tcg/
H A Dfpu_helper.c46 arg1 = (int32_t)env->active_fpu.fcr0; in helper_cfc1()
50 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) { in helper_cfc1()
61 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { in helper_cfc1()
70 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | in helper_cfc1()
71 ((env->active_fpu.fcr31 >> 23) & 0x1); in helper_cfc1()
74 arg1 = env->active_fpu.fcr31 & 0x0003f07c; in helper_cfc1()
77 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | in helper_cfc1()
78 ((env->active_fpu.fcr31 >> 22) & 0x4); in helper_cfc1()
81 arg1 = (int32_t)env->active_fpu.fcr31; in helper_cfc1()
93 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) { in helper_ctc1()
[all …]
H A Dmsa_helper.c100 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); in helper_msa_nloc_b()
101 wr_t *pws = &(env->active_fpu.fpr[ws].wr); in helper_msa_nloc_b()
123 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); in helper_msa_nloc_h()
124 wr_t *pws = &(env->active_fpu.fpr[ws].wr); in helper_msa_nloc_h()
138 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); in helper_msa_nloc_w()
139 wr_t *pws = &(env->active_fpu.fpr[ws].wr); in helper_msa_nloc_w()
149 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); in helper_msa_nloc_d()
150 wr_t *pws = &(env->active_fpu.fpr[ws].wr); in helper_msa_nloc_d()
158 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); in helper_msa_nlzc_b()
159 wr_t *pws = &(env->active_fpu.fpr[ws].wr); in helper_msa_nlzc_b()
[all …]
H A Dmsa_translate.c138 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); in msa_translate_init()
141 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); in msa_translate_init()
H A Dtranslate.c15089 ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || in mips_tr_init_disas_context()
15093 ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; in mips_tr_init_disas_context()
15094 ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; in mips_tr_init_disas_context()
15263 int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); in mips_tcg_init()
15290 offsetof(CPUMIPSState, active_fpu.fcr0), in mips_tcg_init()
15293 offsetof(CPUMIPSState, active_fpu.fcr31), in mips_tcg_init()
/openbmc/qemu/target/mips/
H A Dgdbstub.c36 return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31); in mips_cpu_gdb_read_register()
38 return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0); in mips_cpu_gdb_read_register()
42 env->active_fpu.fpr[n - 38].d); in mips_cpu_gdb_read_register()
45 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]); in mips_cpu_gdb_read_register()
92 env->active_fpu.fcr31 = (tmp & env->active_fpu.fcr31_rw_bitmask) | in mips_cpu_gdb_write_register()
93 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask)); in mips_cpu_gdb_write_register()
101 env->active_fpu.fpr[n - 38].d = tmp; in mips_cpu_gdb_write_register()
103 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; in mips_cpu_gdb_write_register()
H A Dfpu_helper.h18 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], in restore_rounding_mode()
19 &env->active_fpu.fp_status); in restore_rounding_mode()
24 set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0, in restore_flush_mode()
25 &env->active_fpu.fp_status); in restore_flush_mode()
30 bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); in restore_snan_bit_mode()
36 set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); in restore_snan_bit_mode()
37 set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); in restore_snan_bit_mode()
66 &env->active_fpu.fp_status); in fp_reset()
H A Dcpu.c73 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, in fpu_dump_state()
74 get_float_exception_flags(&env->active_fpu.fp_status)); in fpu_dump_state()
77 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); in fpu_dump_state()
248 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; in mips_cpu_reset_hold()
249 env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; in mips_cpu_reset_hold()
250 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; in mips_cpu_reset_hold()
381 (env->active_fpu.fcr0 & (1 << FCR0_F64))) { in mips_cpu_reset_hold()
H A Dkvm.c599 &env->active_fpu.fcr0); in kvm_mips_put_fpu_registers()
606 &env->active_fpu.fcr31); in kvm_mips_put_fpu_registers()
621 &env->active_fpu.fpr[i].d); in kvm_mips_put_fpu_registers()
624 &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); in kvm_mips_put_fpu_registers()
656 env->active_fpu.fpr[i].wr.d); in kvm_mips_put_fpu_registers()
677 &env->active_fpu.fcr0); in kvm_mips_get_fpu_registers()
683 &env->active_fpu.fcr31); in kvm_mips_get_fpu_registers()
700 &env->active_fpu.fpr[i].d); in kvm_mips_get_fpu_registers()
703 &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); in kvm_mips_get_fpu_registers()
735 env->active_fpu.fpr[i].wr.d); in kvm_mips_get_fpu_registers()
H A Dinternal.h383 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { in compute_hflags()
406 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { in compute_hflags()
H A Dcpu.h530 CPUMIPSFPUContext active_fpu; member
1324 return env->active_fpu.fcr0 & (1 << FCR0_3D); in ase_3d_available()
H A Dcpu-defs.c.inc1030 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
/openbmc/qemu/linux-user/mips/
H A Dcpu_loop.c170 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { in cpu_loop()
172 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) { in cpu_loop()
174 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_OVERFLOW) { in cpu_loop()
176 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_UNDERFLOW) { in cpu_loop()
178 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INEXACT) { in cpu_loop()
285 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { in target_cpu_copy_regs()
290 if ((env->active_fpu.fcr0 & (1 << FCR0_F64) in target_cpu_copy_regs()
308 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { in target_cpu_copy_regs()
309 if ((env->active_fpu.fcr31_rw_bitmask & in target_cpu_copy_regs()
315 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008); in target_cpu_copy_regs()
[all …]
H A Dtarget_prctl.h43 if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { in do_prctl_set_fp_mode()
47 if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64)) in do_prctl_set_fp_mode()
52 if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) { in do_prctl_set_fp_mode()
58 fpr_t *fpr = env->active_fpu.fpr; in do_prctl_set_fp_mode()
76 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { in do_prctl_set_fp_mode()
H A Dsignal.c135 __put_user(regs->active_fpu.fpr[i].d, &sc->sc_fpregs[i]); in setup_sigcontext()
166 __get_user(regs->active_fpu.fpr[i].d, &sc->sc_fpregs[i]); in restore_sigcontext()
/openbmc/qemu/target/mips/sysemu/
H A Dmachine.c232 VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,