Revision tags: v9.2.0, v9.1.2, v9.1.1, v9.1.0 |
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a9c17e9a |
| 05-Sep-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'misc-20230831' of https://github.com/philmd/qemu into staging
Misc patches queue
Build fixes: - Only define OS_OBJECT_USE_OBJC with gcc
Overall cleanups: - Do not declare function proto
Merge tag 'misc-20230831' of https://github.com/philmd/qemu into staging
Misc patches queue
Build fixes: - Only define OS_OBJECT_USE_OBJC with gcc
Overall cleanups: - Do not declare function prototypes using 'extern' keyword - Remove unmaintained HAX accelerator - Have FEWatchFunc handlers return G_SOURCE_CONTINUE/REMOVE instead of boolean - Avoid modifying QOM class internals from instance in pmbus_device - Avoid variable-length array in xhci_get_port_bandwidth - Remove unuseful kvmclock_create() stub - Style: permit inline loop variables - Various header cleanups - Various spelling fixes
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* tag 'misc-20230831' of https://github.com/philmd/qemu: (39 commits) build: Only define OS_OBJECT_USE_OBJC with gcc tests/tcg/aarch64: Rename bti-crt.inc.c -> bti-crt.c.inc ui: spelling fixes util: spelling fixes util/fifo8: Fix typo in fifo8_push_all() description hw/i386: Rename 'hw/kvm/clock.h' -> 'hw/i386/kvm/clock.h' hw/i386: Remove unuseful kvmclock_create() stub hw/usb/hcd-xhci: Avoid variable-length array in xhci_get_port_bandwidth() hw/usb: spelling fixes hw/sd: spelling fixes hw/mips: spelling fixes hw/display: spelling fixes hw/ide: spelling fixes hw/i2c: spelling fixes hw/i2c/pmbus_device: Fix modifying QOM class internals from instance hw/char/pl011: Replace magic values by register field definitions hw/char/pl011: Remove duplicated PL011_INT_[RT]X definitions hw/char/pl011: Display register name in trace events hw/char/pl011: Restrict MemoryRegionOps implementation access sizes hw/char: Have FEWatchFunc handlers return G_SOURCE_CONTINUE/REMOVE ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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907a2af1 |
| 28-Aug-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/helpers: Remove unnecessary 'exec/cpu_ldst.h' header
These files don't use the CPU ld/st API, remove the unnecessary "exec/cpu_ldst.h" header.
Reviewed-by: Richard Henderson <richard.henders
target/helpers: Remove unnecessary 'exec/cpu_ldst.h' header
These files don't use the CPU ld/st API, remove the unnecessary "exec/cpu_ldst.h" header.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230828221314.18435-7-philmd@linaro.org>
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Revision tags: v8.0.0, v7.2.0, v7.0.0, v6.2.0, v6.1.0 |
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e93d8bcf |
| 03-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd/tags/mips-20210502' into staging
MIPS patches queue
- Fix CACHEE opcode - Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes - Remove isa_get_ir
Merge remote-tracking branch 'remotes/philmd/tags/mips-20210502' into staging
MIPS patches queue
- Fix CACHEE opcode - Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes - Remove isa_get_irq() call in PIIX4 south bridge - Add various missing fields to the MIPS CPU migration vmstate - Lot of code moved around to allow TCG or KVM only builds - Restrict non-virtualized machines to TCG - Add KVM mips64el cross-build jobs to gitlab-ci
# gpg: Signature made Sun 02 May 2021 15:56:51 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/mips-20210502: (36 commits) gitlab-ci: Add KVM mips64el cross-build jobs hw/mips: Restrict non-virtualized machines to TCG target/mips: Move TCG source files under tcg/ sub directory target/mips: Move CP0 helpers to sysemu/cp0.c target/mips: Move exception management code to exception.c target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c target/mips: Move helper_cache() to tcg/sysemu/special_helper.c target/mips: Move Special opcodes to tcg/sysemu/special_helper.c target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope target/mips: Move tlb_helper.c to tcg/sysemu/ target/mips: Restrict mmu_init() to TCG target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG target/mips: Move physical addressing code to sysemu/physaddr.c target/mips: Move sysemu specific files under sysemu/ subfolder target/mips: Move cpu_signal_handler definition around target/mips: Add simple user-mode mips_cpu_tlb_fill() target/mips: Add simple user-mode mips_cpu_do_interrupt() target/mips: Introduce tcg-internal.h for TCG specific declarations meson: Introduce meson_user_arch source set for arch-specific user-mode ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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a2b0a27d |
| 13-Apr-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Move TCG source files under tcg/ sub directory
To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery.
The following prototypes: - mip
target/mips: Move TCG source files under tcg/ sub directory
To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery.
The following prototypes: - mips_tcg_init() - mips_cpu_do_unaligned_access() - mips_cpu_do_transaction_failed() can now be restricted to the "tcg-internal.h" header.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-29-f4bug@amsat.org>
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