Revision tags: v9.2.0, v9.1.2, v9.1.1, v9.1.0 |
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8f6330a8 |
| 06-Mar-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging
maintainer updates (tests, gdbstub, plugins):
- expand QOS_PATH_MAX_ELEMENT_SIZE to avoid LTO issues
Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging
maintainer updates (tests, gdbstub, plugins):
- expand QOS_PATH_MAX_ELEMENT_SIZE to avoid LTO issues - support fork-follow-mode in gdbstub - new thread-safe scoreboard API for TCG plugins - suppress showing opcodes in plugin disassembly
# -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmXoY7oACgkQ+9DbCVqe # KkTdTwf8D8nUB+Ee6LuglW36vtd1ETdMfUmfRis7RIBsXZZ0Tg4+8LyfKkNi1vCL # UMdWQTkSW79RfXr21QEtETokwLZ0CWQMdxDAWfOiz4S+uDgQyBE+lwUsy0mHBmd7 # +J4SQb3adoZ+//9KMJhRU1wL9j3ygpEoKHVJonDObU6K5XuhE18JuBE44q7FqkWl # 0VhoLDgNxrf2PqT+LLP/O3MFLDXPVKbzrZYQF0IoqBTlcqShCoaykhSwiwCZ4Sqq # NO9hVwZIOFOcOF4F6ZqRXaZrwERldoBwG+BeIx1ah20vKFVT12y02dQqdP/oKwe+ # /PXFXDdzs4yMOghb4Go6SiKlKT5g4A== # =s1lF # -----END PGP SIGNATURE----- # gpg: Signature made Wed 06 Mar 2024 12:38:18 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu: (29 commits) target/riscv: honour show_opcodes when disassembling target/loongarch: honour show_opcodes when disassembling disas/hppa: honour show_opcodes disas: introduce show_opcodes plugins: cleanup codepath for previous inline operation plugins: remove non per_vcpu inline operation from API contrib/plugins/howvec: migrate to new per_vcpu API contrib/plugins/hotblocks: migrate to new per_vcpu API tests/plugin/bb: migrate to new per_vcpu API tests/plugin/insn: migrate to new per_vcpu API tests/plugin/mem: migrate to new per_vcpu API tests/plugin: add test plugin for inline operations plugins: add inline operation per vcpu plugins: implement inline operation relative to cpu_index plugins: define qemu_plugin_u64 plugins: scoreboard API tests/tcg: Add two follow-fork-mode tests gdbstub: Implement follow-fork-mode child gdbstub: Introduce gdb_handle_detach_user() gdbstub: Introduce gdb_handle_set_thread_user() ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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e4e5cb4a |
| 05-Mar-2024 |
Ilya Leoshkevich <iii@linux.ibm.com> |
{linux,bsd}-user: Introduce get_task_state()
A CPU's TaskState is stored in the CPUState's void *opaque field, accessing which is somewhat awkward due to having to use a cast. Introduce a wrapper an
{linux,bsd}-user: Introduce get_task_state()
A CPU's TaskState is stored in the CPUState's void *opaque field, accessing which is somewhat awkward due to having to use a cast. Introduce a wrapper and use it everywhere.
Suggested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240219141628.246823-3-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-4-alex.bennee@linaro.org>
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0d239e51 |
| 19-Oct-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-lu-20231018' of https://gitlab.com/rth7680/qemu into staging
linux-user/mips: fix abort on integer overflow linux-user/sh4: Fix crashes on signal delivery linux-user/loongarch: Enabl
Merge tag 'pull-lu-20231018' of https://gitlab.com/rth7680/qemu into staging
linux-user/mips: fix abort on integer overflow linux-user/sh4: Fix crashes on signal delivery linux-user/loongarch: Enable LSX/LASX in HWCAP linux-user: Fixes for zero_bss linux-user: Propagate failure in mmap_reserve_or_unmap back to target_munmap linux-user: Detect and report host crashes linux-user: Remap guest SIGABRT
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmUwapYdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV92UAf/RSsFWwCBAqt1WKIK # 7/7F8AF7WW1Hhjy3bHLjNnzgsDeWYfdIVxMGfF9IYKrYMeEqFeBeQ+vcOe9LTAvW # fEZkA//V+LosiYCwtVGBXyCbeXYxoONMp/taRv6lVHoqVU7aSlbXsYqwePcUtPWq # r/V+Ru5vssqMueBdE9+E53JPewGPVw8xQE+xGgd1TZIeHWgegZHBzKWVap/3noey # dKjTig3yxXXg1gQJLCRw+a6bl8oCl4vEluGsLzh5P8aV1imjvFPXkR2w1vQOC3ws # 8DmyMcPEcsY4D2WLeTAGMheURLRzs5141nT0fQCOB4yzO/I8zYFIG12xCxgWoQkg # kW9XZw== # =5oFh # -----END PGP SIGNATURE----- # gpg: Signature made Wed 18 Oct 2023 16:30:30 PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-lu-20231018' of https://gitlab.com/rth7680/qemu: linux-user: Remap guest SIGABRT linux-user: Detect and report host SIGILL, SIGFPE, SIGTRAP linux-user: Split out host_sig{segv,bus}_handler linux-user: Simplify signal_init linux-user: Map unsupported signals to an out-of-bounds value linux-user: Only register handlers for core_dump_signal by default linux-user: Detect and report host crashes linux-user: Exit not abort in die_with_backtrace linux-user: Split out die_with_signal linux-user: Propagate failure in mmap_reserve_or_unmap back to target_munmap linux-user/elfload: Enable LSX/LASX in HWCAP for LoongArch linux-user/sh4: Fix crashes on signal delivery linux-user/mips: fix abort on integer overflow linux-user: Fixes for zero_bss
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
6fad9b4b |
| 28-Sep-2023 |
Mikulas Patocka <mpatocka@redhat.com> |
linux-user/mips: fix abort on integer overflow
QEMU mips userspace emulation crashes with "qemu: unhandled CPU exception 0x15 - aborting" when one of the integer arithmetic instructions detects an o
linux-user/mips: fix abort on integer overflow
QEMU mips userspace emulation crashes with "qemu: unhandled CPU exception 0x15 - aborting" when one of the integer arithmetic instructions detects an overflow.
This patch fixes it so that it delivers SIGFPE with FPE_INTOVF instead.
Cc: qemu-stable@nongnu.org Signed-off-by: Mikulas Patocka <mpatocka@redhat.com> Message-Id: <3ef979a8-3ee1-eb2d-71f7-d788ff88dd11@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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19200a0e |
| 17-May-2023 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'linux-user-for-8.1-pull-request' of https://github.com/vivier/qemu into staging
linux-user pull request 20230512-v4
add open_tree(), move_mount() add /proc/cpuinfo for riscv fixes and cl
Merge tag 'linux-user-for-8.1-pull-request' of https://github.com/vivier/qemu into staging
linux-user pull request 20230512-v4
add open_tree(), move_mount() add /proc/cpuinfo for riscv fixes and cleanup
# -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmRkiZISHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L748FdIP/RC1JaCftkP7ajAstNbZLMLegMxjUYHV # TrdhsMOsm804ZmLgTqqfS3bJ080mIHup0xUnHBckcEtUcwaz54cJ1BAR2WlM3/8A # t3fHMt3PDkh3OPd/3AnmpLE8XRh7yBztirPYfZc6SKqnFzT0TZrwBoQnwprEnZ5r # c0gbrgLZLunZhrWU1BbQmuIufW1qDoQo4PzwnyZeux1fHA1/v/dx3wgSLpv3V4k6 # x0Kj8TvtMUU4/io2RqYF4jKopfhwsh0jnr9rlOmydOExalKq1VbRptJI2UC4KVOY # MZuApF1EaZfrW+v/WSlvmzaZ/zRzP1L0X3Xh0wB4J9Rj3057/elXr6bi+R+rM46p # xGTcti9ahWKP2J4/xrazRw2lfPsLcw/YbqVGG79AX1xLJPCiWq6lamzc/g3ptFnx # F/RRETe65z7apzF/nzU7SDOsMdN5p4/fMb1SysLuAov5OepNVjNVWyiTgqOHB5uC # ye+lOYkkvk+qRdMbls/fIcjDQ3C4AjoBWj4QlgRc0/Qf6ac4TkVjzPa70Y6eyzzS # LEV9D4fXD8EZgYWENNGmbbKPNbtfqc9uR6gXdgkEsKDx/rf5IMf1d6r1C99dhB3A # nbu0JpFKKY2lhD2oGVPDE3UQMW9DXXhZpDApUBsLNiEwfuoXZee+apH+6jc8tbn6 # r+8LFB1mM9os # =NfIV # -----END PGP SIGNATURE----- # gpg: Signature made Wed 17 May 2023 01:00:18 AM PDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [undefined] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [undefined] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* tag 'linux-user-for-8.1-pull-request' of https://github.com/vivier/qemu: linux-user: fix getgroups/setgroups allocations linux-user: Fix mips fp64 executables loading linux-user: Don't require PROT_READ for mincore linux-user: Add new flag VERIFY_NONE linux-user/main: Use list_cpus() instead of cpu_list() linux-user: Add open_tree() syscall linux-user: Add move_mount() syscall linux-user: report ENOTTY for unknown ioctls linux-user: Emulate /proc/cpuinfo output for riscv
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v8.0.0 |
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a0f8d270 |
| 04-Apr-2023 |
Daniil Kovalev <dkovalev@compiler-toolchain-for.me> |
linux-user: Fix mips fp64 executables loading
If a program requires fr1, we should set the FR bit of CP0 control status register and add F64 hardware flag. The corresponding `else if` branch stateme
linux-user: Fix mips fp64 executables loading
If a program requires fr1, we should set the FR bit of CP0 control status register and add F64 hardware flag. The corresponding `else if` branch statement is copied from the linux kernel sources (see `arch_check_elf` function in linux/arch/mips/kernel/elf.c).
Signed-off-by: Daniil Kovalev <dkovalev@compiler-toolchain-for.me> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230404052153.16617-1-dkovalev@compiler-toolchain-for.me> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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Revision tags: v7.2.0 |
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1be5a765 |
| 19-Apr-2022 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* Add cpu0-id to query-sev-capabilities * whpx support for breakpoints and stepping * initial support for Hyper-V Synthetic D
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* Add cpu0-id to query-sev-capabilities * whpx support for breakpoints and stepping * initial support for Hyper-V Synthetic Debugging * use monotonic clock for QemuCond and QemuSemaphore * Remove qemu-common.h include from most units and lots of other clenaups * do not include headers for all virtio devices in virtio-ccw.h
# -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmJXCQAUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNT6wf+NHDJUEdDiwaVGVTGXgHuiaycsymi # FpNPiw/+XxSGN5xF3fkUGgqaDrcwIYwVfnXlghKSz8kp1cP3cjxa5CzNMLGTp5je # N6BxFbD7yC6dhagGm3mj32jlsptv3M38OHqKc3t+RaUAotP5RF2VdCyfUBLG6vU0 # aMzvMfMtB5aG0D8Fr5EV63t1JMTceFU0YxsG73UCFs2Yx4Z0cGBbNxMbHweRhd1q # tPeVDS46MFPM3/2cGGHpeeqxkoCTU7A9j1VuNQI3k+Kg+6W5YVxiK/UP7bw77E/a # yAHsmIVTNro8ajMBch73weuHtGtdfFLvCKc6QX6aVjzK4dF1voQ01E7gPQ== # =rMle # -----END PGP SIGNATURE----- # gpg: Signature made Wed 13 Apr 2022 10:31:44 AM PDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (53 commits) target/i386: Remove unused XMMReg, YMMReg types and CPUState fields target/i386: do not access beyond the low 128 bits of SSE registers virtio-ccw: do not include headers for all virtio devices virtio-ccw: move device type declarations to .c files virtio-ccw: move vhost_ccw_scsi to a separate file s390x: follow qdev tree to detect SCSI device on a CCW bus hw: hyperv: Initial commit for Synthetic Debugging device hyperv: Add support to process syndbg commands hyperv: Add definitions for syndbg hyperv: SControl is optional to enable SynIc thread-posix: optimize qemu_sem_timedwait with zero timeout thread-posix: implement Semaphore with QemuCond and QemuMutex thread-posix: use monotonic clock for QemuCond and QemuSemaphore thread-posix: remove the posix semaphore support whpx: Added support for breakpoints and stepping build-sys: simplify AF_VSOCK check build-sys: drop ntddscsi.h check Remove qemu-common.h include from most units qga: remove explicit environ argument from exec/spawn Move fcntl_setfl() to oslib-posix ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.0.0 |
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0f9668e0 |
| 23-Mar-2022 |
Marc-André Lureau <marcandre.lureau@redhat.com> |
Remove qemu-common.h include from most units
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo B
Remove qemu-common.h include from most units
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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91f5f7a5 |
| 12-Jan-2022 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request' into staging
linux-user pull request 20220111 siginfo_t cleanup more prtctl() update target_struct.h cleanu
Merge remote-tracking branch 'remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request' into staging
linux-user pull request 20220111 siginfo_t cleanup more prtctl() update target_struct.h cleanup
# gpg: Signature made Tue 11 Jan 2022 19:52:20 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request: (30 commits) linux-user: Implement capability prctls linux-user: Implement PR_SET_PDEATHSIG linux-user: Map signal number in PR_GET_PDEATHSIG linux-user: Do not special-case NULL for PR_GET_PDEATHSIG linux-user: Move target_struct.h generic definitions to generic/ linux-user/arm: Move target_oabi_flock64 out of target_structs.h linux-user/xtensa: Use force_sig_fault linux-user/sparc: Use force_sig_fault linux-user/sh4: Use force_sig_fault linux-user/s390x: Use force_sig_fault linux-user/riscv: Use force_sig_fault linux-user/ppc: Use force_sig_fault linux-user/openrisc: Use force_sig_fault target/mips: Extract trap code into env->error_code target/mips: Extract break code into env->error_code linux-user/mips: Use force_sig_fault linux-user/mips: Improve do_break linux-user/microblaze: Fix SIGFPE si_codes linux-user/microblaze: Use force_sig_fault linux-user/m68k: Use force_sig_fault ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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0a3336f6 |
| 07-Jan-2022 |
Richard Henderson <richard.henderson@linaro.org> |
target/mips: Extract trap code into env->error_code
Simplify cpu_loop by doing all of the decode in translate.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson
target/mips: Extract trap code into env->error_code
Simplify cpu_loop by doing all of the decode in translate.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-18-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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6f3533dd |
| 07-Jan-2022 |
Richard Henderson <richard.henderson@linaro.org> |
target/mips: Extract break code into env->error_code
Simplify cpu_loop by doing all of the decode in translate.
This fixes a bug in that cpu_loop was not handling the different layout of the R6 ver
target/mips: Extract break code into env->error_code
Simplify cpu_loop by doing all of the decode in translate.
This fixes a bug in that cpu_loop was not handling the different layout of the R6 version of break16. This fixes a bug in that cpu_loop extracted the wrong bits for the mips16e break16 instruction.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-17-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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73c0aa6a |
| 07-Jan-2022 |
Richard Henderson <richard.henderson@linaro.org> |
linux-user/mips: Use force_sig_fault
Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP and SIGFPE; use force_sig (SI_KERNEL)
linux-user/mips: Use force_sig_fault
Use the new function instead of setting up a target_siginfo_t and calling queue_signal. Fill in the missing PC for SIGTRAP and SIGFPE; use force_sig (SI_KERNEL) for EXCP_DSPDIS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-16-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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bf19bdb8 |
| 07-Jan-2022 |
Richard Henderson <richard.henderson@linaro.org> |
linux-user/mips: Improve do_break
Rename to do_tr_or_bp, as per the kernel function. Add a 'trap' argument, akin to the kernel's si_code, but clearer. The return value is always 0, so change the ret
linux-user/mips: Improve do_break
Rename to do_tr_or_bp, as per the kernel function. Add a 'trap' argument, akin to the kernel's si_code, but clearer. The return value is always 0, so change the return value to void. Use force_sig and force_sig_fault.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-15-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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2bf40d08 |
| 20-Dec-2021 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-user-20211220' of https://gitlab.com/rth7680/qemu into staging
Move errno processing from safe_syscall() to safe_syscall_base(). Move safe_syscall() from linux-user to common-user. A
Merge tag 'pull-user-20211220' of https://gitlab.com/rth7680/qemu into staging
Move errno processing from safe_syscall() to safe_syscall_base(). Move safe_syscall() from linux-user to common-user. Add FreeBSD support to safe_syscall_base(). Tidy top-level meson.build wrt {bsd,linux}-user.
# gpg: Signature made Mon 20 Dec 2021 11:46:11 AM PST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-user-20211220' of https://gitlab.com/rth7680/qemu: meson: Move bsd_user_ss to bsd-user/ meson: Move linux_user_ss to linux-user/ linux-user: Move thunk.c from top-level common-user: Adjust system call return on FreeBSD common-user: Move safe-syscall.* from linux-user bsd-user: Create special-errno.h linux-user: Create special-errno.h linux-user: Rename TARGET_QEMU_ESIGRETURN to QEMU_ESIGRETURN bsd-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS linux-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS linux-user: Remove HAVE_SAFE_SYSCALL and hostdep.h linux-user/host/sparc64: Add safe-syscall.inc.S linux-user/host/mips: Add safe-syscall.inc.S linux-user: Move syscall error detection into safe_syscall_base linux-user: Untabify all safe-syscall.inc.S
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v6.2.0 |
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57a0c938 |
| 17-Nov-2021 |
Richard Henderson <richard.henderson@linaro.org> |
linux-user: Rename TARGET_QEMU_ESIGRETURN to QEMU_ESIGRETURN
This value is fully internal to qemu, and so is not a TARGET define.
Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mat
linux-user: Rename TARGET_QEMU_ESIGRETURN to QEMU_ESIGRETURN
This value is fully internal to qemu, and so is not a TARGET define.
Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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af254a27 |
| 22-Nov-2021 |
Richard Henderson <richard.henderson@linaro.org> |
linux-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS
This value is fully internal to qemu, and so is not a TARGET define. We use this as an extra marker for both host and target errno.
Reviewe
linux-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS
This value is fully internal to qemu, and so is not a TARGET define. We use this as an extra marker for both host and target errno.
Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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102f39b3 |
| 02-Nov-2021 |
Richard Henderson <richard.henderson@linaro.org> |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211102' into staging
- Split out host signal handing from accel/tcg/user-exec.c to linux-user/host/arch/host-signal.h - Replace TCGCPUOps.
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211102' into staging
- Split out host signal handing from accel/tcg/user-exec.c to linux-user/host/arch/host-signal.h - Replace TCGCPUOps.tlb_fill with TCGCPUOps.record_sigsegv for user-only - Add TCGCPUOps.record_sigbus for user-only - Remove a lot of target-specific cpu_loop handling for signals, now accomplished with generic code.
# gpg: Signature made Tue 02 Nov 2021 07:06:14 AM EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* remotes/rth/tags/pull-tcg-20211102: (60 commits) linux-user: Handle BUS_ADRALN in host_signal_handler tcg: Add helper_unaligned_{ld,st} for user-only sigbus accel/tcg: Report unaligned load/store for user-only accel/tcg: Report unaligned atomics for user-only target/sparc: Set fault address in sparc_cpu_do_unaligned_access target/sparc: Split out build_sfsr target/sparc: Remove DEBUG_UNALIGNED target/sh4: Set fault address in superh_cpu_do_unaligned_access target/s390x: Implement s390x_cpu_record_sigbus linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu target/ppc: Set fault address in ppc_cpu_do_unaligned_access target/ppc: Move SPR_DSISR setting to powerpc_excp target/microblaze: Do not set MO_ALIGN for user-only linux-user/hppa: Remove EXCP_UNALIGN handling target/arm: Implement arm_cpu_record_sigbus target/alpha: Implement alpha_cpu_record_sigbus linux-user: Add cpu_loop_exit_sigbus hw/core: Add TCGCPUOps.record_sigbus accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
52d4899b |
| 14-Sep-2021 |
Richard Henderson <richard.henderson@linaro.org> |
target/mips: Make mips_cpu_tlb_fill sysemu only
The fallback code in cpu_loop_exit_sigsegv is sufficient for mips linux-user.
This means we can remove tcg/user/tlb_helper.c entirely. Remove the cod
target/mips: Make mips_cpu_tlb_fill sysemu only
The fallback code in cpu_loop_exit_sigsegv is sufficient for mips linux-user.
This means we can remove tcg/user/tlb_helper.c entirely. Remove the code from cpu_loop that raised SIGSEGV.
Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
c99e34e5 |
| 16-Sep-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-6.2-pull-request' into staging
Pull request linux-user 20210916
Code cleanup
# gpg: Signature made Thu 16 Sep 2021 16:11:58 BST #
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-6.2-pull-request' into staging
Pull request linux-user 20210916
Code cleanup
# gpg: Signature made Thu 16 Sep 2021 16:11:58 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier2/tags/linux-user-for-6.2-pull-request: linux-user: Check lock_user result for ip_mreq_source sockopts linux-user: Drop unneeded includes from qemu.h linux-user: Don't include gdbstub.h in qemu.h linux-user: Split linux-user internals out of qemu.h linux-user: Split safe-syscall macro into its own header linux-user: Split mmap prototypes into user-mmap.h linux-user: Split loader-related prototypes into loader.h linux-user: Split signal-related prototypes into signal-common.h linux-user: Split strace prototypes into strace.h linux-user: Fix coding style nits in qemu.h
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
3b249d26 |
| 08-Sep-2021 |
Peter Maydell <peter.maydell@linaro.org> |
linux-user: Split linux-user internals out of qemu.h
qemu.h is included in various non-linux-user files (which mostly want the TaskState struct and the functions for doing usermode access to guest a
linux-user: Split linux-user internals out of qemu.h
qemu.h is included in various non-linux-user files (which mostly want the TaskState struct and the functions for doing usermode access to guest addresses like lock_user(), unlock_user(), get_user*(), etc).
Split out the parts that are only used in linux-user itself into a new user-internals.h. This leaves qemu.h with basically three things: * the definition of the TaskState struct * the user-access functions and macros * do_brk() all of which are needed by code outside linux-user that includes qemu.h.
The addition of all the extra #include lines was done with sed -i '/include.*qemu\.h/a #include "user-internals.h"' $(git grep -l 'include.*qemu\.h' linux-user) (and then undoing the change to fpa11.h).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210908154405.15417-8-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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2113aed6 |
| 08-Sep-2021 |
Peter Maydell <peter.maydell@linaro.org> |
linux-user: Split signal-related prototypes into signal-common.h
Split the signal related prototypes into the existing header file signal-common.h, and include it in those places that now require it
linux-user: Split signal-related prototypes into signal-common.h
Split the signal related prototypes into the existing header file signal-common.h, and include it in those places that now require it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210908154405.15417-4-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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Revision tags: v6.1.0 |
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#
256af05f |
| 15-Jan-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20210114' into staging
MIPS patches queue
- Simplify CPU/ISA definitions - Various maintenance code movements in translate.c - Convert
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20210114' into staging
MIPS patches queue
- Simplify CPU/ISA definitions - Various maintenance code movements in translate.c - Convert part of the MSA ASE instructions to decodetree - Convert some instructions removed from Release 6 to decodetree - Remove deprecated 'fulong2e' machine alias
# gpg: Signature made Thu 14 Jan 2021 16:16:29 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/mips-20210114: (69 commits) docs/system: Remove deprecated 'fulong2e' machine alias target/mips: Remove vendor specific CPU definitions target/mips: Remove CPU_NANOMIPS32 definition target/mips: Remove CPU_R5900 definition target/mips: Convert Rel6 LL/SC opcodes to decodetree target/mips: Convert Rel6 LLD/SCD opcodes to decodetree target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree target/mips: Convert Rel6 COP1X opcode to decodetree target/mips: Convert Rel6 Special2 opcode to decodetree target/mips: Remove now unreachable LSA/DLSA opcodes code target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes target/mips: Extract LSA/DLSA translation generators target/mips: Use decode_ase_msa() generated from decodetree target/mips: Introduce decode tree bindings for MSA ASE target/mips: Pass TCGCond argument to MSA gen_check_zero_element() target/mips: Extract MSA translation routines ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v5.2.0 |
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#
81ddae7c |
| 14-Nov-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Extract FPU helpers to 'fpu_helper.h'
Extract FPU specific helpers from "internal.h" to "fpu_helper.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Phi
target/mips: Extract FPU helpers to 'fpu_helper.h'
Extract FPU specific helpers from "internal.h" to "fpu_helper.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201120210844.2625602-2-f4bug@amsat.org>
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2e211e0a |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
The MIPS ISA release 6 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the definition with the next available bi
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
The MIPS ISA release 6 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-16-f4bug@amsat.org>
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#
7a47bae5 |
| 16-Dec-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
The MIPS ISA release 2 is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe M
target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
The MIPS ISA release 2 is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-13-f4bug@amsat.org>
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