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Searched refs:CCSR (Results 1 – 25 of 32) sorted by relevance

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/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmcm.txt8 The LAW node represents the region of CCSR space where local access
10 of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some
24 physical address offset and length of the CCSR space
37 The MPX LAW node represents the region of CCSR space where MCM config
39 of CCSR space.
53 physical address offset and length of the CCSR space
H A Decm.txt8 The LAW node represents the region of CCSR space where local access
10 of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some
24 physical address offset and length of the CCSR space
37 The E500 LAW node represents the region of CCSR space where ECM config
39 of CCSR space.
53 physical address offset and length of the CCSR space
H A Dinterlaken-lac.txt43 those LAC CCSR registers not protected in partitioned
61 Definition: Points to the non-protected LAC CCSR mapped register space
H A Dmsi-pic.txt83 Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
H A Dpamu.txt32 A standard property. It represents the CCSR registers of
H A Dmpic.txt27 CCSR address space.
/openbmc/linux/drivers/clk/pxa/
H A Dclk-pxa27x.c105 unsigned long ccsr = readl(clk_regs + CCSR); in pxa27x_is_ppll_disabled()
207 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_cpll_get_rate()
252 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_lcd_base_get_rate()
274 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_lcd_base_get_parent()
303 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_core_get_parent()
340 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_run_get_rate()
363 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_system_bus_get_rate()
380 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_system_bus_get_parent()
397 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_memory_get_rate()
416 unsigned long ccsr = readl(clk_regs + CCSR); in clk_pxa27x_memory_get_parent()
H A Dclk-pxa2xx.h6 #define CCSR (0x000C) /* Core Clock Status Register */ macro
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/
H A Dbman.txt16 binding covers the CCSR space programming model
29 Definition: Registers region within the CCSR address space
112 The example below shows a (P4080) BMan CCSR-space node
H A Dqman.txt18 CCSR space programming model
31 Definition: Registers region within the CCSR address space
145 The example below shows a (P4080) QMan CCSR-space node
/openbmc/qemu/hw/ppc/
H A De500-ccsr.h16 OBJECT_DECLARE_SIMPLE_TYPE(PPCE500CCSRState, CCSR)
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.lsch3160 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
161 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
193 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
194 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
228 2) CCSR 4-byte write to 0x01e00404, data=0x00000000
229 3) CCSR 4-byte write to 0x01e00400, data=0x1800a000
/openbmc/u-boot/board/freescale/ls2080a/
H A DREADME8 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa2xx-regs.h135 #define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */ macro
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME119 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
120 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
/openbmc/u-boot/board/freescale/mpc8641hpcn/
H A DREADME125 0xffe0_0000 0xffef_ffff CCSR 1M
146 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A DREADME110 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
111 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
/openbmc/u-boot/doc/
H A DREADME.mpc83xxads38 0xe000_0000 0xe00f_ffff CCSR 1M
H A DREADME.mpc85xxcds39 0xe000_0000 0xe00f_ffff CCSR 1M
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx6sl.c18 #define CCSR 0xc macro
129 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { in imx6sl_get_arm_divider_for_wait()
/openbmc/u-boot/board/freescale/c29xpcie/
H A DREADME39 0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR
/openbmc/u-boot/board/freescale/ls2080ardb/
H A DREADME58 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
/openbmc/u-boot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PB49 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
/openbmc/u-boot/board/freescale/ls2080aqds/
H A DREADME60 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
/openbmc/qemu/hw/pci-host/
H A Dppce500.c421 PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(), in e500_pcihost_bridge_realize()

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