103f5c550SwdenkMotorola MPC85xxCDS boards 203f5c550Swdenk-------------------------- 303f5c550Swdenk 403f5c550SwdenkThe CDS family of boards consists of a PCI backplane called the 503f5c550Swdenk"Arcadia", a PCI-form-factor carrier card that plugs into a PCI slot, 603f5c550Swdenkand a CPU daughter card that bolts onto the daughter card. 703f5c550Swdenk 803f5c550SwdenkMuch of the content of the README.mpc85xxads for the 85xx ADS boards 903f5c550Swdenkapplies to the 85xx CDS boards as well. In particular the toolchain, 1003f5c550Swdenkthe switch nomenclature, and the basis for the memory map. There are 1103f5c550Swdenksome differences, though. 1203f5c550Swdenk 1303f5c550Swdenk 1403f5c550SwdenkBuilding U-Boot 1503f5c550Swdenk--------------- 1603f5c550Swdenk 1703f5c550SwdenkThe Binutils in current ELDK toolchain will not support MPC85xx 1803f5c550Swdenkchip. You need to use binutils-2.14.tar.bz2 (or newer) from 1903f5c550Swdenk http://ftp.gnu.org/gnu/binutils. 2003f5c550Swdenk 2103f5c550SwdenkThe 85xx CDS code base is known to compile using: 2203f5c550Swdenk gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a) 2303f5c550Swdenk 2403f5c550Swdenk 2503f5c550SwdenkMemory Map 2603f5c550Swdenk---------- 2703f5c550Swdenk 28*a187559eSBin MengThe memory map for U-Boot and linux has been extended w.r.t. the ADS 2903f5c550Swdenkplatform to allow for utilization of all 85xx CDS devices. The memory 3003f5c550Swdenkmap is setup for linux to operate properly. The linux source when 3103f5c550Swdenkconfigured for MPC85xx CDS has been updated to reflect the new memory 3203f5c550Swdenkmap. 3303f5c550Swdenk 3403f5c550SwdenkThe mapping is: 3503f5c550Swdenk 3603f5c550Swdenk 0x0000_0000 0x7fff_ffff DDR 2G 3703f5c550Swdenk 0x8000_0000 0x9fff_ffff PCI1 MEM 512M 3803f5c550Swdenk 0xa000_0000 0xbfff_ffff PCI2 MEM 512M 3903f5c550Swdenk 0xe000_0000 0xe00f_ffff CCSR 1M 4003f5c550Swdenk 0xe200_0000 0xe2ff_ffff PCI1 IO 16M 4103f5c550Swdenk 0xe300_0000 0xe3ff_ffff PCI2 IO 16M 4203f5c550Swdenk 0xf000_0000 0xf7ff_ffff SDRAM 128M 4303f5c550Swdenk 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M 4403f5c550Swdenk 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M 4503f5c550Swdenk 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M 4603f5c550Swdenk 4703f5c550Swdenk (*) The system control registers (CADMUS) start at offset 0xfdb0_4000 4803f5c550Swdenk within the NVRAM/CADMUS region of memory. 4903f5c550Swdenk 5003f5c550Swdenk 5103f5c550SwdenkUsing Flash 5203f5c550Swdenk----------- 5303f5c550Swdenk 5403f5c550SwdenkThe CDS board has two flash banks, each 8MB in size (2^23 = 0x00800000). 5503f5c550SwdenkThere is a switch which allows the boot-bank to be selected. The switch 5603f5c550Swdenksettings for updating flash are given below. 5703f5c550Swdenk 58*a187559eSBin MengThe U-Boot commands for copying the boot-bank into the secondary bank are 5903f5c550Swdenkas follows: 6003f5c550Swdenk 6103f5c550Swdenk erase ff780000 ff7fffff 6203f5c550Swdenk cp.b fff80000 ff780000 80000 6303f5c550Swdenk 6403f5c550Swdenk 65*a187559eSBin MengU-Boot/kermit commands for downloading an image, then copying 6603f5c550Swdenkit into the secondary bank: 6703f5c550Swdenk 6803f5c550Swdenk loadb 6903f5c550Swdenk [Drop to kermit: 7003f5c550Swdenk ^\c 7103f5c550Swdenk send <u-boot-bin-image> 7203f5c550Swdenk c 7303f5c550Swdenk ] 7403f5c550Swdenk 7503f5c550Swdenk erase ff780000 ff7fffff 7603f5c550Swdenk cp.b $loadaddr ff780000 80000 7703f5c550Swdenk 7803f5c550Swdenk 79*a187559eSBin MengU-Boot commands for downloading an image via tftp and flashing 8003f5c550Swdenkit into the second bank: 8103f5c550Swdenk 8203f5c550Swdenk tftp 10000 <u-boot.bin.image> 8303f5c550Swdenk erase ff780000 ff7fffff 8403f5c550Swdenk cp.b 10000 ff780000 80000 8503f5c550Swdenk 8603f5c550Swdenk 8703f5c550SwdenkAfter copying the image into the second bank of flash, be sure to toggle 8803f5c550SwdenkSW2[2] on the carrier card before resetting the board in order to set the 8903f5c550Swdenksecondary bank as the boot-bank. 9003f5c550Swdenk 9103f5c550Swdenk 9203f5c550SwdenkCarrier Board Switches 9303f5c550Swdenk---------------------- 9403f5c550Swdenk 9503f5c550SwdenkAs a reminder, you should read the README.mpc85xxads too. 9603f5c550Swdenk 9703f5c550SwdenkMost switches on the carrier board should not be changed. The only 9803f5c550Swdenkuser-settable switches on the carrier board are used to configure 9903f5c550Swdenkthe flash banks and determining the PCI slot. 10003f5c550Swdenk 10103f5c550SwdenkThe first two bits of SW2 control how flash is used on the board: 10203f5c550Swdenk 10303f5c550Swdenk 12345678 10403f5c550Swdenk -------- 10503f5c550Swdenk SW2=00XXXXXX FLASH: Boot bank 1, bank 2 available. 10603f5c550Swdenk 01XXXXXX FLASH: Boot bank 2, bank 1 available (swapped). 10703f5c550Swdenk 10XXXXXX FLASH: Boot promjet, bank 1 available 10803f5c550Swdenk 11XXXXXX FLASH: Boot promjet, bank 2 available 10903f5c550Swdenk 11003f5c550SwdenkThe boot bank is always mapped to FF80_0000 and listed first by 11103f5c550Swdenkthe "flinfo" command. The secondary bank is always FF00_0000. 11203f5c550Swdenk 11303f5c550SwdenkWhen using PCI, linux needs to know to which slot the CDS carrier is 11403f5c550Swdenkconnected.. By convention, the user-specific bits of SW2 are used to 11503f5c550Swdenkconvey this information: 11603f5c550Swdenk 11703f5c550Swdenk 12345678 11803f5c550Swdenk -------- 11903f5c550Swdenk SW2=xxxxxx00 PCI SLOT INFORM: The CDS carrier is in slot0 of the Arcadia 12003f5c550Swdenk xxxxxx01 PCI SLOT INFORM: The CDS carrier is in slot1 of the Arcadia 12103f5c550Swdenk xxxxxx10 PCI SLOT INFORM: The CDS carrier is in slot2 of the Arcadia 12203f5c550Swdenk xxxxxx11 PCI SLOT INFORM: The CDS carrier is in slot3 of the Arcadia 12303f5c550Swdenk 12403f5c550SwdenkThese are cleverly, er, clearly silkscreened as Slot 1 through 4, 12503f5c550Swdenkrespectively, on the Arcadia near the support posts. 12603f5c550Swdenk 12703f5c550Swdenk 12803f5c550SwdenkThe default setting of all switches on the carrier board is: 12903f5c550Swdenk 13003f5c550Swdenk 12345678 13103f5c550Swdenk -------- 13203f5c550Swdenk SW1=01101100 13303f5c550Swdenk SW2=0x1111yy x=Flash bank, yy=PCI slot 13403f5c550Swdenk SW3=11101111 13503f5c550Swdenk SW4=10001000 13603f5c550Swdenk 13703f5c550Swdenk 138d9b94f28SJon Loeliger8555/41 CPU Card Switches 139d9b94f28SJon Loeliger------------------------- 14003f5c550Swdenk 14103f5c550SwdenkMost switches on the CPU Card should not be changed. However, the 14203f5c550Swdenkfrequency can be changed by setting SW3: 14303f5c550Swdenk 14403f5c550Swdenk 12345678 14503f5c550Swdenk -------- 14603f5c550Swdenk SW3=XX00XXXX == CORE:CCB 2:1 14703f5c550Swdenk XX01XXXX == CORE:CCB 5:2 14803f5c550Swdenk XX10XXXX == CORE:CCB 3:1 14903f5c550Swdenk XX11XXXX == CORE:CCB 7:2 15003f5c550Swdenk XXXX1000 == CCB:SYSCLK 8:1 15103f5c550Swdenk XXXX1010 == CCB:SYSCLK 10:1 15203f5c550Swdenk 15303f5c550SwdenkA safe default setting for all switches on the CPU board is: 15403f5c550Swdenk 15503f5c550Swdenk 12345678 15603f5c550Swdenk -------- 15703f5c550Swdenk SW1=10001111 15803f5c550Swdenk SW2=01000111 15903f5c550Swdenk SW3=00001000 16003f5c550Swdenk SW4=11111110 16103f5c550Swdenk 16203f5c550Swdenk 163d9b94f28SJon Loeliger8548 CPU Card Switches 164d9b94f28SJon Loeliger---------------------- 165d9b94f28SJon LoeligerAnd, just to be confusing, in this set of switches: 166d9b94f28SJon Loeliger 167d9b94f28SJon Loeliger ON = 1 168d9b94f28SJon Loeliger OFF = 0 169d9b94f28SJon Loeliger 170d9b94f28SJon LoeligerDefault 171d9b94f28SJon Loeliger SW1=11111101 172d9b94f28SJon Loeliger SW2=10011111 173d9b94f28SJon Loeliger SW3=11001000 (8X) (2:1) 174d9b94f28SJon Loeliger SW4=11110011 175d9b94f28SJon Loeliger 176d9b94f28SJon Loeliger SW3=X000XXXX == CORE:CCB 4:1 177d9b94f28SJon Loeliger X001XXXX == CORE:CCB 9:2 178d9b94f28SJon Loeliger X010XXXX == CORE:CCB 1:1 179d9b94f28SJon Loeliger X011XXXX == CORE:CCB 3:2 180d9b94f28SJon Loeliger X100XXXX == CORE:CCB 2:1 181d9b94f28SJon Loeliger X101XXXX == CORE:CCB 5:2 182d9b94f28SJon Loeliger X110XXXX == CORE:CCB 3:1 183d9b94f28SJon Loeliger X111XXXX == CORE:CCB 7:2 184d9b94f28SJon Loeliger XXXX0000 == CCB:SYSCLK 16:1 185d9b94f28SJon Loeliger XXXX0001 == RESERVED 186d9b94f28SJon Loeliger XXXX0010 == CCB:SYSCLK 2:1 187d9b94f28SJon Loeliger XXXX0011 == CCB:SYSCLK 3:1 188d9b94f28SJon Loeliger XXXX0100 == CCB:SYSCLK 4:1 189d9b94f28SJon Loeliger XXXX0101 == CCB:SYSCLK 5:1 190d9b94f28SJon Loeliger XXXX0110 == CCB:SYSCLK 6:1 191d9b94f28SJon Loeliger XXXX0111 == RESERVED 192d9b94f28SJon Loeliger XXXX1000 == CCB:SYSCLK 8:1 193d9b94f28SJon Loeliger XXXX1001 == CCB:SYSCLK 9:1 194d9b94f28SJon Loeliger XXXX1010 == CCB:SYSCLK 10:1 195d9b94f28SJon Loeliger XXXX1011 == RESERVED 196d9b94f28SJon Loeliger XXXX1100 == CCB:SYSCLK 12:1 197d9b94f28SJon Loeliger XXXX1101 == CCB:SYSCLK 20:1 198d9b94f28SJon Loeliger XXXX1110 == RESERVED 199d9b94f28SJon Loeliger XXXX1111 == RESERVED 200d9b94f28SJon Loeliger 201d9b94f28SJon Loeliger 20203f5c550SwdenkeDINK Info 20303f5c550Swdenk---------- 20403f5c550Swdenk 20503f5c550SwdenkOne bank of flash may contain an eDINK image. 20603f5c550Swdenk 20703f5c550SwdenkMemory Map: 20803f5c550Swdenk 20903f5c550Swdenk CCSRBAR @ 0xe0000000 21003f5c550Swdenk Flash Bank 1 @ 0xfe000000 21103f5c550Swdenk Flash Bank 2 @ 0xff000000 21203f5c550Swdenk Ram @ 0 21303f5c550Swdenk 214*a187559eSBin MengCommands for downloading a U-Boot image to memory from edink: 21503f5c550Swdenk 21603f5c550Swdenk env -c 21703f5c550Swdenk time -s 4/8/2004 4:30p 21803f5c550Swdenk dl -k -b -o 100000 21903f5c550Swdenk [Drop to kermit: 22003f5c550Swdenk ^\c 22103f5c550Swdenk transmit /binary <u-boot-bin-image> 22203f5c550Swdenk c 22303f5c550Swdenk ] 22403f5c550Swdenk 22503f5c550Swdenk fu -l 100000 fe780000 80000 226