1d524dac9SGrant Likely* Freescale MSI interrupt controller 2d524dac9SGrant Likely 3d524dac9SGrant LikelyRequired properties: 4*03daa99eSMinghuan Lian- compatible : compatible list, may contain one or two entries 5*03daa99eSMinghuan Lian The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, 6*03daa99eSMinghuan Lian etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or 7*03daa99eSMinghuan Lian "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic 8*03daa99eSMinghuan Lian version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is 9*03daa99eSMinghuan Lian provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3" 10*03daa99eSMinghuan Lian should be used. The first entry is optional; the second entry is 11*03daa99eSMinghuan Lian required. 126820feadSScott Wood 13da3b6c05SDiana CRACIUN- reg : It may contain one or two regions. The first region should contain 14da3b6c05SDiana CRACIUN the address and the length of the shared message interrupt register set. 15*03daa99eSMinghuan Lian The second region should contain the address of aliased MSIIR or MSIIR1 16*03daa99eSMinghuan Lian register for platforms that have such an alias, if using MSIIR1, the second 17*03daa99eSMinghuan Lian region must be added because different MSI group has different MSIIR1 offset. 186820feadSScott Wood 19d524dac9SGrant Likely- interrupts : each one of the interrupts here is one entry per 32 MSIs, 20d524dac9SGrant Likely and routed to the host interrupt controller. the interrupts should 216820feadSScott Wood be set as edge sensitive. If msi-available-ranges is present, only 226820feadSScott Wood the interrupts that correspond to available ranges shall be present. 236820feadSScott Wood 242bcd1c0cSTimur TabiOptional properties: 25*03daa99eSMinghuan Lian- msi-available-ranges: use <start count> style section to define which 26*03daa99eSMinghuan Lian msi interrupt can be used in the 256 msi interrupts. This property is 27*03daa99eSMinghuan Lian optional, without this, all the MSI interrupts can be used. 28*03daa99eSMinghuan Lian Each available range must begin and end on a multiple of 32 (i.e. 29*03daa99eSMinghuan Lian no splitting an individual MSI register or the associated PIC interrupt). 30*03daa99eSMinghuan Lian MPIC v4.3 does not support this property because the 32 interrupts of an 31*03daa99eSMinghuan Lian individual register are not continuous when using MSIIR1. 32*03daa99eSMinghuan Lian 332bcd1c0cSTimur Tabi- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register 342bcd1c0cSTimur Tabi is used for MSI messaging. The address of MSIIR in PCI address space is 352bcd1c0cSTimur Tabi the MSI message address. 362bcd1c0cSTimur Tabi 372bcd1c0cSTimur Tabi This property may be used in virtualized environments where the hypervisor 382bcd1c0cSTimur Tabi has created an alternate mapping for the MSIR block. See below for an 392bcd1c0cSTimur Tabi explanation. 402bcd1c0cSTimur Tabi 412bcd1c0cSTimur Tabi 42d524dac9SGrant LikelyExample: 43d524dac9SGrant Likely msi@41600 { 44d524dac9SGrant Likely compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; 45d524dac9SGrant Likely reg = <0x41600 0x80>; 46d524dac9SGrant Likely msi-available-ranges = <0 0x100>; 47d524dac9SGrant Likely interrupts = < 48d524dac9SGrant Likely 0xe0 0 49d524dac9SGrant Likely 0xe1 0 50d524dac9SGrant Likely 0xe2 0 51d524dac9SGrant Likely 0xe3 0 52d524dac9SGrant Likely 0xe4 0 53d524dac9SGrant Likely 0xe5 0 54d524dac9SGrant Likely 0xe6 0 55d524dac9SGrant Likely 0xe7 0>; 56d524dac9SGrant Likely interrupt-parent = <&mpic>; 57d524dac9SGrant Likely }; 582bcd1c0cSTimur Tabi 59*03daa99eSMinghuan Lian msi@41600 { 60*03daa99eSMinghuan Lian compatible = "fsl,mpic-msi-v4.3"; 61*03daa99eSMinghuan Lian reg = <0x41600 0x200 0x44148 4>; 62*03daa99eSMinghuan Lian interrupts = < 63*03daa99eSMinghuan Lian 0xe0 0 0 0 64*03daa99eSMinghuan Lian 0xe1 0 0 0 65*03daa99eSMinghuan Lian 0xe2 0 0 0 66*03daa99eSMinghuan Lian 0xe3 0 0 0 67*03daa99eSMinghuan Lian 0xe4 0 0 0 68*03daa99eSMinghuan Lian 0xe5 0 0 0 69*03daa99eSMinghuan Lian 0xe6 0 0 0 70*03daa99eSMinghuan Lian 0xe7 0 0 0 71*03daa99eSMinghuan Lian 0x100 0 0 0 72*03daa99eSMinghuan Lian 0x101 0 0 0 73*03daa99eSMinghuan Lian 0x102 0 0 0 74*03daa99eSMinghuan Lian 0x103 0 0 0 75*03daa99eSMinghuan Lian 0x104 0 0 0 76*03daa99eSMinghuan Lian 0x105 0 0 0 77*03daa99eSMinghuan Lian 0x106 0 0 0 78*03daa99eSMinghuan Lian 0x107 0 0 0>; 79*03daa99eSMinghuan Lian }; 80*03daa99eSMinghuan Lian 812bcd1c0cSTimur TabiThe Freescale hypervisor and msi-address-64 822bcd1c0cSTimur Tabi------------------------------------------- 832bcd1c0cSTimur TabiNormally, PCI devices have access to all of CCSR via an ATMU mapping. The 842bcd1c0cSTimur TabiFreescale MSI driver calculates the address of MSIIR (in the MSI register 852bcd1c0cSTimur Tabiblock) and sets that address as the MSI message address. 862bcd1c0cSTimur Tabi 872bcd1c0cSTimur TabiIn a virtualized environment, the hypervisor may need to create an IOMMU 882bcd1c0cSTimur Tabimapping for MSIIR. The Freescale ePAPR hypervisor has this requirement 892bcd1c0cSTimur Tabibecause of hardware limitations of the Peripheral Access Management Unit 902bcd1c0cSTimur Tabi(PAMU), which is currently the only IOMMU that the hypervisor supports. 912bcd1c0cSTimur TabiThe ATMU is programmed with the guest physical address, and the PAMU 922bcd1c0cSTimur Tabiintercepts transactions and reroutes them to the true physical address. 932bcd1c0cSTimur Tabi 942bcd1c0cSTimur TabiIn the PAMU, each PCI controller is given only one primary window. The 952bcd1c0cSTimur TabiPAMU restricts DMA operations so that they can only occur within a window. 962bcd1c0cSTimur TabiBecause PCI devices must be able to DMA to memory, the primary window must 972bcd1c0cSTimur Tabibe used to cover all of the guest's memory space. 982bcd1c0cSTimur Tabi 992bcd1c0cSTimur TabiPAMU primary windows can be divided into 256 subwindows, and each 1002bcd1c0cSTimur Tabisubwindow can have its own address mapping ("guest physical" to "true 1012bcd1c0cSTimur Tabiphysical"). However, each subwindow has to have the same alignment, which 1022bcd1c0cSTimur Tabimeans they cannot be located at just any address. Because of these 1032bcd1c0cSTimur Tabirestrictions, it is usually impossible to create a 4KB subwindow that 1042bcd1c0cSTimur Tabicovers MSIIR where it's normally located. 1052bcd1c0cSTimur Tabi 1062bcd1c0cSTimur TabiTherefore, the hypervisor has to create a subwindow inside the same 1072bcd1c0cSTimur Tabiprimary window used for memory, but mapped to the MSIR block (where MSIIR 1082bcd1c0cSTimur Tabilives). The first subwindow after the end of guest memory is used for 1092bcd1c0cSTimur Tabithis. The address specified in the msi-address-64 property is the PCI 1102bcd1c0cSTimur Tabiaddress of MSIIR. The hypervisor configures the PAMU to map that address to 1112bcd1c0cSTimur Tabithe true physical address of MSIIR. 112