Home
last modified time | relevance | path

Searched refs:reg_write (Results 1 – 25 of 246) sorted by relevance

12345678910

/openbmc/linux/arch/x86/pci/
H A Dce4100.c66 static void reg_write(struct sim_dev_reg *reg, u32 value) in reg_write() function
104 DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write)
105 DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write)
106 DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
107 DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
108 DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
109 DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write)
110 DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write)
111 DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write)
112 DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
[all …]
/openbmc/u-boot/board/micronas/vct/
H A Debi_onenand.c16 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr)); in ebi_nand_read_word()
25 reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16)); in ebi_nand_write_word()
26 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), in ebi_nand_write_word()
36 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); in ebi_init_onenand()
38 reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002); in ebi_init_onenand()
39 reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); in ebi_init_onenand()
41 reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002); in ebi_init_onenand()
42 reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */ in ebi_init_onenand()
44 reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000); in ebi_init_onenand()
45 reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000); in ebi_init_onenand()
[all …]
H A Debi_smc911x.c16 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020); in ebi_init_smc911x()
17 reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); in ebi_init_smc911x()
19 reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100); in ebi_init_smc911x()
20 reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111); in ebi_init_smc911x()
22 reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000); in ebi_init_smc911x()
23 reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF); in ebi_init_smc911x()
25 reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100); in ebi_init_smc911x()
26 reg_write(EBI_DEV1_TIM1_WR2(EBI_BASE), 0x3FC21110); in ebi_init_smc911x()
40 reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); in smc911x_reg_read()
42 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); in smc911x_reg_read()
[all …]
H A Debi_nor_flash.c14 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr); in ebi_read()
28 reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val); in ebi_write_u16()
29 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), in ebi_write_u16()
64 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); in ebi_init_nor_flash()
66 reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002); in ebi_init_nor_flash()
67 reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); in ebi_init_nor_flash()
69 reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113); in ebi_init_nor_flash()
70 reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000); in ebi_init_nor_flash()
71 reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x04003113); in ebi_init_nor_flash()
72 reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC12011); in ebi_init_nor_flash()
[all …]
/openbmc/linux/drivers/firewire/
H A Dinit_ohci1394_dma.c40 static inline void reg_write(const struct ohci *ohci, int offset, u32 data) in reg_write() function
58 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000); in get_phy_reg()
75 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000); in set_phy_reg()
89 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); in init_ohci1394_soft_reset()
114 reg_write(ohci, OHCI1394_BusOptions, bus_options); in init_ohci1394_initialize()
117 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0); in init_ohci1394_initialize()
120 reg_write(ohci, OHCI1394_HCControlSet, in init_ohci1394_initialize()
124 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); in init_ohci1394_initialize()
127 reg_write(ohci, OHCI1394_LinkControlSet, in init_ohci1394_initialize()
131 reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400); in init_ohci1394_initialize()
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c315 reg_write(CPU_AVS_CONTROL0_REG, tmp2); in serdes_phy_config()
333 reg_write(CORE_AVS_CONTROL_0REG, core_avs); in serdes_phy_config()
339 reg_write(CORE_AVS_CONTROL_2REG, core_avs); in serdes_phy_config()
346 reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2); in serdes_phy_config()
351 reg_write(CPU_AVS_CONTROL2_REG, cpu_avs); in serdes_phy_config()
369 reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111); in serdes_phy_config()
373 reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */ in serdes_phy_config()
375 reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */ in serdes_phy_config()
377 reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */ in serdes_phy_config()
379 reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */ in serdes_phy_config()
[all …]
/openbmc/linux/drivers/media/i2c/
H A Drj54n1cb0c.c446 static int reg_write(struct i2c_client *client, const u16 reg, in reg_write() function
472 return reg_write(client, reg, (ret & ~mask) | (data & mask)); in reg_set()
481 ret = reg_write(client, rv->reg, rv->val); in reg_write_multiple()
515 ret = reg_write(client, reg_xy, in rj54n1_set_rect()
520 ret = reg_write(client, reg_x, width & 0xff); in rj54n1_set_rect()
522 ret = reg_write(client, reg_y, height & 0xff); in rj54n1_set_rect()
533 int ret = reg_write(client, RJ54N1_INIT_START, 1); in rj54n1_commit()
536 ret = reg_write(client, RJ54N1_INIT_START, 0); in rj54n1_commit()
725 ret = reg_write(client, RJ54N1_RESIZE_HOLD_L, resize & 0xff); in rj54n1_sensor_scale()
727 ret = reg_write(client, RJ54N1_RESIZE_HOLD_H, resize >> 8); in rj54n1_sensor_scale()
[all …]
/openbmc/u-boot/board/Synology/ds414/
H A Dds414.c133 reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW); in board_early_init_f()
134 reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID); in board_early_init_f()
135 reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH); in board_early_init_f()
138 reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW); in board_early_init_f()
139 reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID); in board_early_init_f()
140 reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH); in board_early_init_f()
143 reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW); in board_early_init_f()
144 reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID); in board_early_init_f()
145 reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH); in board_early_init_f()
148 reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]); in board_early_init_f()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c78 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
91 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_write_leveling_hw()
164 reg_write(REG_DUNIT_CTRL_LOW_ADDR, reg); in ddr3_write_leveling_hw()
223 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_wl_supplement()
226 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_wl_supplement()
258 reg_write(REG_DRAM_TRAINING_2_ADDR, in ddr3_wl_supplement()
403 reg_write(REG_DRAM_TRAINING_2_ADDR, in ddr3_wl_supplement()
453 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_wl_supplement()
457 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_wl_supplement()
[all …]
H A Dddr3_init.c159 reg_write((win_ctrl_reg + 0x4 * ui), win_backup[ui]); in ddr3_restore_and_set_final_windows()
165 reg_write(0x8c04, 0x40000000); in ddr3_restore_and_set_final_windows()
175 reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg); in ddr3_restore_and_set_final_windows()
179 reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg); in ddr3_restore_and_set_final_windows()
192 reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg); in ddr3_restore_and_set_final_windows()
205 reg_write(0x8c04, 0); in ddr3_save_and_set_training_windows()
222 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); in ddr3_save_and_set_training_windows()
250 reg_write(win_ctrl_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
253 reg_write(win_base_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
257 reg_write(win_remap_reg + in ddr3_save_and_set_training_windows()
[all …]
H A Dxor.c41 reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg); in mv_sys_xor_init()
45 reg_write(XOR_BASE_ADDR_REG(0, dram_info->num_cs), base); in mv_sys_xor_init()
47 reg_write(XOR_SIZE_MASK_REG(0, dram_info->num_cs), 0x03FF0000); in mv_sys_xor_init()
71 reg_write(XOR_BASE_ADDR_REG(0, cs_count), base); in mv_sys_xor_init()
74 reg_write(XOR_SIZE_MASK_REG(0, cs_count), 0x0FFF0000); in mv_sys_xor_init()
88 reg_write(XOR_WINDOW_CTRL_REG(0, 0), xor_regs_ctrl_backup); in mv_sys_xor_finish()
90 reg_write(XOR_BASE_ADDR_REG(0, ui), xor_regs_base_backup[ui]); in mv_sys_xor_finish()
92 reg_write(XOR_SIZE_MASK_REG(0, ui), xor_regs_mask_backup[ui]); in mv_sys_xor_finish()
94 reg_write(XOR_ADDR_OVRD_REG(0, 0), 0); in mv_sys_xor_finish()
149 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl); in mv_xor_ctrl_set()
[all …]
H A Dddr3_spd.c776 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
783 reg_write(REG_DUNIT_CTRL_LOW_ADDR, reg);
849 reg_write(REG_SDRAM_TIMING_LOW_ADDR, reg);
863 reg_write(REG_SDRAM_TIMING_HIGH_ADDR, reg);
932 reg_write(REG_SDRAM_ADDRESS_CTRL_ADDR, reg);
940 reg_write(REG_SDRAM_OPERATION_ADDR, reg);
944 reg_write(REG_SDRAM_EXT_MODE_ADDR, reg);
952 reg_write(REG_DDR_CONT_HIGH_ADDR, reg);
959 reg_write(0x142C, reg);
964 reg_write(REG_MBUS_CPU_BLOCK_ADDR, 0x0000E907);
[all …]
H A Dddr3_hw_training.c109 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_hw_training()
541 reg_write(REG_SDRAM_TIMING_HIGH_ADDR, reg); in ddr3_set_performance_params()
562 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
564 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
583 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
585 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
603 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_read_pup_reg()
606 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_read_pup_reg()
629 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_load_patterns()
632 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_load_patterns()
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dqm1d1c0042.c64 static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val) in reg_write() function
107 return reg_write(state, 0x03, state->regs[0x03]); in qm1d1c0042_set_srch_mode()
117 ret = reg_write(state, 0x01, state->regs[0x01]); in qm1d1c0042_wakeup()
119 ret = reg_write(state, 0x05, state->regs[0x05]); in qm1d1c0042_wakeup()
205 ret = reg_write(state, 0x02, val); in qm1d1c0042_set_params()
213 ret = reg_write(state, 0x06, state->regs[0x06]); in qm1d1c0042_set_params()
219 ret = reg_write(state, 0x07, state->regs[0x07]); in qm1d1c0042_set_params()
230 ret = reg_write(state, 0x08, val); in qm1d1c0042_set_params()
251 ret = reg_write(state, 0x09, state->regs[0x09]); in qm1d1c0042_set_params()
253 ret = reg_write(state, 0x0a, state->regs[0x0a]); in qm1d1c0042_set_params()
[all …]
/openbmc/linux/drivers/media/usb/gspca/
H A Dspca505.c533 static int reg_write(struct gspca_dev *gspca_dev, in reg_write() function
577 ret = reg_write(gspca_dev, data[i][0], data[i][2], in write_vector()
619 reg_write(gspca_dev, 0x05, 0x00, (255 - brightness) >> 6); in setbrightness()
620 reg_write(gspca_dev, 0x05, 0x01, (255 - brightness) << 2); in setbrightness()
651 ret = reg_write(gspca_dev, 0x06, 0x16, 0x0a); in sd_start()
654 reg_write(gspca_dev, 0x05, 0xc2, 0x12); in sd_start()
659 reg_write(gspca_dev, 0x02, 0x00, 0x00); in sd_start()
662 reg_write(gspca_dev, SPCA50X_REG_COMPRESS, 0x00, mode_tb[mode][0]); in sd_start()
663 reg_write(gspca_dev, SPCA50X_REG_COMPRESS, 0x06, mode_tb[mode][1]); in sd_start()
664 reg_write(gspca_dev, SPCA50X_REG_COMPRESS, 0x07, mode_tb[mode][2]); in sd_start()
[all …]
H A Dspca508.c1231 static int reg_write(struct gspca_dev *gspca_dev, u16 index, u16 value) in reg_write() function
1278 ret = reg_write(gspca_dev, 0x8802, reg >> 8); in ssi_w()
1281 ret = reg_write(gspca_dev, 0x8801, reg & 0x00ff); in ssi_w()
1285 ret = reg_write(gspca_dev, 0x8805, val & 0x00ff); in ssi_w()
1290 ret = reg_write(gspca_dev, 0x8800, val); in ssi_w()
1325 ret = reg_write(gspca_dev, (*data)[1], in write_vector()
1393 reg_write(gspca_dev, 0x8500, mode); in sd_start()
1397 reg_write(gspca_dev, 0x8700, 0x28); /* clock */ in sd_start()
1402 reg_write(gspca_dev, 0x8700, 0x23); /* clock */ in sd_start()
1405 reg_write(gspca_dev, 0x8112, 0x10 | 0x20); in sd_start()
[all …]
H A Dspca501.c1745 static int reg_write(struct gspca_dev *gspca_dev, in reg_write() function
1769 ret = reg_write(gspca_dev, data[i][0], data[i][2], in write_vector()
1783 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x12, val); in setbrightness()
1788 reg_write(gspca_dev, 0x00, 0x00, (val >> 8) & 0xff); in setcontrast()
1789 reg_write(gspca_dev, 0x00, 0x01, val & 0xff); in setcontrast()
1794 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x0c, val); in setcolors()
1799 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x11, val); in setblue_balance()
1804 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x13, val); in setred_balance()
1880 reg_write(gspca_dev, SPCA50X_REG_USB, 0x6, 0x94); in sd_start()
1883 reg_write(gspca_dev, SPCA50X_REG_USB, 0x07, 0x004a); in sd_start()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dxor.c46 reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg); in mv_sys_xor_init()
81 reg_write(XOR_BASE_ADDR_REG(0, ui), (u32)base); in mv_sys_xor_init()
85 reg_write(XOR_SIZE_MASK_REG(0, ui), (u32)size_mask); in mv_sys_xor_init()
98 reg_write(XOR_WINDOW_CTRL_REG(0, 0), ui_xor_regs_ctrl_backup); in mv_sys_xor_finish()
100 reg_write(XOR_BASE_ADDR_REG(0, ui), in mv_sys_xor_finish()
103 reg_write(XOR_SIZE_MASK_REG(0, ui), in mv_sys_xor_finish()
106 reg_write(XOR_ADDR_OVRD_REG(0, 0), 0); in mv_sys_xor_finish()
160 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl); in mv_xor_ctrl_set()
188 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); in mv_xor_mem_init()
194 reg_write(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), start_ptr); in mv_xor_mem_init()
[all …]
/openbmc/linux/drivers/media/platform/st/stm32/dma2d/
H A Ddma2d-hw.c24 static inline void reg_write(void __iomem *base, u32 reg, u32 val) in reg_write() function
32 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); in reg_update_bits()
49 reg_write(d->regs, DMA2D_IFCR_REG, isr_val & 0x003f); in dma2d_clear_int()
58 reg_write(d->regs, DMA2D_NLR_REG, (width << 16) | height); in dma2d_config_common()
75 reg_write(d->regs, DMA2D_OMAR_REG, o_addr); in dma2d_config_out()
77 reg_write(d->regs, DMA2D_OCOLR_REG, in dma2d_config_out()
90 reg_write(d->regs, DMA2D_FGMAR_REG, f_addr); in dma2d_config_fg()
105 reg_write(d->regs, DMA2D_FGCOLR_REG, in dma2d_config_fg()
114 reg_write(d->regs, DMA2D_BGMAR_REG, b_addr); in dma2d_config_bg()
129 reg_write(d->regs, DMA2D_BGCOLR_REG, in dma2d_config_bg()
/openbmc/linux/drivers/gpu/drm/i2c/
H A Dtda998x_drv.c651 reg_write(struct tda998x_priv *priv, u16 reg, u8 val) in reg_write() function
695 reg_write(priv, reg, old_val | val); in reg_set()
705 reg_write(priv, reg, old_val & ~val); in reg_clear()
712 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); in tda998x_reset()
714 reg_write(priv, REG_SOFTRESET, 0); in tda998x_reset()
722 reg_write(priv, REG_PLL_SERIAL_1, 0x00); in tda998x_reset()
723 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); in tda998x_reset()
724 reg_write(priv, REG_PLL_SERIAL_3, 0x00); in tda998x_reset()
725 reg_write(priv, REG_SERIALIZER, 0x00); in tda998x_reset()
726 reg_write(priv, REG_BUFFER_OUT, 0x00); in tda998x_reset()
[all …]
/openbmc/linux/drivers/base/regmap/
H A Dregmap-mmio.c25 void (*reg_write)(struct regmap_mmio_context *ctx, member
162 ctx->reg_write(ctx, reg, val); in regmap_mmio_write()
399 .reg_write = regmap_mmio_write,
451 ctx->reg_write = regmap_mmio_iowrite8; in regmap_mmio_gen_context()
454 ctx->reg_write = regmap_mmio_write8_relaxed; in regmap_mmio_gen_context()
457 ctx->reg_write = regmap_mmio_write8; in regmap_mmio_gen_context()
463 ctx->reg_write = regmap_mmio_iowrite16le; in regmap_mmio_gen_context()
466 ctx->reg_write = regmap_mmio_write16le_relaxed; in regmap_mmio_gen_context()
469 ctx->reg_write = regmap_mmio_write16le; in regmap_mmio_gen_context()
475 ctx->reg_write = regmap_mmio_iowrite32le; in regmap_mmio_gen_context()
[all …]
/openbmc/linux/drivers/net/dsa/
H A Dmv88e6060.c22 static int reg_write(struct mv88e6060_priv *priv, int addr, int reg, u16 val) in reg_write() function
63 ret = reg_write(priv, REG_PORT(i), PORT_CONTROL, in mv88e6060_switch_reset()
73 ret = reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL, in mv88e6060_switch_reset()
105 ret = reg_write(priv, REG_GLOBAL, GLOBAL_CONTROL, in mv88e6060_setup_global()
112 return reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL, in mv88e6060_setup_global()
129 ret = reg_write(priv, addr, PORT_CONTROL, in mv88e6060_setup_port()
143 ret = reg_write(priv, addr, PORT_VLAN_MAP, in mv88e6060_setup_port()
156 return reg_write(priv, addr, PORT_ASSOC_VECTOR, BIT(p)); in mv88e6060_setup_port()
174 ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_01, val); in mv88e6060_setup_addr()
178 ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_23, in mv88e6060_setup_addr()
[all …]
/openbmc/linux/drivers/media/pci/tw686x/
H A Dtw686x-core.c108 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en); in tw686x_disable_channel()
109 reg_write(dev, DMA_CMD, dma_cmd); in tw686x_disable_channel()
133 reg_write(dev, DMA_CHANNEL_ENABLE, dev->pending_dma_en); in tw686x_dma_delay()
134 reg_write(dev, DMA_CMD, dev->pending_dma_cmd); in tw686x_dma_delay()
156 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en & ~ch_mask); in tw686x_reset_channels()
162 reg_write(dev, DMA_CMD, dma_cmd & ~ch_mask); in tw686x_reset_channels()
300 reg_write(dev, SYS_SOFT_RST, 0x0f); in tw686x_probe()
303 reg_write(dev, SRST[0], 0x3f); in tw686x_probe()
305 reg_write(dev, SRST[1], 0x3f); in tw686x_probe()
308 reg_write(dev, DMA_CMD, 0); in tw686x_probe()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dmxc_spi.c35 #define reg_write(a, v) writel(v, a) macro
146 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
148 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
202 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
204 reg_write(&regs->cfg, reg_config); in spi_cfg_mxc()
211 reg_write(&regs->intr, 0); in spi_cfg_mxc()
212 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
234 reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); in spi_xchg_single()
236 reg_write(&regs->cfg, mxcs->cfg_reg); in spi_xchg_single()
240 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
[all …]
/openbmc/linux/drivers/soundwire/
H A Dqcom.c209 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val); member
454 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); in qcom_swrm_cmd_fifo_wr_cmd()
494 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); in qcom_swrm_cmd_fifo_rd_cmd()
511 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, in qcom_swrm_cmd_fifo_rd_cmd()
513 ctrl->reg_write(ctrl, in qcom_swrm_cmd_fifo_rd_cmd()
713 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
740 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
749 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
756 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
766 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
[all …]

12345678910